JP2962352B2 - Bit weight order display / connection validity check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Regarding the connection validity check method, in particular, a printed circuit board or an LSI (Large S
The present invention relates to a method of displaying a bit weight order and a connection validity check when designing a circuit diagram by using a circuit diagram input system.

[0002]

2. Description of the Related Art Hitherto, a circuit diagram input system for a printed circuit board or an LSI does not have a function of displaying the bit weight order of symbols or a function of judging the validity of a connection in consideration of the bit weight. Here, the bit weight order of the symbols is, for example, as shown in FIG. 5, a 4-bit pin group A (0) to
When there are A (3) and pin groups B (0) to B (3),
Pin groups A (0) to A (3) and pin groups B (0) to B (3)
Is an order indicating whether 4-bit data should be allocated from the lower bit or from the upper bit. Pin groups A (0) to A (3) and pin groups B (0) to B
The numbers in parentheses in (3) are suffixes indicating bit positions, such as pin groups A (0) to A (3) and pin groups B (0) to B (B).
When bits of data are assigned in ascending order to subscripts in (3), the bit weight order is called ascending, and pin groups A (0) to A (3) and pin groups B (0) to B ( When data bits are assigned in ascending order of subscripts to 3) in descending order, the bit weight order is said to be in descending order. Note that the bit weight order is originally an attribute for a series of pin groups, but since the bit weight order different for each pin group within the same symbol causes confusion, the bit weight order within the same symbol is Are unified into one.

[0005] The validity of the connection in consideration of the bit weight is, for example, as shown in FIG.
When there are (0) to A (3) and pin groups B (0) to B (3), the bit weights of the pin groups A (0) to A (3) are in descending order, and the pin group B ( If the bit weight order of 0) to B (3) is ascending, even if the pin A (0) and the pin B (0) are connected, the most significant bit and the least significant bit remain as data bits. Is connected, which means that it is not appropriate.

An example of a conventional circuit element connection search method in circuit diagram design is described in Japanese Patent Application Laid-Open No. 5-225286. As shown in FIG. 6, the circuit element connection search method includes an input / output device 1 for analyzing an input signal, a data storage device 2 for storing data, a connection path extraction unit 5 and a circuit diagram display unit 6, The circuit comprises a circuit element connection search means 4 for searching for a connection path of an element, and an arithmetic processing unit 2 for instructing data storage and circuit element connection search.
The connection path between the circuit elements is automatically extracted and the circuit elements and signal lines of the connection path are highlighted.

[0005]

A first problem is that in the prior art, it is not possible to display how the bit weight order is allocated. The reason is that information indicating the bit weight order is not registered in an information file necessary for designing a circuit diagram of a printed circuit board or LSI.

A second problem is that, in the prior art, a connection path can be searched, but it cannot be determined whether or not the connection is correct in terms of bit weight. The reason is that information indicating the bit weight order is not registered in an information file necessary for designing a circuit board of a printed circuit board or an LSI, and it is not possible to determine whether or not the connection is correct, and there is no mechanism for determining. is there.

An object of the present invention is to provide a bit weight order display / connection validity check method for displaying a bit weight order of a symbol registered in advance when a symbol is arranged on a circuit diagram input system. It is in.

Another object of the present invention is to provide a bit weight order display / connection validity check system for checking whether or not the connection relation is valid in terms of bit weight after connection between an input pin and an output pin on a circuit diagram input system. Is to provide.

[0009]

A bit weight order display / connection validity check method according to the present invention displays a bit weight order of a series of bits in a symbol for each symbol of a circuit diagram in a circuit diagram input system. And a bit weight check unit for checking the validity of the connection in consideration of the bit weight.

The bit weight order display / connection validity check method of the present invention is registered in advance in a circuit diagram input system when a symbol is arranged at a designated position in accordance with an externally input symbol arrangement instruction. It checks whether the bit weight order of the arranged symbols is given in ascending order or descending order from the information that has been assigned, and displays bit weight order display means for displaying the bit weight order, and externally when operating in real time. When wiring is performed in accordance with the input wiring instruction, it is checked whether or not the pins are connected as a result of the wiring, and the bit weight order of the symbol to which each connected pin belongs and the bit number of the pin To determine if the connection between pins is valid due to the weight of the bit.If not, display an error mark and operate in batch processing. If so, select one unchecked pin, find all the pins connected to the selected pin, and make the connection between the selected pin and all the found pins appropriate for the bit weight. Bit weight checking means for judging whether or not it is not appropriate, and displaying an error mark when the judgment is not appropriate.

Further, the machine-readable recording medium according to the present invention is arranged such that a computer arranges a symbol at a designated position in accordance with an externally input symbol arrangement instruction, and sets a bit weight of the arranged symbol based on information registered in advance. It is checked whether the order is given in ascending order or descending order, and bit weight order display means for displaying the bit weight order, and when operating in real time, wiring is performed in accordance with an externally input wiring instruction. When the wiring is completed, it is checked whether the pins are connected as a result of the wiring, the bit weight order of the symbol to which each connected pin belongs and the bit number of the pin are checked, and the connection between the pins is Judge whether the weight is appropriate, display an error mark if it is not appropriate, and check if it is operating in batch processing. Select one pin that is not, find all the pins connected to the selected pin, determine whether the connection between the selected pin and all the found pins is bit-weighted, and if not, Records a program for functioning as bit weight checking means for displaying an error mark.

[0012]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a bit weight order display / connection validity check system according to a first embodiment of the present invention. The bit weight order display / connection validity check method according to the present embodiment includes an input / output device 1, an arithmetic processing unit 2, a data storage device 3, a bit weight order display unit 4, a bit weight check unit 5, , The main part is constituted.

The bit weight check means 5 traces from the selected pin to find all the pins connected to the selected pin, and determines whether the connection between the pins is appropriate as a bit weight. And an error mark display unit 8 that displays an error mark on a connection between pins determined to be invalid by the connection correctness / incorrectness determination unit 7.

Referring to FIG. 2, the processing of the bit weight order display means 4 includes a symbol arrangement step S1 and a bit weight order display step S2.

Referring to FIG. 3 (a), when the bit weight checking means 5 is executed in real time, the processing includes a wiring step S3, an inter-pin connection determination step S4, a connection validity determination step S5, an error mark It consists of a display step S6.

Referring to FIG. 3 (b), when the bit weight checking means 5 is implemented in a batch process, the process includes an unchecked pin selection step S3 ', an all connection pin trace step S4', and a connection validity judgment. It comprises a step S5 and an error mark display step S6.

Next, the operation of the bit weight order display / connection validity check system according to the first embodiment configured as described above will be described.

The arithmetic processing unit 2 analyzes an input signal from the input / output unit 1 and stores data in the data storage unit 3 in the case of a data storage instruction. In this manner, information files (not shown) necessary for circuit diagram design are created in the data storage device 3. In particular, the bit weight order of the symbols is stored in the designation field of the symbol library.

The arithmetic processing unit 2 analyzes an input signal from the input / output device 1 and, in the case of a symbol arrangement instruction, acquires information on the symbol from the data storage device 3 and arranges the symbol. .

When the symbols are arranged according to the symbol arrangement instruction (step S1), the bit weight order display means 4
Acquires the bit weight order of the symbols arranged in step S1 from the data storage device 3 and displays the bit weight order of the symbols (step S2).

Further, the arithmetic processing unit 2 includes an input / output unit 1
In the case of a wiring instruction, the information of the designated pin is obtained from the data storage device 3 and wiring between the pins is performed.

When the bit weight checking means 5 is operating in real time, if wiring is performed according to a wiring instruction (step S3), the bit weight checking means 5 is operated.
Determines whether or not the pins are connected by the wiring performed in step S3 (step S4). If not connected, the bit weight checking means 5
If the connection is made in the external input waiting state and the connection is made, the connection correct / incorrect judgment unit 7 judges whether the connection between the connected pins is a proper connection in terms of the bit weight in consideration of the bit weight order of the symbol ( Step S5). If the connection is valid, the bit weight checking unit 5 waits for an external input. If the connection is not valid, the error mark display unit 8 displays an error mark on the wiring between the pins (step S6). , And waits for an external input.

When the bit weight checking means 5 is operating in batch processing, if one pin which has not been checked is selected (step S3 '), the bit weight checking means 5 causes the connection destination trace section 6 to operate. As a result, trace is performed from the pin selected in step S3 'to find all connected pins (step S4'). Subsequently, the bit weight checking means 5 causes the connection correct / incorrect judgment section 7 to consider the bit weight order of the symbol in step S
It is determined whether or not the connection between the pin selected in 3 'and all the pins found in step S4' is appropriate in terms of bit weight (step S5). If the connection is valid, the bit weight checking means 5 returns the control to step S3 ', and if the connection is not valid, the error mark display unit 8
Displays an error mark on the wiring that is not a proper connection, and returns the control to step S3 '.

FIG. 4 is a block diagram showing a configuration of a bit weight order display / connection validity check system according to a second embodiment of the present invention. The bit weight order display / connection validity check method according to the present embodiment is different from the bit weight order display / connection validity check method according to the first embodiment for the bit weight order display / connection validity check method. It is provided with a recording medium 9 on which a program is recorded. The recording medium 9 may be a magnetic disk, a semiconductor memory, or another recording medium. The other means are the same as the means in the bit weight order display / connection validity check method according to the first embodiment. The detailed description of is omitted.

In the bit weight order display / connection validity check method according to the second embodiment configured as described above,
The bit weight order display / connection validity check program is read from the recording medium 9 into the arithmetic processing unit 2 and executes processing as the bit weight order display means 4 and the connection validity check means 5. The detailed operations are exactly the same as those in the case of the bit weight order display / connection validity check method according to the first embodiment, and a detailed description thereof will be omitted.

[0027]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the bit weight order display / connection validity check method according to the present invention is an input / output device 1, an arithmetic processing unit 2, a data storage device 3, a bit weight order display. The main part is constituted by the means 4 and the bit weight checking means 5.

The bit weight check means 5 traces from the selected pin to find all the pins connected to the selected pin, and determines whether the connection between the pins is appropriate in terms of bit weight. And an error mark display unit 8 that displays an error mark on a connection between pins determined to be invalid by the connection correctness / incorrectness determination unit 7.

Referring to FIG. 2, the processing of the bit weight order display means 4 includes a symbol arrangement step S1 and a bit weight order display step S2.

Referring to FIG. 3 (a), when the bit weight checking means 5 is executed in real time, the processing is performed by a wiring step S3, a pin connection determination step S4, a connection validity determination step S5, an error mark It consists of a display step S6.

Referring to FIG. 3 (b), when the bit weight checking means 5 is implemented in a batch process, the process is a non-check pin selection step S3 ', an all connection pin trace step S4', and a connection validity judgment. It comprises a step S5 and an error mark display step S6.

FIG. 5 is a diagram showing an example of the bit weight order and the error mark displayed by the bit weight order display / connection validity check method of this embodiment. In FIG. 5, “down” and “ascending” displayed above each symbol indicate the bit weight order. Further, “x” given on the wiring connecting the pins indicates an error mark. Note that L001,
L002 and L003 indicate symbol names, and A (0)
~ A (3), B (0) ~ B (3), C (0) ~ C
(7), D (0) to D (7) indicate logical pin names. The number in parentheses of the logical pin name indicates the bit position of the pin, and does not indicate the bit weight order.

Next, the operation of the bit weight order display / connection validity check system of the present embodiment configured as described above will be described.

The processing unit 2 analyzes an input signal from the input / output unit 1 and stores data in the data storage unit 3 in the case of a data storage instruction. In this manner, information files (not shown) necessary for circuit diagram design are created in the data storage device 3. In particular, the symbol L00
It is assumed that the bit weighting order is stored as “descending”, “ascending”, and “descending” in the designation fields of the libraries L1, L002, and L003.

The arithmetic processing unit 2 analyzes an input signal from the input / output device 1 and, in the case of a symbol arrangement instruction, acquires information on the symbol from the data storage device 3 and arranges the symbol. . For example, as shown in FIG.
It is assumed that symbols L001, L002, and L003 are arranged.

According to the symbol arrangement instruction, the symbol L00
When 1, L002 and L003 are arranged (Step S1), the bit weight order display means 4 changes the bit weight order of the symbols L001, L002, and L003 arranged in Step S1 to "Down", "Up", and "Down". Obtained from the data storage device 3, the bits L001, L002, and L003 are displayed in the order of bit weight “lower”, “rising”, and “lower”, respectively (step S2).

Further, the arithmetic processing unit 2 includes an input / output unit 1
In the case of a wiring instruction, the information of the designated pin is obtained from the data storage device 3 and wiring between the pins is performed. For example, as shown in FIG.
It is assumed that wiring between (0) and pin B (0) has been performed.

When the bit weight checking means 5 is operating in real time, the pin A
When wiring is performed between (0) and the pin B (0) (Step S3), the bit weight checking means 5 sets
It is determined whether the pin A (0) and the pin B (0) are connected by the wiring performed in step 3 (step S4). If not connected, the bit weight checking means 5
Are in a state of waiting for an external input, and when the connection is established, the connection correct / incorrect judgment unit 7 sets the symbols L001 and L002
It is determined whether or not the connection between the pin A (0) and the pin B (0) connected in consideration of the bit weight order is an appropriate connection in terms of bit weight (step S5). Symbol L001
Is “descending” and the bit weighting order of the symbol L002 is “ascending”.
Even if the pin A (0) and the pin B (0) are connected, since the most significant bit and the least significant bit are connected as data bits, it is determined that the connection is not proper. Therefore, the bit weight checking means 5 displays an error mark "x" on the wiring between the pin A (0) and the pin B (0) by the error mark display section 8 (step S6), and waits for an external input. Becomes It is needless to say that the error mark “x” is not displayed for a proper connection.

When the bit weight checking means 5 is operating in batch processing, if one pin which has not been checked is selected (step S3 '), the bit weight checking means 5 sets the connection destination trace. The unit 6 traces all the connected pins by tracing from the pin selected in step S3 '(step S4'). Subsequently, the bit weight checking means 5 causes the connection correct / incorrect judgment section 7 to consider the bit weight order of the symbol in step S
It is determined whether or not the connection between the pin selected in 3 'and all the pins found in step S4' is appropriate in terms of bit weight (step S5). If the connection is valid, the bit weight checking means 5 returns the control to step S3 ', and if the connection is not valid, the error mark display unit 8
Error mark “×” on wiring that is not proper connection due to
Is displayed, and the control returns to step S3 '.

As described above, in this embodiment, since the bit weight order of each symbol is displayed by the bit weight order display means 4, wiring can be performed while checking the bit weight order, and connection errors can be prevented beforehand. . In addition, the bit weight checking means 5 detects an error even if a wrong connection is performed in terms of bit weight, so that a connection error can be prevented.

[0042]

A first effect is that whether the bit weight order of each symbol is ascending or descending is displayed. As a result, the pins can be correctly connected in terms of bit weight. The reason is that wiring can be performed while checking the weight order of bits.

A second effect is that it is checked whether or not the connection between pins is valid in terms of bit weight, and an error mark is displayed for an invalid connection. As a result, there is no possibility of a connection error relating to the bit weight.
The reason is that it is easy to find the connection with the error mark, change the connection, and repeat the check and the connection change until the error disappears.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a bit weight order display / connection validity check method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of a bit weight order display means in FIG. 1;

3 is a flowchart showing an operation of a bit weight check unit in FIG. 1, wherein (a) shows a case where a connection validity check is performed in real time, and (b) shows a case where a connection validity check is performed by batch processing; The following shows the case.

FIG. 4 is a block diagram showing a configuration of a bit weight order display / connection validity check method according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a bit weight order and an error mark displayed by a bit weight order display / connection validity check method according to an embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 I / O device 2 Arithmetic processing unit 3 Data storage device 4 Bit weight order display means 5 Bit weight check means 6 Connection destination trace part 7 Connection correctness judgment part 8 Error mark display part 9 Recording medium

Claims (6)

(57) [Claims] In a circuit diagram input system, a bit weight order display means for displaying a bit weight order of a series of pins in a symbol for each symbol of a circuit diagram, and a connection validity in consideration of a bit weight is checked. And a bit weight order display / connection validity check method. 2. The bit weight order display / connection validity according to claim 1, wherein the bit weight order display means displays the bit weight order of the symbol registered in advance for the arranged symbol. Check method. 3. The bit weight checking means determines the number of each bit of the connected pins from information registered in advance, and determines whether the connection is appropriate in terms of the bit weight. And displaying an error mark when the connection is not a valid connection.
Connection validity check method. 4. A connection destination trace section in which the bit weight check means traces from a selected pin to find all pins connected to the selected pin, and whether a connection between the pins is appropriate in terms of bit weight. 2. The bit weight order display / connection according to claim 1, further comprising: a connection correct / incorrect judgment unit for judging whether the connection is correct, and an error mark display unit for displaying an error mark on a connection between pins determined to be invalid by the connection correct / incorrect judgment unit. Validity check method. 5. In a circuit diagram input system, when a symbol is arranged at a designated position in accordance with an externally input symbol arrangement instruction, the bit weighting order of the arranged symbols is increased in ascending order /
Bit weight order display means for checking which one is assigned in descending order and displaying the bit weight order, and when operating in real time, when wiring is performed according to an externally input wiring instruction, As a result of the wiring, it is checked whether or not the pins are connected to each other, and the bit weight order of the symbol to which each connected pin belongs and the bit number of the pin are checked. Judge whether it is not appropriate, display an error mark if it is not appropriate, and when operating in batch processing, select one unchecked pin and check all pins connected to the selected pin Bit weight checking means for determining whether or not connections between selected pins and all found pins are valid in terms of bit weight, and displaying an error mark if not valid And a bit weight order display / connection validity check method. 6. A computer according to claim 1, further comprising: arranging a symbol at a designated position in accordance with a symbol arrangement instruction input from the outside;
Bit weight order display means for checking whether the bit weight order of the arranged symbols is assigned in ascending order or descending order from the information registered in advance, and a bit weight order display means for displaying the bit weight order. When wiring is performed according to a wiring instruction input from the outside, it is checked whether or not the pins are connected as a result of the wiring, and the bit weight order of the symbol to which each connected pin belongs and the The bit is checked to determine whether the connection between the pins is valid due to the weight of the bit. If the connection is not valid, an error mark is displayed. Select a pin, find all the pins connected to the selected pin, and check if the connection between the selected pin and all the found pins is valid for the bit weight. Determine, if not valid records a program for functioning as bit weight check means for displaying the error mark machine-readable recording medium.