JP2963282B2 - Sense circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense circuit for a dynamic circuit.

[0002]

2. Description of the Related Art Conventionally, register files, RAM, RO
A dynamic circuit has been used as a configuration of a large-scale circuit requiring high-speed operation such as M and PLA. The dynamic circuit has a data line that is precharged to a predetermined potential, and a sense circuit is used to detect the potential of the data line.

As a conventional dynamic circuit, a register file read circuit will be described with reference to FIG. FIG. 7 is a circuit diagram for explaining a sense circuit of a conventional dynamic circuit. In FIG. 7, reference numeral 701 denotes a memory cell in a register file.
OSFETs 701a and 701b and latch circuit 701
c. Reference numeral 702 denotes a precharge circuit formed of a P-channel MOSFET, and reference numeral 703 denotes an inverter circuit serving as a sense circuit.

In the conventional dynamic circuit configured as described above, the bit line 711 is controlled by controlling the precharge enable line 712 of the precharge circuit 702.
Is precharged to a high potential (hereinafter abbreviated as “H”), and when the word line 713 of the memory cell 701 is set to “H”, the potential of the bit line 711 is determined based on the contents of the memory cell 701. Is done.

When the content of the memory cell 701 is "H", the bit line 711 is discharged to a low potential (hereinafter abbreviated as "L"). When the content of the memory cell 701 is "L", there is no current path for discharging, so that the bit line 711 remains "H". Then, the content of the memory cell 701 is output by outputting the logical inversion signal of the bit line 711 to the sense output line 714 by the inverter circuit 703.

[0006]

However, in the conventional dynamic circuit configured as described above, when data is read, the MOSFET 701 in the memory cell 701 is read.
The bit line 711 was discharged by using only a and 701b. Usually, for the purpose of reducing the memory cell area, a MOSFET 7 having a small gate width is provided in the memory cell 701.
01a and 701b and the two are connected in series, the discharge time of the bit line 711 becomes longer. In particular, in applications such as microprocessors, the length of the data line such as the bit line 711 is increased due to the enlargement of the circuit, and a plurality of cells are connected to increase the load capacitance and wiring resistance of the data line. The time was getting longer and longer.

As a result, there is a problem that the delay time from the time when the word line 713 is set to the "H" level to the time when the logic level of the sense output line 714 is determined becomes longer, and the sense time by the inverter circuit 703 becomes longer. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and to provide a sense circuit suitable for a dynamic circuit and capable of detecting a potential change of a precharged data line at a high speed.

[0008]

According to a first aspect of the present invention, there is provided a sense circuit, comprising: a current supply means for detecting a potential change of a data line and supplying a current; and a supply current of the current supply means being inputted as a reference current; And a current mirror circuit having an output current terminal connected to the data line. According to a second aspect of the present invention, there is provided a sense circuit for detecting a potential change of a data line to supply a current, inputting a supply current of the current supply unit as a reference current, and connecting an output current terminal to the data line. Current mirror circuit, an inverter circuit having a gate input line connected to the data line, and a supply current amount control means for controlling the amount of current supplied from the current supply means to the current mirror circuit based on the potential of the output line of the inverter circuit. It is provided with.

According to a third aspect of the present invention, there is provided a sense circuit for detecting a potential change of a data line to supply a current, inputting a supply current of the current supply unit as a reference current, and connecting an output current terminal to a data current terminal. A current mirror circuit connected to the line; and a supply current amount control means for controlling the amount of current supplied from the current supply means to the current mirror circuit based on the potential of the data line.

According to a fourth aspect of the present invention, there is provided a sense circuit, comprising: a current supply means for detecting a potential change of a data line and supplying a current; inputting a supply current of the current supply means as a reference current; A current mirror circuit connected to the line; and a potential setting means for setting a potential of an input line of a reference current of the current mirror circuit to a ground line potential when precharging the data line.

[0011] The sense circuit according to claim 5 has the following features.
5. The sense circuit according to 2, 3, or 4, wherein the current mirror circuit has a first MOSFET having a drain and a gate connected to a reference current input line and a source connected to a ground line.
And a second MO having a gate connected to a reference current input line, a drain connected to a data line, and a source connected to a ground line.
And SFETs.

According to a sixth aspect of the present invention, in the sensing circuit of the fifth aspect, both the first MOSFET and the second MOSFET are N-channel MOSFETs. A sense circuit according to a seventh aspect is characterized in that, in the sense circuit according to the fifth aspect, both the first MOSFET and the second MOSFET are P-channel MOSFETs.

[0013] The sense circuit according to claim 8 is the first embodiment.
4. The sense circuit according to 2, 3, or 4, wherein the current mirror circuit includes a first NPN transistor having a collector and a base connected to a reference current input line, an emitter connected to a ground line, and a base connected to a reference current input line. And a second NPN transistor connected to the data line, the collector connected to the data line, and the emitter connected to the ground line.

According to a ninth aspect of the present invention, there is provided the sense circuit according to the first aspect.
2. The sense circuit according to 2, 3, 4, 5, 6, 7 or 8, wherein the current supply means comprises a P-channel MOSFET having a gate connected to a data line and a source connected to a power supply line. The drain current is a supply current of the current supply means.

[0015]

According to the structure of the present invention, the change in the potential of the data line is detected by the current supply means as the presence or absence of the supply current of the current supply means, and this supply current is used as the reference current of the current mirror circuit. Then, by using the output current flowing through the current mirror circuit by the reference current for discharging the data line, the sensing time can be shortened.

Further, according to the second aspect of the present invention, the supply current amount control means controls the amount of current supplied from the current supply means to the current mirror circuit based on the potential of the output line of the inverter circuit. After the potential of the output line of the inverter circuit is determined, the current supply path from the current supply means to the current mirror circuit is cut off. Therefore, the DC current flowing through the sense circuit can be reduced.

According to the third aspect of the present invention, the supply current amount control means controls the amount of current supplied from the current supply means to the current mirror circuit based on the potential of the output line of the data line. After the potential of the output line of the data line is determined, the current supply path from the current supply means to the current mirror circuit is cut off. Therefore, the DC current flowing through the sense circuit can be reduced.

Further, according to the configuration of the fourth aspect, the potential of the input line of the reference current of the current mirror circuit is set to the ground line potential by the potential setting means when the data line is precharged. During precharging, the current mirror circuit can be cut off from the bit line. Therefore, the potential stabilization of the data line and the reduction of the precharge time can be realized.

According to the eighth aspect of the present invention, in the configuration of the first, second, third or fourth aspect, the current mirror circuit has the first NPN having a high mutual conductance and a high current driving capability. Type transistor and a second N
Since it is composed of the PN type transistor, it is possible to detect the presence or absence of the supply current of the current supply means and discharge the data line at a higher speed.

[0020]

【Example】

[First Embodiment] FIG. 1 is a circuit diagram showing a main part of a dynamic circuit to which a sense circuit according to a first embodiment of the present invention is added. FIG. 1 shows a register file read circuit.

In FIG. 1, 101 is a memory cell in a register file, 102 is a precharge circuit composed of a P-channel MOSFET, and by controlling a precharge enable line 112, the potential of a bit line 111 is set to "H". To charge. Reference numeral 103 denotes a P-channel MOSFET serving as a current supply means, and when the potential V _B of the bit line 111 connected to the gate becomes a value shown in [Equation 1], a drain current flows, thereby detecting the potential of the bit line 111. Is what you do.

[0022]

V _DD −V _tp ≧ V _B where V _DD is the power supply potential and V _tp is the P-channel MOSFET
103 is the threshold voltage. 104 and 105 are N-channel MOSFETs constituting the current mirror circuit 145
It is. The N-channel MOSFET 104 has a gate and a drain connected to the drain of the P-channel MOSFET 103 and a source grounded. The N-channel MOSFET 105 has a gate connected to the P-channel MOSFET.
T103 is connected to the drain, and the drain is connected to the bit line 11
1 and the source is grounded. In the embodiment, the inverter circuit 106 is provided to drive the output load of the sense circuit, and the output line of the inverter circuit 106 is used as the sense output line 114.

Such inverter circuit 106, P-channel MOSFET 103 and current mirror circuit 14
5 will be described with reference to the operation timing chart shown in FIG. In FIG. 2, FIG.
The potential waveform corresponding to each signal line of the sense circuit shown in
The same reference numerals are assigned to each signal line. For comparison, a potential waveform corresponding to each signal line of the conventional example shown in FIG. 7 is indicated by a broken line, and the same reference numeral is assigned to each signal line.

First, when the potential V _B of the bit line 111 has the value shown in [Equation 2], the operation is performed as follows.

[0025]

V _DD ≧ V _B ≧ V _DD −V _{tp As} shown in FIG. 2, when the word line 113 changes to “H”, the bit line 111 is set based on the contents of the memory cell 101.
Is determined. Here, when the content of the memory cell 101 is set to “H”, the potential of the bit line 111 starts to be lowered to “L”. Note that when the content of the memory cell 101 is “L”, the potential of the bit line 111 remains at the precharge potential.

Next, when the potential V _B of the bit line 111 reaches the value shown in [Equation 3], the following operation is performed.

[0027]

V _DD −V _tp ≧ V _B ≧ V _SS where V _SS is a ground line potential. When the potential V _B of the bit line 111 becomes equal to or lower than V _DD −V _tp , the P-channel MOSFET
T103 is turned on, and a drain current flows. This drain current becomes a reference current input to the current mirror circuit 145, and an output current induced by this reference current flows to the drain of the N-channel MOSFET 105. Since the output current terminal 105a, which is the drain of the N-channel MOSFET 105, is connected to the bit line 111, the bit line 111 is also discharged by the output current of the current mirror circuit 145.

By operating as described above, the word line 11
3 becomes “H” and the delay time T _dnLater, bit line 1
11 potential V_BIs the logical threshold value of the inverter circuit 106
Voltage, and when the inverter circuit 106 delays
Interval T_ivLater, the potential of the sense output line 114 is determined. I
Therefore, the sense time T of the sense circuit shown in FIG.
_snIs the delay time T_dnAnd delay time T_ivAnd the time
Become.

On the other hand, in the conventional sense circuit shown in FIG. 7, the discharge of the bit line 711 is caused by the MO in the memory cell 701.
Since the operation is performed only by the SFETs 701a and 701b, FIG.
As shown by the broken line, the discharge time becomes longer. Word line 11
After a delay time t _dp (longer than the delay time T _dn ) after 3 becomes “H”, the potential of the bit line 111 changes to the logical threshold voltage of the inverter circuit 106, and the delay time of the inverter circuit 106 further decreases. After t _iv , sense output line 114
Is determined. Thus, sense time t _sp of conventional sense circuit shown in Figure 7, becomes a time which is a sum of a delay time t _dp and the delay time t _iv, is longer than the sense time T _sn of the sense circuit shown in FIG. 1 .

As described above, according to the first embodiment, the bit line 111 of the dynamic circuit is connected to the N
In addition to the discharge by the MOSFETs 101a and 101b, the output current (drain current of the N-channel MOSFET 105) flowing through the current mirror circuit 145 is also discharged, so that the sensing time can be reduced. In the first embodiment, the current mirror circuit 145 is configured and the N-channel MOSFETs 104 and 105 are used.
Similar effects can be obtained by using a channel MOSFET.

[Second Embodiment] FIG. 3 is a circuit diagram showing a main part of a dynamic circuit to which a sense circuit according to a second embodiment of the present invention is added. The same reference numerals as those in FIG. 1 indicate the same parts. In FIGS. 3 (a) and (b), 30
Reference numerals 1 and 302 denote P-channel MOSFETs serving as supply current amount control means for controlling the amount of current supplied from the P-channel MOSFET 103 serving as current supply means to the current mirror circuit 145 based on the potential of the sense output line 114.

In the sense circuit shown in FIG. 3A, the gate of the P-channel MOSFET 301 is connected to the sense output line 114.
And the source is connected to the drain of the P-channel MOSFET 103, and the drain is connected to the reference current input line 104a.
Connected to. When the bit line 111 is precharged and the sense output line 114 is “L”, the P-channel MOSFET 301
Becomes conductive. When a reference current flows from the P-channel MOSFETs 103 and 301 to the current mirror circuit 145 with a decrease in the potential of the bit line 111, N
The bit line 111 is further discharged by a drain current that is an output current induced in the channel MOSFET 105. When the sense output line 114 becomes "H", the P-channel MOSFET 301 is turned off, so that there is no DC current path existing between the P-channel MOSFET 103 and the current mirror circuit 145, and no DC current flows through the sense circuit. .

In the sense circuit shown in FIG.
The channel MOSFET 302 has a gate connected to the sense output line 114 and a source connected to the N-channel MOS transistors 104 and 105 forming the current mirror circuit 145.
And the drain is grounded. When the bit line 111 is precharged and the sense output line 114 is “L”,
The channel MOSFET 302 becomes conductive. 3A, an output current flows through the current mirror circuit 145 as the potential of the bit line 111 decreases, and the bit line 111 is discharged. Then, when the sense output line 114 becomes “H”, the P-channel MOSFET 302 is turned off, so that there is no DC current path between the P-channel MOSFET 103 and the current mirror circuit 145, and no DC current flows through the sense circuit. .

According to the second embodiment, after the potential of the sense output line 114 is determined, the P-channel MOSFET
By turning off 301 and 302, the current supply path from the P-channel MOSFET 103 serving as current supply means to the current mirror circuit 145 is cut off.
The DC current flowing through the sense circuit can be reduced, and the sense time can be reduced, and a sense circuit with low power consumption can be realized.

[Third Embodiment] FIG. 4 is a circuit diagram showing a main part of a dynamic circuit to which a sense circuit according to a third embodiment of the present invention is added. The same reference numerals as those in FIG. 1 indicate the same parts. In FIGS. 4A and 4B, 40
Reference numerals 1 and 402 denote N-channel MOSFETs serving as supply current amount control means for controlling the amount of current supplied from the P-channel MOSFET 103 serving as current supply means to the current mirror circuit 145 based on the potential of the bit line 111.

In the sense circuit shown in FIG. 4A, the gate of the N-channel MOSFET 401 is connected to the bit line 111, the drain is connected to the drain of the P-channel MOSFET 103, and the source is connected to the reference current input line 104a. Things. The sense circuit thus configured is
When the bit line 111 is precharged and becomes “H”,
N-channel MOSFET 401 enters a conductive state.
The P-channel MOSF
When the reference current flows from the ET 103 and the N-channel MOSFET 104 to the current mirror circuit 145, the bit line 111 is further discharged by the output current induced in the N-channel MOSFET 105. When the bit line 111 becomes “L”, an N-channel MOSFET
Since 401 is turned off, a P-channel MOSFET
D existing between the current mirror circuit 103 and the current mirror circuit 145
There is no C current path, and no DC current flows through the sense circuit.

In the sense circuit shown in FIG.
The channel MOSFET 402 has a gate connected to the bit line 11.
1, the drain is connected to the sources of the N-channel MOS transistors 104 and 105 constituting the current mirror circuit 145, and the sources are grounded. In the sense circuit configured as described above, when the bit line 111 is precharged to “H”, the N-channel MOSFET
Reference numeral 401 indicates a conductive state. As in the case of FIG. 4A, the current mirror circuit 1
The output current flows through 45, and the bit line 111 is discharged.
When the bit line 111 becomes “L” by reading, the N-channel MOSFET 402 is turned off, so that there is no DC current path between the P-channel MOSFET 103 and the current mirror circuit 145, and a DC current flows through the sense circuit. Disappears.

According to the third embodiment, after the potential of the bit line 111 is determined, the N-channel MOSFET 40
By turning off the transistors 1402 and 402, the current supply path from the P-channel MOSFET 103 serving as a current supply unit to the current mirror circuit 145 is cut off, so that the DC current flowing through the sense circuit can be reduced, and the sense time can be reduced. And a sense circuit with low power consumption can be realized.

[Fourth Embodiment] FIG. 5 is a circuit diagram showing a main part of a dynamic circuit to which a sense circuit according to a fourth embodiment of the present invention is added. The same reference numerals as those in FIG. 1 indicate the same parts. 5, reference numeral 500 denotes a potential setting means, which is an N-channel MOSFET for setting the potential of the reference current input line 104a of the current mirror circuit 145 to the ground line potential during the precharge period of the bit line 111.
The precharge circuit 501 includes an inverter circuit 502 that generates a logically inverted signal of the precharge signal input to the precharge enable signal line 112 of the precharge circuit 102.

The sense circuit configured as described above solves the following disadvantages. The potential of the reference current input line 104a is equal to that of the P-channel MOSFET 103 and the N-channel MOSFET.
The potential is divided by the resistance component with the SFET 104.
Therefore, when the gate width of the N-channel MOSFET 104 is reduced, the gate potential of the N-channel MOSFET 105 increases. Further, when the gate width of the N-channel MOSFET 105 is increased, a large output current, that is, the drain current of the N-channel MOSFET 105 is obtained, so that the sensing time can be reduced. However, even if the discharge of the bit line 111 ends, the N channel M
The gate potential of the OSFET 105 remains above the threshold voltage, and the N-channel MOSFET 105 continues to be turned on to try to fix the potential of the bit line 111 to “L”. Therefore, if the gate width of the N-channel MOSFET 104 is too small, the driving capability of the N-channel MOSFET 105 increases, and the bit line 11
In some cases, the potential of 1 does not return to “H”. Further, the precharge circuit 102 and the N-channel MOSFET 1
Since there is a DC current path during the period 05, it takes a long time to precharge the bit line 111.

In order to avoid such a drawback, an N-channel MOSFET 501 is provided, and when the bit line 111 is precharged, the N-channel MOSFET 501 is turned on, so that the potential of the reference current input line 104a, that is, the N-channel MOSFET 104 , 105 to the ground line potential. Thereby, N channel M
The OSFET 105 is turned off, and the current mirror circuit 145 is cut off from the bit line 111. Therefore, even if the gate width of the N-channel MOSFET 104 is reduced, the potential of the bit line 111 can be stabilized and the precharge time can be reduced.

As described above, according to the fourth embodiment, when the potential setting means 500 precharges the bit line 111, the input line 10 of the reference current of the current mirror circuit 145 is supplied.
By setting the potential of 4a to the ground line potential, the bit line 1
At the time of precharge of 11, the current mirror circuit 145 can be cut off from the bit line 111. Therefore, it is easy to optimize the circuit constant for shortening the sensing time, and it is possible to stabilize the potential of the bit line 111 and shorten the precharge time.

The same effect can be obtained by using the potential setting means 500 shown in the fourth embodiment in the sense circuits shown in FIGS. 1, 3 and 4. [Fifth Embodiment] FIG. 6 is a circuit diagram showing a main part of a dynamic circuit to which a sense circuit according to a fifth embodiment of the present invention is added. 6A shows an example in which the current supply means is constituted by a P-channel MOSFET 103, FIG. 6B shows an example in which the current supply means is constituted by a PNP-type bipolar transistor 603, and FIG. P channel MOS
FET 604 and NPN-type bipolar transistor 6
05, the current supply means detects the potential drop of the bit line 111 and detects the current mirror circuit 146.
To supply current to the 1 have the same reference numerals as those in FIG.
As shown in FIG. 6, in the fifth embodiment, the current mirror circuit 146 includes two NPN-type bipolar transistors 601, 60.
It consists of two.

Since bipolar transistors 601 and 602 have high mutual conductance and high current driving capability, P-channel MOSFET 1 serving as a current supply means
03, the PNP-type bipolar transistor 603, the P-channel MOSFET 604, and the presence or absence of the current from the NPN-type bipolar transistor 605 to detect the bit line 1
11 can be discharged at a high speed.

Such a sense circuit can be applied to a high-speed sense circuit such as a BiCMOS circuit, an ECL circuit, and an ECL-CMOS circuit.

[0046]

According to the sense circuit of the present invention, the change in the potential of the data line is detected by the current supply means as the presence or absence of the supply current of the current supply means, and this supply current is used as the reference current of the current mirror circuit. Then, by using the output current flowing through the current mirror circuit by the reference current for discharging the data line, the sensing time can be shortened. As a result, it is possible to obtain a sense circuit capable of detecting a change in potential of the precharged data line at a high speed.

Further, according to the sense circuit of the present invention, the supply current amount control means controls the amount of current supplied from the current supply means to the current mirror circuit based on the potential of the output line of the inverter circuit. After the potential of the output line of the inverter circuit is determined, the current supply path from the current supply means to the current mirror circuit is cut off. Therefore,
DC current flowing through the sense circuit can be reduced.

According to the sense circuit of the present invention, the supply current amount control means controls the amount of current supplied from the current supply means to the current mirror circuit based on the potential of the output line of the data line. After the potential of the output line of the data line is determined, the current supply path from the current supply means to the current mirror circuit is cut off. Therefore, the DC current flowing through the sense circuit can be reduced.

As a result, it is possible to reduce the sensing time and realize a low power consumption sensing circuit. Further, according to the sense circuit of the fourth aspect, the potential setting means sets the potential of the input line of the reference current of the current mirror circuit to the ground line potential when precharging the data line, thereby precharging the data line. At the time of charging, the current mirror circuit can be cut off from the bit line. Therefore, the potential stabilization of the data line and the reduction of the precharge time can be realized.

According to the sense circuit of the eighth aspect, in the sense circuit of the first, second, third or fourth aspect, the current mirror circuit has a high mutual conductance and a high current drive capability. By using the NPN-type transistor and the second NPN-type transistor, it is possible to detect the presence or absence of the supply current of the current supply means and discharge the data line at a higher speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main configuration of a dynamic circuit to which a sense circuit according to a first embodiment of the present invention is added (corresponding to claim 1);

FIG. 2 is a timing chart for explaining the operation of the sense circuit according to the first embodiment;

FIG. 3 is a circuit diagram showing a main configuration of a dynamic circuit to which a sense circuit according to a second embodiment of the present invention is added (corresponding to claim 2);

FIG. 4 is a circuit diagram showing a main configuration of a dynamic circuit to which a sense circuit according to a third embodiment of the present invention is added (corresponding to claim 3);

FIG. 5 is a circuit diagram showing a main configuration of a dynamic circuit to which a sense circuit according to a fourth embodiment of the present invention is added (corresponding to claim 4);

FIG. 6 is a circuit diagram showing a main configuration of a dynamic circuit to which a sense circuit according to a fifth embodiment of the present invention is added (corresponding to claim 8).

FIG. 7 is a circuit diagram for explaining a sense circuit of a conventional dynamic circuit.

[Explanation of symbols]

111 Bit line (data line) 103 P-channel MOSFET (current supply means) 105 a Output current terminal 145 Current mirror circuit 104 N-channel MOSFET (first MOSFE)
T) 104a Reference current input line 105 N-channel MOSFET (second MOSFET)
T) 106 Inverter circuit 114 Sense output line (output line) 301 P-channel MOSFET (supply current amount control means) 302 P-channel MOSFET (supply current amount control means) 401 N-channel MOSFET (supply current amount control means) 402 N-channel MOSFET (Supply current amount control means) 500 Potential setting means 146 Current mirror circuit 601a Reference current input line 601 NPN-type bipolar transistor (first N
PN transistor 602 NPN bipolar transistor (second N
PN type transistor)

Claims (9)

(57) [Claims] 1. A sense circuit for a dynamic circuit having a data line precharged to a predetermined potential, comprising: a current supply means for detecting a potential change of the data line and supplying a current; and a supply of the current supply means. Input the current as the reference current,
And a current mirror circuit having an output current terminal connected to the data line. 2. A sense circuit of a dynamic circuit having a data line precharged to a predetermined potential, comprising: a current supply means for detecting a potential change of the data line and supplying a current; and a supply of the current supply means. Input the current as the reference current,
A current mirror circuit having an output current terminal connected to the data line; an inverter circuit having a gate input line connected to the data line; and a current mirror circuit from the current supply means based on a potential of an output line of the inverter circuit. A supply current amount control means for controlling the amount of current supplied to the sensing circuit. 3. A sense circuit for a dynamic circuit having a data line precharged to a predetermined potential, comprising: a current supply means for detecting a change in potential of the data line and supplying a current; Input the current as the reference current,
A current mirror circuit having an output current terminal connected to the data line; and a supply current amount control means for controlling an amount of current supplied from the current supply means to the current mirror circuit based on the potential of the data line. Sense circuit. 4. A sense circuit for a dynamic circuit having a data line precharged to a predetermined potential, comprising: a current supply means for detecting a potential change of the data line and supplying a current; and a supply of the current supply means. Input the current as the reference current,
And a current mirror circuit having an output current terminal connected to the data line; and potential setting means for setting a potential of an input line of a reference current of the current mirror circuit to a ground line potential when precharging the data line. Equipped sense circuit. 5. A current mirror circuit comprising: a first MOSFET having a drain and a gate connected to a reference current input line, a source connected to a ground line, a gate connected to the reference current input line, and a drain connected to the reference current input line. A second MO connected to the data line and the source connected to the ground line
4. An SFET according to claim 1, wherein
Or the sense circuit according to 4. 6. A first MOSFET and a second MOSFET.
6. The sense circuit according to claim 5, wherein both T are N-channel MOSFETs. 7. A first MOSFET and a second MOSFET.
6. The sense circuit according to claim 5, wherein both T are P-channel MOSFETs. 8. A current mirror circuit, comprising: a first NPN transistor having a collector and a base connected to a reference current input line, an emitter connected to a ground line, and a base connected to the reference current input line; A second N connected to the data line and the emitter to the ground line;
5. The sense circuit according to claim 1, comprising a PN transistor. 9. A P-channel MOSFET having a gate connected to a data line and a source connected to a power supply line.
9. The sense circuit according to claim 1, wherein said P-channel MOSFET comprises a drain current, and a drain current of said P-channel MOSFET is a supply current of said current supply means.