JPH0721744B2 - Bus line precharge circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic bus such as a microprocessor or a memory, and more particularly to a precharge circuit suitable for accessing the bus at high speed.

[Background of the Invention]

FIG. 2 is a diagram showing a conventional precharge circuit (Japanese Patent Laid-Open No. 58-58-58).
(Quoted from the publication No. 211226). In FIG. 2, 1 is a data bus line, 2 is a P-channel type MOS transistor (hereinafter abbreviated as PMOST), 3 and 4 are N-channel type MOS transistors (hereinafter abbreviated as NMOST), 5, 6, 7, 8 Is an inverter circuit, 9 is a capacitor, 10 is a NAND circuit, 11 is a precharge circuit for the data bus line 1, 12 is a discharge circuit for outputting data to the data bus line 1, and 13 is an output for reading data according to the potential of the data bus line 1. Circuit, 14
Is a level detection circuit for detecting a predetermined potential of the data bus line 1, 15 is a delay circuit, and 16 is a synchronization circuit.

FIG. 3 is a time chart showing the operation of the circuit of FIG. The synchronization circuit 11 starts charging the data bus line 1 in synchronization with the clock φ. When the potential of the data bus line 1 exceeds the detection level V _a of the level detection circuit 14, the level detection circuit 14 performs the detection operation and stops the charging of the data bus line 1 after the delay time of the delay circuit 15. The display circuit 12 operates in synchronization with the clock. When the internal data is "1", NMOST4 is turned on, the charge of the data bus line 1 is extracted, and when the potential of the data bus line 1 becomes lower than the threshold level V _d of the output circuit 13, the output d
Stands up. On the other hand, if the internal data is "0", NM
OST4 is turned off, the potential of the data bus line 1 does not change, and the output d also maintains the L (LOW) level.

By the way, since the data bus line 1 generally has a wiring length of several mm, it has a large parasitic capacitance. On the other hand, NMOST 3 and 4 are of small size for high integration, and their on-resistance is large. Therefore, the electric charge charged in the data bus line 1 is discharged with an extremely large time constant. This appears as a drawback that the access time of data becomes long. The access time depends on the potential of the data bus line 1 being the threshold level of the output circuit 13.
It is determined by the time to reach V _d , t _d .

Figure 4 shows the input / output characteristics of the CMOS logic gate. In general,
The voltage v _{Ia at} which the output voltage v _o and the input voltage v _I are equal to each other is called a logical threshold voltage V _LT . FIG. 5 is a diagram showing the relationship between the bus potential and the delay time t _d when reading the bus. As a result of precharging, the initial voltage of the bus in the read cycle is V
_When set to _bo , if the parasitic capacitance of the bus is C _pb and the on-resistance of the discharge circuit is R _ds , the bus potential V _b will be The delay time t _d is Can be approximated by As shown in FIG. 2, after the level detection circuit 14 detects a predetermined bus potential, PMOST2 is turned off with a delay,
If the bus is precharged to a sufficiently high potential, of course t _d
Grows. For example, set the initial voltage V _{bo of the} bus to 4
(V), assuming that the logic threshold voltage V _LT is 2 (V), the delay time t _d reaches about 0.7τ _d (τ _d = C _pb -R _ds : time constant of the discharge circuit).

That is, to read the bus at high speed, the precharge voltage V _bo
The need to close the logic threshold voltage V _LT, For that purpose, from the bus potential during Purichiyaji reaches the logic threshold voltage V _LT described above, it is reduced delay before turning off the PMOST2 for Purichiyaji I have to. Also,
In order to speed up the bus access cycle, it is necessary to increase the precharge current, and in this case, the precharge must be stopped even faster. However, these cannot be satisfied by the conventional method as shown in FIG.

[Object of the Invention]

An object of the present invention is to provide a precharge circuit capable of high-speed access to a dynamic bus.

[Outline of Invention]

In order to access the dynamic bus at high speed, it is necessary to increase the precharge current, and also to turn off the precharge current at high speed when the bus potential exceeds the logic threshold voltage of the output circuit. The feature of the present invention is that the detection of the bus potential is performed by the output circuit itself for reading from the bus, or by the sense circuit having the consistency of the output circuit and the logical threshold voltage, and the output of either of these circuits is used as the bus. The switching element for supplying the precharge current is controlled, and the high-speed feedback circuit is connected between the bus line and the control input of the switching element to cut off the precharge current at high speed.

Example of Invention

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the figure, the NPN bipolar transistor (hereinafter NPN BiT
The collector 17 is connected to the power supply voltage V _cc , and the emitter is connected to the data bus line 1. PMOST1 whose gate is connected to the output A of the output circuit 23 which reads out the data of the data bus line 1 which is a series circuit of the inverter circuits G1 and G2
One end of the series circuit of the PMOST 18 whose gate is controlled by 9 and the clock is connected to the power supply voltage _Vcc , and the other end is connected to the base B of the NPNBiT17. One end of a parallel circuit of NMOST21 whose gate is connected to the data bus line 1 and NMOST20 whose gate is controlled by a clock is connected to the base B of NPNBiT17 and the other end is connected to the ground. Next, this embodiment will be described using the time chart shown in FIG. In the previous cycle (clock is high level), when the selected internal data is "1", the electric charge of the data bus line 1 is drawn and the potential of the data bus line 1 is lowered,
The output A of the output circuit 23 is at a low level. Therefore, PMOS
T19 is on. On the other hand, NMOST21 has a low potential on the data bus line 1 and is in an off state or in a high impedance state. If the clock is high, PMOST18
Is off and NMOST20 is on, and the base B of NPNBiT17 is pulled down to ground by NMOST20. From this state, if the clock is switched to low level, PMOST18 will be on and NMOST20 will be off,
Current is injected into the base B of NPNBiT17 via PMOST 18,19. That is, PMOST 18, 19 and NMOST 20 form a switching control circuit for switching the ON / OFF cycle of NPN BiT 17, which is a switching element. As a result, the collector current of NPNBiT17 flows, the data bus line 1 is charged, and the potential rises. By the way, when the potential of the data bus line 1 rises, the gate voltage of NMOST21 increases, so that the conductance increases and the current easily flows. Therefore, the base currents flowing into PMNP18 and 19 from NPNBiT17 are shunted and flow into NMOST21, so that the base current decreases, the collector current of NPNBiT17 decreases, and the charging speed of data bus line 1 decreases. Then, since the potential of the data bus line 1, exceeds the threshold level V _o of the output circuit 23, the output A is inverted, the high level, PMOST19
Is turned off to stop the supply of the base current of the NPNBiT17, and the NMOST20 is turned on to remove the charge accumulated in the base B of the NPNBiT17, so that the charging of the data bus line 1 is stopped. That is, NMOST21 is an output circuit 23 for detecting the potential of the bus line, and an NPNB that is a switching element via a switching control circuit of PMOST18-NMOST20.
A high-speed feedback circuit that feeds back the bus potential to the base of the NPNBiT17, which is the control input of the switching element, at a higher speed than the control loop that controls the iT17 is formed. In this case, the precharge voltage V _p of the data bus line 1 is the threshold level of the output circuit 23 corresponding to the amount of charge charged between the response delay of the output circuit 23 and the operation delay of the PMOST 19 and NMOST 20. It will be higher than V _o . However, in this circuit, as the voltage of the data bus line 1 rises, the charging current decreases due to the action of NMOST21. Therefore, the precharge voltage V _p of the data bus line 1 becomes slightly smaller than the threshold level V _o of the output circuit 23. Can be set to a high level.

That is, the charge control of the data bus line 1 is controlled by the output circuit.
Since the output A of 23 is used, the relationship between the precharge voltage V _p of the data bus line 1 and the threshold level V _o of the output circuit 23 is not affected by variations in elements, fluctuations in ambient temperature, power supply voltage, etc. Extremely stable operation is possible. Further, in this embodiment, the precharge time is shortened because the data bus line 1 is precharged with a sufficiently large precharge current by using a bipolar transistor having a high load driving capability for charging the data bus line 1. Moreover, when the bus potential approaches the logical threshold voltage V _LT of the output circuit 23, the action of NMOST21 forming the high-speed feedback circuit suppresses the precharge current, so that the output circuit 23 controls the NPNBiT17 with high accuracy. . As a result, for example, the logical threshold voltage V
Precharge voltage of bus line 1 for _LT = 2 (V)
If V _p = 2.2 (V) is set, the read delay time t _d becomes t _d = 0.095τ _d from the equation (2), which enables extremely high speed bus access.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. The difference between FIG. 5 and FIG. 1 is that the gate is output circuit 23.
The series circuit of PMOST25 connected to the output A of PMOST24 and PMOST24 whose gate is controlled by the clock is connected to the power supply voltage V _cc at one end.
The other end is connected to the data bus line 1. PMOST24,
The series circuit of 25 charges the data bus line 1 until the output A of the output circuit 23 is inverted. That is, in this embodiment, the data bus line 1 is charged by the parallel circuit of the NPNBiT 17 and the PMOST 24, 25 series circuit. Comparing the conductances of bipolar transistors and MOS transistors, bipolar transistors are generally an order of magnitude larger. Therefore, the charging current of NPNBiT17 is larger than the charging current of the series circuit of PMOST 24,25. However, as mentioned above, NPNB
The charging current of iT17 decreases as the potential of the data bus line 1 increases. On the other hand, the charging current of the series circuit of PMOST24,25 is determined by the conductance of the series circuit of PMOST24,25. Even if the potential of the data bus line 1 changes, it becomes substantially constant. That is, the series circuit of the PMOST 24, 25 sets the minimum value of the charging current of the data bus line 1, so that the time for precharging the data bus line 1 can be shortened.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention. In FIG. 6, the point different from FIG. 5 is that the output A of the sense circuit 23 'for detecting the bus potential, which is a series circuit of inverter circuits G1 and G2, is connected to the gates of the PMOSTs 19 and 25. . By setting the logic threshold voltages V _LT of the sense circuit 23 'and the output circuit 23 to be substantially equal, the same circuit characteristics as those of the second embodiment can be obtained. In this embodiment, the output circuit 23
In addition to the above, by providing a sense circuit 23 'and controlling the charging of the data bus line 1 by its output A', the degree of freedom in arrangement of the precharge circuit of the data bus line 1 and the output circuit 23 is increased, The layout is facilitated, a plurality of read circuits 23 can be connected to the bus line 1, and the degree of freedom in system design is expanded.

FIG. 9 is a circuit diagram showing a fourth embodiment of the present invention. In Fig. 9, a high-speed feedback circuit is added to NMOST21, it is formed by a series circuit of PMOST26 and 27, the gate of PMOST26 is connected to the clock, and switching of precharge cycle is performed.
The gate of the PMOST27 is connected to the bus line 1, and the bus potential is fed back to the NPNBiT17 at high speed as in the NMOST21.

In the present embodiment, the inverter amplifier is formed by NMOST21 and PMOST27, and the high-speed feedback to NPNBiT17 is more optimally performed except that NMOST21 alone causes overbraking.

FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention. First
What is new in the embodiment shown in Fig. 10 is that the series circuit of PMOST 28 and 29 and NM
Connect the series circuit of OST30,31 in series, connect the connection point to bus line 1, gates of PMOST29 and NMOST31 to bus line 1, gate of PMOST28 to clock, NMOST30
That is, a circuit in which the gate of is connected to the clock φ is added. PMOST29 and NMOST31 form an inverter amplifier,
Both the input and output of this inverter amplifier are connected to the bus line 1. The PMOST28 and NMOST30 perform switching to activate the inverter amplifier into the precharge amplifier. The logical threshold voltage of the inverter amplifier is set to be approximately equal to the logical threshold voltage of the output circuit 23.

The effect of the present embodiment is that the inverter amplifier forms a precharged circuit having a small driving force but an independent minor loop, and when the bus potential slightly changes from the logical threshold voltage V _LT , the bus potential correction operation is locally performed. Is to have. That is, the precharge circuits according to the embodiments shown in FIGS. 1, 7, 8, and 9 form a kind of peak hold circuit. Therefore, when the potential of the bus line 1 gradually rises due to the charge circuit with the output circuit 23, the discharge circuit 12, etc., or the leakage current, there is no function of lowering the bus potential except for the discharge circuit 12. . In this embodiment, this function is added to the pre-charge circuit, and in addition to the supply of the pre-charge current by the NPN BiT17, an auxiliary pre-charge circuit for additionally supplying the pre-charge current is added.

〔The invention's effect〕

According to the present invention, it is possible to set the precharge voltage that is well matched to the logic threshold voltage of the output circuit without being affected by the ambient temperature, the power supply voltage and the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional data bus line precharge circuit, and FIG. 3 is a time chart showing the operation of the circuit shown in FIG. FIG. 4 is a time chart showing the operation of the circuit of FIG. 1, FIG. 5 is a circuit diagram showing a second embodiment of the present invention, and FIG.
FIG. 7 is a circuit diagram showing a third embodiment of the present invention, and FIGS. 7 to 10 are circuit diagrams of the fourth to seventh embodiments of the present invention. 1 ... Data bus line, 17 ... NPNBiT, 18,19,24,25
…… PMOST, 20,21 …… NMOST, 23 …… Output circuit.

Claims (5)

[Claims] 1. A bus line (1), a precharge circuit for precharging the bus line, a discharge circuit (12) for outputting data to the bus line after precharging, and an output for reading data on the bus line. In a dynamic bus line system composed of a circuit (23), the precharge circuit comprises a switching element (17) connected between a first power supply and the bus line, and the output circuit and a logical threshold voltage. A sense circuit (23 ') which is connected to the bus line and detects the potential of the bus line, and a precharge control signal () connected to the control input terminal of the switching element and the output of the sense circuit And a switching control circuit (18, 19, 20) for controlling the switching element, and the drain and the source are the switching element. A high speed feedback circuit including a MOS transistor (21) which is connected to a control input terminal and a second power source, has a gate connected to the bus line, and is driven in an ON direction when the bus line is precharged. A precharge circuit for the bus line, which is characterized in that 2. The bus line precharge circuit according to claim 1, wherein the sense circuit also serves as the output circuit. 3. The switching element is a bipolar transistor having a collector connected to a first power supply, an emitter connected to the bus line, and a base connected as the control input terminal to an output terminal of the switching control circuit. The bus line precharge circuit according to claim 1 or 2, wherein: 4. The high-speed feedback circuit has a first conductivity type MOS transistor having a drain connected to a control input terminal of the switching element, a source connected to a second power supply, and a gate connected to the bus line. ), And a pair of second conductive members connected in series between the first power source and the control input terminal of the switching element, each gate being configured to receive the precharge control signal or the potential of the bus line. Type MOS transistor (26, 27), the bus line precharge circuit according to claim 1, 2, or 3. 5. The precharge circuit is connected in series between a second power source and the bus line and is configured to receive the precharge control signal or the potential of the bus line at each gate. A pair of second-conductivity-type MOS transistors (28, 29), which are connected in series between the bus line and the first power supply and each gate has an inverted signal of the precharge control signal or the potential of the bus line. A pair of first-conductivity-type MOS transistors (30, 31) configured to receive the voltage are provided, and the first, second, third, or fourth claim. A precharge circuit for the bus line described in the item.