JP2964567B2 - Overcurrent protection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an overcurrent prevention circuit for a power supply terminal of a semiconductor integrated circuit device.

〔Overview〕

According to the present invention, in a circuit for protecting an overcurrent of a plurality of semiconductor integrated circuits, which is collectively protected by a common fuse, unnecessary fuse blowing can be prevented by providing a means for restricting an overcurrent to flow in a short time. It is made possible.

[Conventional technology]

When an integrated circuit device manufactured by a high withstand voltage process is used for a telephone exchange or the like, one semiconductor integrated circuit device is used corresponding to one telephone line. In this case, protection of the power supply terminal against excessive current is not provided for each integrated circuit device, but one fuse is often provided for about 128 lines. Normally, when an excessive current flows to the power supply terminal due to some cause, such as breakage of the electrical isolation inside the device in a semiconductor integrated circuit device manufactured by a high withstand voltage process, it is possible to flow up to about 2 to 3 A It is possible. On the other hand, fuses that collectively protect each integrated circuit device are often blown by a current of 2 to 3 A. Therefore, when an excessive current flows to the power supply terminal due to an abnormality in a certain semiconductor integrated circuit device, the fuse blows before the semiconductor integrated circuit device alone is destroyed, and as a result, about 128 lines cannot be used simultaneously. May be.

[Problems to be solved by the invention]

In this conventional semiconductor integrated circuit device, when a certain cause such as a dielectric breakdown in one integrated circuit device occurs, an excessive power supply current flows, and as a result, a plurality of integrated circuit devices are collectively protected. However, there is a disadvantage that about 128 lines cannot be used at once due to an abnormality in one semiconductor integrated circuit device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an overcurrent prevention circuit which eliminates such a drawback and in which an abnormality of one semiconductor integrated circuit does not spread to another.

[Means for solving the problem]

The present invention relates to an overcurrent prevention circuit coupled to a plurality of semiconductor integrated circuits, which are protected from overcurrent by a common fuse connected to one of a first power supply terminal and a second power supply terminal. A first bipolar transistor having an input electrode connected to a terminal, an input electrode connected to an output electrode of the first bipolar transistor, and a second electrode having an output electrode connected to a control electrode of the first bipolar transistor. A bipolar transistor, a first resistor having one end connected to the input electrode of the second bipolar transistor, and the other end connected to the control electrode of the second bipolar transistor and one power supply terminal of the semiconductor integrated circuit, One end is connected to the output electrode of the second bipolar transistor and the control electrode of the first bipolar transistor. The other end is characterized in that a second resistor connected to the other power supply terminal of the second power supply terminal and the semiconductor integrated circuit. Here, a MOS transistor may be used instead of the bipolar transistor.

[Action]

In normal times, the first transistor is on and the second transistor is off, but excessive current turns on the second transistor, which turns off the first transistor. The circuit is interrupted.
With this interruption, the second transistor is turned off again, and thus the first transistor is turned back on. That is, the steady inflow of the excessive current is prevented.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an overcurrent prevention circuit of the semiconductor integrated circuit device of this embodiment.

The semiconductor integrated circuit device 5 manufactured by the high withstand voltage process has a first power supply terminal (power supply voltage V _BB = −48 V),
A potential is applied from a second power supply terminal (reference potential GND). Circuit of the present invention, on the wiring from the first power supply terminal V _BB to a semiconductor integrated circuit device 5, and an emitter connected to the first power supply terminal V _BB side, the semiconductor integrated circuit device collector 5
An NPN transistor 4 connected to the side is provided. Also,
A resistor 1 of about 10Ω is connected between the collector of the NPN transistor 4 and the semiconductor integrated circuit device 5, and an NPN transistor 2 having both ends serving as an emitter and a base is provided. The collector of the NPN transistor 2 is 4
And the other end of the resistor 3 is connected to the second power supply terminal GND. It is desirable that the resistor 3 has a resistance as large as possible in the manufacturing process of the semiconductor integrated circuit device 5 using the circuit of the present invention.

In the first embodiment, as shown in FIG.
A common fuse connected to one of V _{BB and} the second power supply terminal GND is coupled to a plurality of semiconductor integrated circuits protected from overcurrent, and an input electrode is connected to the first power supply terminal V _BB NPN transistor 4 and NPN transistor 4
The input electrode is connected to the output electrode of the NPN transistor 4
NPN transistor 2 whose output electrode is connected to the control electrode
And one end is connected to the input electrode of NPN transistor 2,
A resistor 1 having the other end connected to the control electrode of the NPN transistor 2, and one end connected to the output electrode of the NPN transistor 2 and the NPN
A resistor connected to the control electrode of the transistor and having the other end connected to the second power supply terminal;

As shown in FIG. 2, the second embodiment has the same configuration as the first embodiment except that a MOS transistor is used instead of the NPN transistor.

 Next, the operation of this embodiment will be described.

In a state where the semiconductor integrated circuit device 5 is operating normally, for example, the current I _BB of the first power supply terminal (V _BB = −48 V) is about 4 mA, and the potential difference between both ends AB of the resistor 1 is 0.04 V , And the NPN transistor 2 is not turned on. Therefore, point C is the reference potential, and since there is a potential difference of about 48 V between the base and the emitter of the NPN transistor 4, this NPN
Transistor 4 is on.

When an excessive current of about 60 mA or more flows through the first power supply terminal V _BB for some reason, the resistor 1 of about 10Ω
Potential of approximately 0.6V is generated between AB, NPN transistor 2 is turned on, an excessive power current flows from point D to point A on the first power supply terminal V _BB. As a result, the potential at the point C is lowered by the resistor 3 having a large resistance value, and
The potential difference between V _BB is no longer sufficient to keep the NPN transistor 4 on. Thus, the semiconductor integrated circuit device 5 that caused the characteristic abnormality is disconnected from the first power supply terminal V _BB. When the excessive current does not flow through the first power supply terminal _VBB , the potential difference between both ends of the resistor 1 disappears, and the NPN transistor 2 is turned off. As a result, no current flows through the resistor 3 and the potential at the point C becomes the reference potential.
A potential difference of about 48 V is generated between the base and the emitter of the transistor 4. As a result, the NPN transistor 4 is turned on, and the power supply to the semiconductor integrated circuit device 5 returns to the normal use state.

The current of the first power supply terminal _VBB flows in a pulse shape, and it is possible to prevent the fuse from being blown from the power supply terminal due to the steady flow of the excessive current. The present invention may be built in the semiconductor integrated circuit device or may be provided outside.

FIG. 2 is a circuit diagram of an overcurrent prevention circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention.

In this example, an n-channel MOS transistor is used for each transistor. In a state where the semiconductor integrated circuit device 5 is operating normally, a current difference (I _BB = −4 mA) of the first power supply terminal (V _BB = −48 V) causes a potential difference between both ends AB of the resistor 1. if the threshold voltage V _T of the n-channel MOS transistor 6 by setting higher than the potential difference, the transistor does not become turned on. Therefore, no current flows through the resistor 3, and the potential at the point C is equal to the second power supply terminal GND. Therefore, a voltage of about 48 V is applied to the gate of the n-channel MOS transistor 7, and this transistor is on.

When excessive current flows to the first power supply terminal V _BB for some reason, a potential difference occurs between the AB by resistors 1, when it is higher than the threshold voltage V _T of the n-channel MOS transistors 6, the The transistor is turned on. Then, a current from the second power supply terminal GND flows to point A of the first power supply terminal V _BB through the resistor 3 from point D. Then, the potential of the point C is pulled down by the current, and the potential difference between the C～V _BB is lower than the threshold voltage V _T of the n-channel MOS transistor 7, the transistor is turned off, causing a characteristic abnormality the semiconductor integrated circuit device 5 is disconnected from the first power supply terminal V _BB.

When excessive current does not flow to the first power supply terminal V _BB, the potential difference across the resistor 1 becomes lower than the threshold voltage V _T of the n-channel MOS transistors 6, this transistor is turned off. Then, the transistor when the voltage applied to the gate of n-channel MOS transistor 7 is higher than the threshold voltage V _T of the transistor is turned on, the power supply normal use of the semiconductor integrated circuit device 5 Return to

When a MOS transistor is used as the transistor as in this example, unlike the bipolar transistor, the first
N channel M arranged in series on the power supply terminal V _{BB of}
There is an advantage that no potential difference occurs between the source and the drain of the OS transistor 7. Similarly, an n-channel M is disposed between the first power supply terminal V _BB and the second power supply terminal GND.
No potential difference occurs between the source and the drain of the OS transistor 6.

〔The invention's effect〕

As described above, the present invention disconnects a semiconductor integrated circuit device from a power supply terminal when an excessive current flows to a power supply terminal of the semiconductor integrated circuit device. Thus, there is an effect that it is possible to prevent a fuse that is being protected from being blown and a plurality of lines from being disabled at once.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention. FIG. 2 is a circuit diagram of a second embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional example. 1, 3, ... resistor, 2, 4, ... NPN transistor, 5 ...
... Semiconductor integrated circuit device, 6, 7 ... N-channel MOS transistor.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H02H 3/08-3/10 H02H 7/20

Claims (2)

(57) [Claims] An overcurrent protection circuit coupled to a plurality of semiconductor integrated circuits, which are protected from overcurrent by a common fuse connected to one of a first power supply terminal and a second power supply terminal; A first bipolar transistor having an input electrode connected to a power supply terminal; an input electrode connected to an output electrode of the first bipolar transistor; and a second electrode having an output electrode connected to a control electrode of the first bipolar transistor. And a first resistor having one end connected to the input electrode of the second bipolar transistor and the other end connected to the control electrode of the second bipolar transistor and one power supply terminal of the semiconductor integrated circuit. One end is connected to the output electrode of the second bipolar transistor and the control electrode of the first bipolar transistor And a second resistor having the other end connected to the second power supply terminal and the other power supply terminal of the semiconductor integrated circuit. 2. The method according to claim 1, wherein said bipolar transistor is replaced with an MO.
2. The overcurrent protection circuit according to claim 1, wherein an S transistor is used.