JP2965595B2 - Redundant device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (FIG. 3) Problems to be solved by the invention Means for solving the problem (FIG. 1) Action Embodiment (a) One Description of Embodiment (FIG. 2) (b) Description of Other Embodiments [Overview] In a duplexer that duplicates the same functional circuit, performs the same operation, and outputs one output data,
Regarding a redundant device that performs an operation check between functional circuits, a plurality of functional circuits having the same function are provided for the purpose of performing data check at the time of bus output on the master side even if the enable generation circuit on the slave side fails, A data check circuit for checking the output data of the master function circuit and the slave function circuit, and performing the same operation and outputting the output data of the master function circuit on the bus. A timing circuit for outputting the output of the data check circuit at the timing of a master enable signal for controlling the timing of sending the output data of the master function circuit to the bus.

[Industrial applications]

The present invention relates to a duplexer that duplicates the same functional circuit, performs the same operation, and outputs one output data, and checks the operation between the functional circuits.

Error checking has been actively performed to improve the reliability of the device.

For the purpose of improving reliability, a duplex system has been proposed in which chips having the same function are provided in duplicate, operated in the same manner, and one output data is output, and both output data are checked. .

In this duplex system, there is a demand for efficient error checking.

[Conventional technology]

FIG. 3 is an explanatory view of the prior art, FIG. 3 (A) is an explanatory view of a chip duplex system, and FIG. 3 (B) is an explanatory view of a conventional check system.

As shown in FIG. 3A, the chip duplication system includes two operation chips 1a and 1b having the same operation function.

In the figure, a CPU (central processing unit) is shown, and a control chip 2, a bus (data bus A, data bus B) 4,
The memory control chip 3 and two operation chips 1a and 1b are connected.

One of the operation chips is the master chip 1a and the other is the slave chip 1b, and has the same circuit configuration.

The operation chips 1a and 1b take in data from the data bus B under the control of the control chip 2 and execute the same operation.

The operation result of the master chip 1a is output to the bus B,
The control chip 2 is notified and the slave chip 1b is notified.
To the check circuit CH of the slave chip 1b.
The calculation result of the slave chip 1b is checked, and the check result is notified to the control chip 2.

As described above, in a chip duplex system in which the operation chips 1a and 1b are duplicated, the same operation is performed, and the result of both operations is checked, attention is paid to the fact that a parity check and an ECC check, which are generally performed, are not required. ing.

That is, the parity check and the ECC check are used to detect the occurrence of an error by giving data redundancy, for example, the parity check requires one additional bit.

Therefore, the additional bits require an additional configuration on a circuit or a bus, and a parity generator and a parity checker are required. Be up.

However, if the parity check is stopped by duplicating the chip, the cost increases at first glance, but the chip is
Because it is made with LSI, the more you make it, the cheaper it becomes.

For this reason, the cost is reduced by duplicating the chip as compared with the case where the parity is added.

In such a chip duplex system, data check is indispensable, and conventionally, as shown in FIG. 3 (B).

The master chip 1a outputs the operation result from the driver 10a to the bus 4 by the master enable signal MST-ENABLE.

The slave chip 1b takes in the master output from the bus 4 with the receiver 11b, and performs EXOR (exclusive or)
The slave output and the master output are compared by the data check circuit 12 composed of a circuit, and the comparison result is output by the timing circuit 13 composed of an AND gate at the timing of the slave enable signal SLV-ENABLE.

In addition, 11a is a master side bus receiver, and 10b is a slave side bus driver.

As a result, it is possible to check the operation output of the master and the slave.

[Problems to be solved by the invention]

However, the prior art has the following problems because the check is performed at the timing of the enable signal on the slave side and only the data is checked.

Since the check is performed at the timing of the enable signal on the slave side, if the enable generation circuit on the slave side breaks down and the slave enable signal is not generated, the data check is not performed even if both the master and slave output.

Since only the data is checked, the master-side enable generation circuit breaks down and if the master enable signal is issued without permission, data is erroneously output from the master chip 1a onto the bus 4 and another chip (memory control chip 3) and a bus fight occurs, but this cannot be detected.

Accordingly, it is an object of the present invention to provide a duplexer capable of performing data check at the time of bus output on the master side even if the enable generation circuit on the slave side fails.

Another object of the present invention is to provide a duplexer capable of detecting a failure of the enable generation circuit on the master side.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

Claim 1 of the present invention is to provide a master function circuit 1a and a slave function circuit 1b having the same functions as shown in FIG. In a duplexer that outputs output data of the circuit 1a, a data check circuit 12 that checks output data of the master function circuit 1a and the slave function circuit 1b, and an output of the data check circuit 12 And a timing circuit 13 for outputting at the timing of the master enable signal which is the output timing of the operation result.

Further, claim 2 of the present invention is directed to a master function circuit 1a having the same function as shown in FIG.
And a slave function circuit 1b for performing the same operation, a data check circuit 12 for checking output data of the master function circuit 1a and the slave function circuit 1b, and transmission of each output data to the bus 4. An enable check circuit 14 checks a master enable signal of the master function circuit 1a for controlling timing and a slave enable signal of the slave function circuit 1b.

[Action]

In claim (1) of the present invention, since the check is performed at the timing of the enable signal on the master side, the check timing is the time when an output is actually output to the bus 4 from the master side.

Therefore, even if the enable generation circuit on the slave side fails, the data is checked when output data is output from the master to the bus 4, and the check race can be eliminated.

Note that a failure in which the enable signal on the master side is not output may be considered, but in this case, the data check is meaningless because the master data is not output to the bus 4.

Also, in claim (2) of the present invention, since the enable signals of the master and the slave are checked, if the enable generation circuit on the master side breaks down, it can be detected immediately.
There is no need to leave the bus fight state.

In addition, a failure of the enable signal generation circuit on the slave side can be detected.

〔Example〕

 (A) Description of one embodiment FIG. 2 is a configuration diagram of one embodiment of the present invention.

In the figure, the same components as those shown in FIGS. 1 and 3 are denoted by the same symbols.

The enable check circuit 14 detects a match or mismatch between the input master enable signal MST-ENABLE and the slave enable signal SLV-ENABLE formed by an EX-OR circuit.
Is output.

An OR gate 15 performs an OR operation on the data error of the AND gate 13 and the enable error of the enable check circuit 14, and outputs an error ERROR.

Reference numerals 16a and 16b denote enable permission gates, each of which is constituted by an output inversion type AND gate. The high level master chip instruction + MASTER-CHIP and the master enable signal respectively correspond to the low level slave chip instruction SLAVE-CHIP and the slave enable signal. Is input, and each driver 10
Output to a and 10b.

40 is an enable signal transmission line, and the master chip 1a
For transmitting a master enable signal from the slave chip 1b to the slave chip 1b.

When the master chip 1a and the slave chip 1b are determined,
A high-level master chip instruction + MASTER-CHIP is input to the master chip 1a, and the enable permission gate 16
a is opened and the driver 10a sends the master enable signal MST
It is driven according to −ENABLE.

On the other hand, a low-level slave chip instruction SLAVE-CHIP is input to the slave chip 1b, the AND gate 16b is closed, and the driving of the driver 10b by the slave enable SLV-ENABLE is prohibited.

Therefore, data output from the slave chip 1b to the bus 4 is prohibited.

Since the master chip 1a and the slave chip 1b have the same configuration, when the input data is supplied from the bus 4 and the operation is instructed, the same operation is executed, and in the output of the operation result, the master enable signal and the slave enable signal are output. Goes up.

In the master chip 1a, the driver 10a is driven by the master enable signal, and outputs a calculation result to the bus 4.

The operation result is input to the slave chip 1b from the bus 4, and the master enable signal is input to the slave chip 1b from the transmission line 40.

In the slave chip 1b, the result of the master operation of the bus 4 is received by the receiver 11b and input to the data check circuit 12.

Since the slave circuit result is input to the data check circuit 12, a match or mismatch with the master result is detected. If not, a high-level mismatch output is issued.
The timing circuit 13 outputs a data error at the timing of the master enable signal.

The master enable signal input to the slave chip 1b is checked with the slave enable signal by the enable check circuit 14, and if they do not match, a high-level enable error is issued.

The outputs of the timing circuit 13 and the enable check circuit 14 are output as an error ERROR through the OR gate 15, for example,
This is notified to the control chip 2 in FIG.

In this manner, the data is checked at the timing of the master enable, so that the master side transfers the data to the bus 4.
If you output to, data check is always performed.

Further, since the master and slave enable signals are checked, it is possible to immediately detect that the master-side enable generation circuit has failed, and the bus fight state is not left.

(B) Description of Another Embodiment In the above-described embodiment, the duplicated chip has been described as an arithmetic chip, but another chip may be used.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified in accordance with the gist of the present invention and is not excluded from the present invention.

[Effects of the Invention] As described above, the present invention has the following effects.

In claim (1), since the data is checked at the timing of the master enable, the data check is always performed if the master outputs data to the bus, and the data check is performed due to the failure of the slave enable generation circuit. Prevent the situation of disappearing.

In claim (2), since both the master and slave enable signals are checked, it is possible to immediately detect that the master-side enable generation circuit has failed, and it is possible to prevent the bus fight from being left unattended.

[Brief description of the drawings]

 FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. In the figure, 1a, 1b: functional chip, 4: bus, 12: data check circuit, 13: timing circuit, 14: enable check circuit.

Continuation of the front page (72) Inventor Eizo Ninoi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within Fujitsu Limited (56) References JP-A-1-154202 (JP, A) (58) Fields investigated (Int .Cl. ⁶ , DB name) G06F 11/16-11/20

Claims (2)

(57) [Claims] 1. A duplexer for providing a master function circuit and a slave function circuit each having the same function, performing the same operation, and outputting output data of the master function circuit on a bus, wherein the master function circuit and the slave function A data check circuit that checks the output data of the circuit; and a timing circuit that outputs the output of the data check circuit at the timing of a master enable signal that is the output timing of the operation result of the master function circuit. Duplex device. 2. A duplicate device comprising a master function circuit and a slave function circuit each having the same function and performing the same operation, comprising: a data check circuit for checking output data of the master function circuit and the slave function circuit; A duplexer, comprising: an enable check circuit for checking a master enable signal of a master function circuit for controlling a timing of sending each output data to a bus and a slave enable signal of a slave function circuit.