JP2969844B2 - Programmable controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual control system of a programmable controller having a so-called multi-scan system that executes a plurality of sequence processes at independent periods.

[Related Art] In a control system that requires high reliability of the system, a duplex configuration in which two control devices having the same configuration are connected in parallel is often adopted. Generally, in the case of a programmable controller having such a duplex configuration, the input section and the output section are made common and only the arithmetic section is duplicated. That is, data input from the common input unit is processed in parallel by the duplicated operation unit, and the operation result is output to the common output unit. Here, even if one of the duplicated operation units fails, the processing is continued in the other sound operation unit, so that the system does not stop.

However, in such a pluggable controller, when the operation content is divided into a plurality of parts and an attempt is made to realize a so-called multi-scan system in which each operation has a priority and a period, a synchronization shift between the duplicated operation units becomes a problem. In other words, if a low-priority scan (low-order scan) is interrupted and executed by a high-priority scan (high-order scan), a difference in the interrupt address due to a synchronization error between the arithmetic units of both systems causes a difference between the scans in both systems. There is a possibility that the shared data becomes inconsistent, resulting in an inconsistency in the operation of the sequence processing and an inconsistency in the output data.

As a method for preventing this, as disclosed in Japanese Patent Application Laid-Open No. Sho 59-72506, an address comparator and an address latch circuit are provided to compare the execution addresses of the microprocessors of both systems. There is a method in which interrupt processing is executed at the same address in both systems by holding the data while assuming that it is proceeding and holding the processing while assuming that the processing with a smaller execution address is delayed and continuing the processing.

[Problems to be Solved by the Invention] In the prior art described above, special hardware is required for synchronizing each instruction of the microprocessor, and an address which is not always executed like a recent microprocessor is required. If a method that prefetches the data is adopted, the realization of this method becomes considerably difficult.

In order to solve this problem, a method is conceivable in which interrupts are prohibited in a section for accessing shared data in the low-order scan sequence processing, and interrupt execution of the high-order scan is restricted. However, this method has a problem that the periodicity of the input / output processing of the high-order scan is lost.

The present invention has been made in order to solve the above-described problems. By performing scan-specific sequence processing and input / output processing at different timings,
An object of the present invention is to provide a programmable controller that guarantees the consistency of shared data between scans without impairing the periodicity of input / output processing.

Means for Solving the Problems In order to achieve the above object, the present invention has the following configuration. That is, in a redundant programmable controller having a multi-scan system, means for interrupting execution of sequence processing and input / output processing of a high-priority scan (high-order scan) at different timings;
An interrupt restriction section for prohibiting interrupt execution of the sequence processing and permitting execution of interrupts for the input / output processing in low-priority scans (low-order scans), and synchronization control means for synchronizing dual systems at the timing of the interrupt execution And performs scan-specific sequence processing and input / output processing.

[Operation] In the low-order scan sequence processing, by setting the section for accessing the shared data between scans as an interrupt restriction section, the interrupt execution of the high-order scan sequence processing is prohibited, and the shared data between scans in the duplex system is prohibited. Consistency is guaranteed. Further, in the input / output processing of the high-order scan, the execution of an interrupt is permitted even in the interrupt-limited section, so that the periodicity of the input / output processing is not impaired.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. A programmable controller 1 includes an input unit 2, duplicated operation units 3a and 3b, an output unit 4, and a duplicate synchronization control unit 5.

FIG. 2 is a flowchart showing an embodiment of the present invention. A plurality of scan processes 10 exist in the operation units 3a and 3b, and are executed at regular intervals with priorities, and execute the following steps.

(1) In order to match the timing of the start of the output processing of the arithmetic units 3a and 3b, the synchronous processing is performed using the duplicated synchronous control unit 5. (Step 1) (2) Output processing of the calculation result of the previous scan is performed.
(Step 2) (3) Synchronization processing is performed using the dual synchronization control unit 5 in order to match the timing of starting the input processing of the operation units 3a and 3b. (Step 3) (4) Input processing for the current scan is performed. (Step 4) (5) With reference to the interrupt limit state value of the low-order scan, if it is within the interrupt limit section (true), the processing is interrupted and the execution is shifted to the low-order scan, and if it is outside the interrupt limit section (false). Proceed to the next step. (Step 5) (6) Synchronization processing is performed using the duplex synchronization control unit 5 in order to match the timing of the start of the sequence processing by the arithmetic units 3a and 3b. (Step 6) (7) Set the self-scanning interrupt restriction state value to “true”. (Step 7) (8) One of a plurality of divided sequence processing units is executed. (Step 8) (9) The self-scanning interrupt restriction state value is set to “false”. (Step 9) (10) If there is a high-order scan in which the processing is suspended, the execution is moved to that. (Step 10) (11) Steps 7 to 10 are repeated for the remaining sequence processing units. (Step 11) The low-order scan sequence processing is divided into processing units each having an execution time shorter than the execution cycle time of the high-order scan, and at the same time, an interrupt restriction section. That is, the input / output processing of the high-order scan can always be executed by interrupting the low-order scan. However, the sequence processing of the high-order scan is such that the interrupt restriction state value becomes “true” during the execution of the sequence processing of step 8 in the low-order scan. Execution is prohibited. Further, when Steps 8 and 9 of the low-order scan are completed, the interrupt restriction state value becomes “false”, so that the sequence processing of the high-order scan can be executed.

As described above, the execution of the high-order scan sequence processing can be prevented during the execution of the low-order scan sequence processing, so that there is no inconsistency in the shared data between scans in the duplex system. Further, since the input / output processing of the high-order scan can always be executed by interruption, the fixed periodicity of the input / output processing is not impaired.

[Effects of the Invention] As described above, according to the present invention, there is no need to synchronize the dual system for each instruction of the microprocessor, so that special hardware is not required. In addition, since the multi-scan method can be realized without impairing the periodicity of the input / output processing, there is an effect that a reduction in performance due to duplication can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a duplicated programmable controller, and FIG. 2 is a flowchart showing a scanning operation of the programmable controller according to the present invention. 1 Programmable controller 2 Input part 3a, 3b Operation part 4 Output part 5 Synchronous control part 10 Scan processing

Claims (1)

(57) [Claims] In a redundant programmable controller having a multi-scan system for executing a plurality of sequence processes with independent cycles and priorities, interrupt execution of a high-priority scan sequence process and an input / output process at different timings. Means for interrupting, executing interrupts of the sequence processing in low-priority scanning, and permitting execution of interrupts of the input / output processing, and synchronization control means for synchronizing dual systems at the timing of the execution of the interrupts. A programmable controller that performs scan-specific sequence processing and input / output processing.