JPH0693240B2 - Program synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention increases the number of signal processing steps by deleting a synchronizing circuit for synchronizing a synchronizing signal from the outside and a signal processing program, particularly a flag sense and clear instruction. The present invention relates to a synchronization circuit for a target program.

[Prior Art] Conventionally, a digital signal processing device for handling a digital signal obtained by quantizing a voice signal or the like is disclosed in, for example, Japanese Patent Application Laid-Open No. 56-101266, and has a plurality of arithmetic processors having a plurality of sampling rates. It is composed by. When this arithmetic processing is executed by the digital signal processor of the micro program system, the synchronism of the filter arithmetic having a plurality of sampling rates is required.

For example, in order to synchronize the filter operation of 8 KHz and the filter operation of 32 KHz, it is necessary to execute the filter operation process of 32 KHz four times each time the filter operation process of 8 KHz is executed once. For this reason, a plurality of event flags are provided externally, and the setting / resetting of these flags is controlled by hardware or software, and the state of these flags is determined by a program (generally, this is a "flag sense" instruction. That is, the synchronization between the filter calculation processing and the synchronization with the interface for the external device were performed. Then, in a digital signal processing device realized by a microprogram method, when executing this kind of real-time calculation, the larger the number of processing steps of the program, the higher the calculation processing capacity,
Due to time constraints, it is often necessary to reduce the processing steps of the program.

Further, as program instructions for achieving synchronization, there are a "flag sense" instruction for determining whether a flag is on or off and a "flag clear" instruction for resetting a flag by a program, and these two instructions are synchronized. Since it is necessary for each cycle, the number of processing steps of the program cannot be reduced.

In order to reduce the number of processing steps of this program, the flag sense and clear are configured by one command, that is, a "flag sense and clear" command, and the flag determination and flag clear are performed in one step. Was being improved.

[Problems to be Solved by the Invention] However, in the conventional technique described above, at least one "flag sense and clear" instruction is required for each cycle in order to synchronize with one flag. Since the number of instructions cannot be reduced, in the field of digital signal processing that performs this kind of real-time processing, the number of steps for synchronization is reduced, and there is a limit to improving the arithmetic processing capacity by increasing the number of other processing steps. I was not satisfied.

The present invention is a digital signal processing device that requires a synchronization process with the outside.
The purpose is to enable reduction of "and-clear" instructions, to give flexibility to the program, and to improve the processing capability of the digital signal processor.

[Means for Solving Problems] The present invention is to provide the following means in a digital signal processing device which requires a synchronous operation of a periodic synchronizing signal from the outside and an internal program.

The hardware automatically sets the corresponding flag in each cycle in which the external periodic synchronization signal is obtained.

When the software has time, the software programs the "flag sense and clear" command within one cycle and resets the corresponding flag programmatically.

The software can reduce the "flag sense and clear" instruction when the signal processing steps in one cycle increase and there is no time margin. In this case, the hardware forcibly resets the corresponding flag before the arrival of the next periodic synchronization signal.

By such means, the synchronization flag is prevented from being continuously turned on, and the digital signal processing device can operate while maintaining synchronization with the external periodic synchronization signal.

[Operation] In the present invention, the setting and resetting of the flag corresponding to the external periodic synchronizing signal is executed as follows to perform the synchronizing operation of the signal processing device.

First, the flag is set every time the hardware automatically obtains the periodic synchronization signal.

The flag is normally reset within one cycle by a "flag sense and clear" instruction of software, but if the above instruction is deleted, the hardware will instead force it within that cycle.

In this way, the number of processing steps of the signal processing device increases, and even if the "flag sense and clear" instruction is unavoidably deleted, it is possible to prevent the flag from continuously turning on, and There is no error in the cycle determination.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1 is a set signal input terminal, 2 is a reset signal input terminal, 3 is a flip-flop for outputting a flag signal F, and 4 is a signal processor. Reference numeral 5 is a decoder for decoding an input signal and generating an output signal, 6 is an AND gate, 7 is an OR gate, and 8 is a test input terminal in the signal processor 4. Further, T ₁ is a flag set signal, T ₂ is a flag reset signal, D is an output signal from the decoder, and F is a flag signal output from the flip-flop 3.

Further, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, in which (a) is a flag set signal T ₁ , (b) is a flag reset signal T ₂ , (c) is a decoder output signal D, ( D) shows the waveform of the flag signal F, respectively.

The circuit operation of FIG. 1 will be described with reference to the waveforms of FIG. First, when the periodic flag set signal T ₁ is input from the set signal input terminal 1 to the set terminal S of the flip-flop 3, the flip-flop 3 is periodically set, and the flag signal F output from the terminal Q is High level. This flag signal F is input to the test input terminal 8 in the signal processor 4, and the signal processor 4 executes "flag sense and clear" by a program.
The state of the flag is determined by the instruction, and the execution address of the program is controlled according to the result. Decoder 5 at the same time
Outputs a pulsed decoder output signal D when this instruction is executed. The decoder output signal D is applied to one end of the input of the AND gate 6, and a logical product operation is performed with the flag signal F applied to the other end of the input, and the output signal is reset via the OR gate 7 to the flip-flop 3. Input to the terminal R. Therefore, when the program executes the "flag sense and clear" instruction, if the flip-flop 3 is already set and the flag signal F is at a high level, the AND gate 6 generates an output signal, so that the flip-flop 3 is reset and the flag is reset. The signal F goes low. The waveform of the flag signal F is shown in (d) of cycle (1) of FIG.

Next, when the "flag sense and clear" instruction is deleted, the decoder 5 does not generate the decoder output signal D even if the flag signal F is input to the test input terminal 8. However, since the flag reset signal T ₂ is directly input to the OR gate 7 from the reset input terminal 2 and its output is connected to the reset terminal R of the flip-flop 3,
The flag reset signal T ₂ resets the flip-flop 3 and the flag signal F becomes low level. The waveform of the flag signal F is shown in (d) of cycle (2) of FIG.

FIG. 3 is a flow chart of the program in this embodiment. In the figure, step 11 and step 14 are arithmetic processing S, step 12 and step 15 are arithmetic processing A,
Steps 13 and 15 show the calculation process C. Further, the arithmetic process S has a "flag sense and clear" command built therein.

FIG. 4 is a waveform diagram for explaining the program flow of FIG. In the figure, (a) is a periodic synchronization signal,
(B) is the flag set signal T ₁ generated by the rising edge of the periodic synchronization signal (a), (c) is the flag reset signal T ₂ generated by the falling edge of the periodic synchronization signal (a), ( (D) shows the respective arithmetic processing sequences of A, B, C, S, and (e) shows the waveform of the flag signal F.

Next, the operation of FIG. 3 will be described with reference to the waveforms of FIG.
In the cycle (0) of FIG. 4, the signal processing device executes the arithmetic processing S shown in step 11 of FIG. 3 as an initial operation. In this arithmetic processing S, "flag sense
Includes the "and clear" instruction. Therefore, in the next cycle (1) in FIG. 4, immediately after the flag signal F is turned on by the flag set signal T ₁ , the program is synchronized with the program at the program synchronization point indicated by P ₁ in the figure. , The flag signal F is reset. And steps 12, 13, and 14 in FIG.
The arithmetic processes A, B and S indicated by are respectively executed. In this cycle (1), since both the calculation processes A and B are short-time, the calculation process S can be executed within the cycle. Therefore, when the next cycle (2) is entered, the flag signal F is set and the same as in the previous cycle.
After synchronizing with the program at the program synchronization point indicated by P ₂ , the flag signal F is reset. Then, the arithmetic processes A and C shown in steps 15 and 16 of FIG. 3 are executed. However, since the arithmetic processing C has a large number of steps in the program, the processing time is extended to a part of the next cycle (3). Therefore, in this cycle (2), the arithmetic processing S is deleted and the arithmetic processing shown in steps 12, 13, and 14 of FIG. 3 is performed again.
The cycle (3) for executing A, B, S is entered. In this period (3), the flag signal F is set, but since the "flag sense and clear" instruction is deleted in the program, the flag signal F is not immediately reset, and the flag reset signal T ₂
Causes the hardware to be used to reset at point H in the figure. As a result, when the next period (4) is entered, the flag signal F is reset again after being synchronized at the program synchronization point P ₃ , and thereafter, repeatedly in synchronization with the periodic synchronization signal (a). A signal processing program can be executed.

[Effects of the Invention] As described in detail above, according to the present invention, the flag for synchronization of a program is set by hardware, and reset is performed by a "flag sense and reset" instruction by the program and by hardware. Since it is used together with the means for performing, the program synchronous processing can be maintained even if the "flag sense and clear" instruction is deleted when the number of processing steps of the program increases, so the arithmetic processing capacity by increasing the number of processing steps of the program Can be improved.

[Brief description of drawings]

FIG. 1 is a program synchronization circuit diagram according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a flow chart of a program according to the present invention, and FIG. 4 is a diagram of FIG. It is a waveform diagram for explaining a program flow. In the figure, 1 is a set signal input terminal, 2 is a reset signal input terminal, 3 is a flip-flop, 4 is a signal processor, 5 is a decoder, 6 is an AND gate, 7 is an OR gate, 8 is a test input terminal, and T ₁ is Flag set signal, T ₂
Is a flag reset signal, D is a decoder output signal, and F is a flag signal.

Claims (1)

[Claims] 1. A flag flip-flop set by the periodic synchronization signal for synchronizing the periodic synchronization signal input from the outside with the signal processing program, and the flag flip-flop set by the signal processing program. Resetting means for judging the state of the flag flip-flop and resetting, and the set flag flip-flop not reset by an instruction of the signal processing program,
A program synchronization circuit, comprising: a forced reset means for forcibly resetting the flag flip-flop before the next periodic signal of the periodic synchronization signal is input.