JP2970060B2 - Lead frame for resin-sealed semiconductor device - Google Patents
Lead frame for resin-sealed semiconductor deviceInfo
- Publication number
- JP2970060B2 JP2970060B2 JP3134526A JP13452691A JP2970060B2 JP 2970060 B2 JP2970060 B2 JP 2970060B2 JP 3134526 A JP3134526 A JP 3134526A JP 13452691 A JP13452691 A JP 13452691A JP 2970060 B2 JP2970060 B2 JP 2970060B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- lead
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/865—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止型半導体装置
用リードフレームに関し、特にＬＯＣ（Ｌｅａｄ Ｏｎ
Ｃｈｉｐ）用リードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a resin-encapsulated semiconductor device, and more particularly to a LOC (Lead On).
Chip) lead frame.
【０００２】[0002]
【従来の技術】従来のＬＯＣ用リードフレームは、図４
に示す様に内部リード１Ｃの下に両面に接着層を有する
テープ２が接着されている。半導体素子３は、テープ２
の下面に貼り付けられるような形で固着されて搭載され
る。次に、Ａｕワイヤ４によって内部リード１Ｃと半導
体素子３とが電気的に接続される。2. Description of the Related Art A conventional LOC lead frame is shown in FIG.
As shown in FIG. 7, a tape 2 having an adhesive layer on both sides is adhered below the internal lead 1C. The semiconductor element 3 is a tape 2
It is fixed and mounted in such a way as to be attached to the lower surface of the. Next, the internal lead 1 </ b> C and the semiconductor element 3 are electrically connected by the Au wire 4.
【０００３】この様にＬＯＣ用リードフレームは、内部
リード１Ｃが半導体素子３の上部に引き回せるため、半
導体素子の周辺に内部リード１ａを引き回す領域を必要
としない。従ってＬＯＣの樹脂封止型半導体装置は、半
導体素子搭載部を有し、その上部に半導体素子３を搭載
し、その周辺に内部リードを引き回す樹脂封止型半導体
素子に比べてより大きな半導体素子が搭載できる。As described above, in the LOC lead frame, since the internal lead 1C can be routed above the semiconductor element 3, there is no need for a region for routing the internal lead 1a around the semiconductor element. Therefore, the LOC resin-encapsulated semiconductor device has a semiconductor element mounting portion, on which the semiconductor element 3 is mounted, and a larger semiconductor element than the resin-encapsulated semiconductor element around which the internal leads are routed. Can be installed.
【０００４】[0004]
【発明が解決しようとする課題】この従来のＬＯＣ用リ
ードフレームでは、内部リード１Ｃの下面が平面である
ために、滑りやすくなっており、そのためボンディング
時において内部リード１Ｃが動いてしまい、内部リード
１ＣとＡｕリード４との接合が不十分になってしまう問
題点がある。In this conventional LOC lead frame, since the lower surface of the internal lead 1C is flat, it is slippery, so that the internal lead 1C moves during bonding and the internal lead 1C moves. There is a problem that the bonding between the 1C and the Au lead 4 becomes insufficient.
【０００５】本発明の目的は、このような問題を解決
し、内部リードのずれをなくし、Ａｕリードとその接合
を良好にできる樹脂封止型半導体装置用リードフレーム
を提供することにある。It is an object of the present invention to provide a lead frame for a resin-encapsulated semiconductor device which can solve such a problem, eliminate the displacement of the internal leads, and improve the bonding between the Au leads and the leads.
【０００６】[0006]
【課題を解決するための手段】本発明は、半導体素子上
の一平面に接着層を介して内部リードの下部を固着して
なる樹脂封止型半導体装置用リードフレームであって、
前記内部リードは、前記半導体素子と接触する面内に凹
部を有し、前記凹部に前記接着層で完全に覆われ、前記
凹部には前記接着層の接着剤が入り込んでいることを特
徴とする。さらに、本発明は、半導体素子上の一平面に
接着層を介して内部リードの下部を固着してなる樹脂封
止型半導体装置用リードフレームにおいて、前記内部リ
ードは、前記半導体素子と接触する面内にスルーホール
を有し、前記スルーホールの開口部は前記接着層の接着
剤で塞がれていることを特徴とする。SUMMARY OF THE INVENTION The present invention relates to a resin-encapsulated lead frame for a semiconductor device in which the lower portion of an internal lead is fixed to one surface of a semiconductor element via an adhesive layer,
The internal lead has a concave portion in a surface in contact with the semiconductor element, the concave portion is completely covered with the adhesive layer, and the adhesive of the adhesive layer enters the concave portion. . Further, the present invention provides a resin-encapsulated semiconductor device lead frame in which a lower portion of an internal lead is fixed to a plane on a semiconductor element via an adhesive layer, wherein the internal lead is in contact with the semiconductor element. A through hole, and an opening of the through hole is closed by an adhesive of the adhesive layer.
【０００７】[0007]
【実施例】図１は本発明の第一の実施例のＬＯＣ用リー
ドフレームの断面図である。図のように、内部リード１
はその下面がエッチングにより球面状に凹部５を設けら
れている。この凹部５にテープ２の上面の接着層が入り
こんで、内部リード１は滑りにくくなっている。さら
に、平面の場合より接着層と内部リード１の接着面が増
加するため、内部リード１とテープ２との接着力も向上
する。FIG. 1 is a sectional view of a LOC lead frame according to a first embodiment of the present invention. As shown, internal lead 1
Is provided with a concave portion 5 in a spherical shape on the lower surface by etching. The adhesive layer on the upper surface of the tape 2 penetrates into the concave portion 5, and the internal lead 1 is hard to slip. Further, since the bonding surface between the bonding layer and the internal lead 1 is increased as compared with the case of a flat surface, the bonding strength between the internal lead 1 and the tape 2 is also improved.
【０００８】図２は本発明の第二の実施例のＬＯＣ用リ
ードフレームの断面図である。この実施例では、凹部５
ａがプレスによりＶノッチの形で内部リード１ａの下面
に設けられている。FIG. 2 is a sectional view of a LOC lead frame according to a second embodiment of the present invention. In this embodiment, the recess 5
a is provided on the lower surface of the internal lead 1a in the form of a V notch by pressing.
【０００９】図３は本発明の第三の実施例のＬＯＣ用リ
ードフレームの断面図である。前記２例の場合、半導体
素子３をテープ２に貼り付ける際に凹部５，５ａに空気
が侵入してしまい、テープ２の接着層の接着剤が十分に
凹部に入り込まないという不具合が発生する可能性があ
る。そのため、本実施例では、凹部５，５ａの代りにス
ルーホール６を設けることにより、内部リード１ｂの下
面の空気が抜ける様にして確実にテープ２の接着層の接
着剤がスルーホール６に入り込むようにしている。FIG. 3 is a sectional view of a LOC lead frame according to a third embodiment of the present invention. In the case of the above two examples, when the semiconductor element 3 is attached to the tape 2, air may enter the recesses 5 and 5 a, causing a problem that the adhesive of the adhesive layer of the tape 2 does not sufficiently enter the recesses. There is. Therefore, in this embodiment, the through holes 6 are provided in place of the recesses 5 and 5a, so that the air on the lower surface of the internal lead 1b escapes and the adhesive of the adhesive layer of the tape 2 surely enters the through holes 6. Like that.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、テープの
接着層の接着剤がリードフレームの凹部やスルーホール
に入りこむ様にして、内部リードを滑りにくくし、さら
にテープとの接着面が増加したのでテープと内部リード
の接着力が向上し、平面の内部リードの場合に比べてさ
らに滑りにくくなっている。このような効果から従来は
２〜３％発生していた内部リードの滑りによるボンディ
ング不良が無くなったという効果が得られている。As described above, according to the present invention, the adhesive of the adhesive layer of the tape enters the recesses and through holes of the lead frame, thereby preventing the internal leads from slipping and increasing the adhesive surface with the tape. As a result, the adhesive strength between the tape and the internal lead is improved, and the tape is less slippery than a flat internal lead. From such an effect, the effect that the bonding failure due to the sliding of the internal lead, which has conventionally occurred by 2 to 3%, is eliminated.
【図１】本発明の第一の実施例のＬＯＣ用リードフレー
ムの断面図。FIG. 1 is a sectional view of a LOC lead frame according to a first embodiment of the present invention.
【図２】本発明の第二の実施例のＬＯＣ用リードフレー
ムの断面図。FIG. 2 is a sectional view of a LOC lead frame according to a second embodiment of the present invention.
【図３】本発明の第三の実施例のＬＯＣ用リードフレー
ムの断面図。FIG. 3 is a sectional view of a LOC lead frame according to a third embodiment of the present invention.
【図４】従来例のＬＯＣ用リードフレームの断面図。FIG. 4 is a cross-sectional view of a conventional LOC lead frame.
１ 内部リード ２ テープ ３ 半導体素子 ４ Ａｕワイヤ ５，５ａ 凹部 ６ スルーホール DESCRIPTION OF SYMBOLS 1 Internal lead 2 Tape 3 Semiconductor element 4 Au wire 5, 5a Depression 6 Through hole
Claims (2)
部リードの下部を固着してなる樹脂封止型半導体装置用
リードフレームにおいて、前記内部リードは、前記半導
体素子と接触する面内に凹部を有し、前記凹部に前記接
着層で完全に覆われ、前記凹部には前記接着層の接着剤
が入り込んでいることを特徴とする樹脂封止型半導体装
置用リードフレーム。1. A lead frame for a resin-encapsulated semiconductor device in which a lower portion of an internal lead is fixed to a flat surface on a semiconductor element via an adhesive layer, wherein the internal lead is provided in a plane contacting the semiconductor element. A lead frame for a resin-encapsulated semiconductor device, wherein the recess is completely covered with the adhesive layer, and the adhesive of the adhesive layer enters the recess.
部リードの下部を固着してなる樹脂封止型半導体装置用
リードフレームにおいて、前記内部リードは、前記半導
体素子と接触する面内にスルーホールを有し、前記スル
ーホールの開口部は前記接着層の接着剤で塞がれている
ことを特徴とする樹脂封止型半導体装置用リードフレー
ム。2. A resin-encapsulated semiconductor device lead frame in which a lower portion of an internal lead is fixed to a plane on a semiconductor element via an adhesive layer, wherein the internal lead is formed in a plane contacting the semiconductor element. A lead frame for a resin-sealed semiconductor device, characterized in that a through hole is provided, and an opening of the through hole is closed by an adhesive of the adhesive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134526A JP2970060B2 (en) | 1991-06-06 | 1991-06-06 | Lead frame for resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3134526A JP2970060B2 (en) | 1991-06-06 | 1991-06-06 | Lead frame for resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04359461A JPH04359461A (en) | 1992-12-11 |
| JP2970060B2 true JP2970060B2 (en) | 1999-11-02 |
Family
ID=15130384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3134526A Expired - Fee Related JP2970060B2 (en) | 1991-06-06 | 1991-06-06 | Lead frame for resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2970060B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002181A (en) * | 1994-11-08 | 1999-12-14 | Oki Electric Industry Co., Ltd. | Structure of resin molded type semiconductor device with embedded thermal dissipator |
| US6531784B1 (en) * | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
-
1991
- 1991-06-06 JP JP3134526A patent/JP2970060B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04359461A (en) | 1992-12-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |