JP2972452B2 - Receive data identification circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for transmitting digital signals. The present invention relates to a reception data identification circuit according to the CCITT I-430 recommendation, and more particularly to a reception data identification circuit capable of securing a sampling margin of 100%.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional received data identification circuit converts a received signal of a positive direction code and a received signal of a negative direction code received by a data receiving circuit 24 into U / B (unipolar / bipolar) conversion. And output U / B conversion circuit 27
And a violation detection circuit 25 for inputting a positive-direction received signal and a negative-direction received signal, and an F-bit change signal for receiving an output signal of the violation detection circuit 25 and outputting an F-bit change point detection signal. Point detection circuit 26
A clock generation circuit 28 which receives an output signal of the F-bit change point detection circuit 26 and outputs a clock signal;
Data dividing circuit 29 which receives the output signal of / B conversion circuit 27 and the output of clock generation circuit 28 and divides the received data
And

[0003]

In such a conventional reception data discriminating circuit, the reception data is directly U / B converted and divided, so that if there is a large phase change at the time of data sampling, the sampling is not performed. There has been a problem that the margin is small, the amount of delay of the received data varies due to the code correlation, and the sampling range for the phase change is limited.

The present invention solves such a problem. A receiving data identification circuit capable of securing a sampling margin of 100% without being limited by a sampling range for a phase change even when a large phase change occurs. The purpose is to provide.

[0005]

According to the present invention, there is provided a receiving circuit for receiving a signal of a positive sign and a negative sign, and a U / B (unipolar / bipolar) conversion of the signal received by the receiving circuit for output. A U / B conversion circuit, a violation detection circuit for detecting a violation of the signal received by the receiving circuit, and an F for receiving an output signal of the violation detection circuit and outputting an F-bit change point detection signal
A bit change point detection circuit, a clock generation circuit that receives an output signal of the F bit change point detection circuit and outputs a clock signal, an output of the clock generation circuit, and the U /
A data dividing circuit for inputting and dividing an output of a B conversion circuit, wherein a positive direction code, a negative direction code, and a zero code are delayed toward a delay frame side before the U / B conversion, and It is characterized by including a waveform generation circuit that matches and outputs the phases of the sign, the negative sign, and the zero sign.

The waveform generating circuit includes a first counting circuit for delaying a positive code signal from the data receiving circuit for a predetermined time, and a first differential circuit for inputting a positive code signal from the data receiving circuit. A clamp circuit for receiving an output signal of the first differentiating circuit and an output signal of the F-bit change point detection circuit and outputting a signal for resetting the first count circuit; An L-bit identification circuit that receives an output signal of the circuit and outputs an L-bit signal; a second count circuit that receives a signal having a negative sign from the data receiving circuit; A second differentiating circuit for receiving a signal and outputting a signal for resetting the second counting circuit, an output of the F-bit change point detecting circuit, and an output of the L-bit identifying circuit. A gate circuit that inputs a signal of a positive sign and a negative sign from the data receiving circuit and outputs a reset signal; a third count circuit that receives an output of the gate circuit; A third differentiation circuit that receives a circuit output signal and outputs a reset signal that resets the third count circuit, and the first count circuit, the second count circuit, and the third count circuit. It is desirable to include a phase matching circuit that receives an output signal, performs phase matching, and outputs the result.

[0007]

Before the U / B conversion, the positive direction code, the negative direction code, and the zero value code are delayed toward the delay frame side to ensure 100% waveform duty, and the waveform generation circuit generates a positive direction code, a negative direction code, Data is divided and output according to the respective phases of the zero value code.

Thus, it is possible to eliminate the deviation of the frame phase and the variation of the duty of the code correlation.
A 100% data sampling margin can be secured.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a waveform generation circuit according to an embodiment of the present invention.

In the embodiment of the present invention, a data receiving circuit 1 for receiving a signal of a positive direction code and a signal of a negative direction code, and a U / B (unipolar / bipolar) conversion of the signal received by the data receiving circuit 1 is output. A U / B conversion circuit 5, a violation detection circuit 3 for detecting the violation of the signal received by the data receiving circuit 1, and an output signal of the violation detection circuit 3 are input to output an F-bit change point detection signal. F bit change point detection circuit 4, clock generation circuit 6 which receives the output signal of F bit change point detection circuit 4 and outputs a clock signal, output of clock generation circuit 6 and output of U / B conversion circuit 5 And a data dividing circuit 7 for inputting and dividing the input signal, and as a feature of the present invention, a positive sign, a negative sign and a zero sign are delayed before U / B conversion. Comprising positive sign by delaying the arm side, negative sign, and zero symbols each waveform generating circuit 2 to output the combined phases.

The waveform generating circuit 2 includes a data receiving circuit 1
A first count circuit 8 for delaying the signal of the positive direction from the first receiving circuit 1, a first differentiating circuit 11 for inputting the signal of the positive direction from the data receiving circuit 1, and a first differential circuit 11 An output signal and an output signal of the F-bit change point detection circuit 4 are input, and a clamp circuit 12 that outputs a signal for resetting the first count circuit 8 is input. An L-bit identification circuit 15 that outputs a signal; a second count circuit 17 that receives a signal of a negative sign from the data receiving circuit 1; a second signal that receives a signal of a negative sign from the data receiving circuit 1; A second differentiating circuit 19 for outputting a signal for resetting the count circuit 17 of the second circuit, a reset circuit 16 for receiving an output of the F-bit change point detecting circuit 4 and an output of the L-bit identifying circuit 15, A gate circuit 20 for inputting a signal of a positive sign and a negative sign from the communication circuit 1 and outputting a reset signal, a third count circuit 21 for receiving an output of the gate circuit 20, and an output signal of the gate circuit 20. A third differentiating circuit 22 that outputs a reset signal for resetting the third count circuit 21 that is input, and an output signal of the first count circuit 8, the second count circuit 17, and the third count circuit 21 is input. And a phase matching circuit 23 for performing phase matching and outputting.

Next, the operation of the embodiment of the present invention thus configured will be described.

When the data receiving circuit 1 receives data,
The violation detection circuit 3 detects a violation of the received waveform, and then detects F after the detection of the violation.
The bit change point is detected by the F bit change point detection circuit 4.

On the other hand, in order to compensate for an output frame phase between terminals by an extended passive bus or the like in a connection configuration according to CCITT I-430, an L bit identification circuit 15 of the waveform generation circuit 2 identifies L bits of a lag phase frame. Then, after detecting the violation via the clock generation circuit reset signal line 18 for clamping the output of the clock generation circuit 6 until the L bit is no longer identified, the delay until the L bit of the delayed phase frame is no longer identified. No clock is output to the second count circuit 17 which is a circuit, and only the data bits are output to the second count circuit 17.
Output to delay.

Due to this delay, the duty varies due to the code correlation of the waveform, and when the slice level is high, the duty can be corrected to 100% without reduction in the duty, and the positive sign, the negative sign, Regarding the phase difference between the zero-value code and the zero-value code, the phases of the respective codes can be matched by the phase matching circuit 23 in the next stage.

As the phase matching circuit 23, a data latch circuit such as a flip-flop circuit can be used, and a circuit such as a selector for adjusting a code-divided waveform at a certain time interval can be used to achieve 100% duty ratio. It is possible to generate a waveform having a phase matching the delay side frame, which is 100 times smaller than the conventional sampling margin.
% Margin can be secured.

[0017]

As described above, according to the present invention, 1
While ensuring a duty of 00%,
Since the phases between the codes can be appropriately adjusted, there is an effect that the sampling margin hindered by the phase difference between the received data frames and the code correlation can be maximized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a waveform generation circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 24 data reception circuit 2 waveform generation circuit 3, 25 violation detection circuit 4, 26 F bit change point detection circuit 5, 27 U / B conversion circuit 6, 28 clock generation circuit 7, 29 data division circuit 8 first Count circuit 9 Positive sign signal line 10 F bit change point detection signal line 11 First differentiating circuit 12 Clamp circuit 14 Negative sign signal line 15 L bit discriminating circuit 16 Reset circuit 17 Second count circuit 18 Clock generation circuit reset Signal line 19 Second differentiation circuit 20 Gate circuit 21 Third counting circuit 22 Third differentiation circuit 23 Phase matching circuit

Claims (2)

(57) [Claims] A receiving circuit for receiving a signal of a positive sign and a signal of a negative sign; a U / B converting circuit for converting a signal received by the receiving circuit into a U / B (unipolar / bipolar) signal and outputting the converted signal; A violation detection circuit for detecting a violation of the signal received by the receiving circuit; an F-bit change point detection circuit for receiving an output signal of the violation detection circuit and outputting an F-bit change point detection signal; A reception data identification circuit comprising: a clock generation circuit that receives an output signal of a point detection circuit and outputs a clock signal; and a data division circuit that receives and divides the output of the clock generation circuit and the output of the U / B conversion circuit. In the above, before the U / B conversion, the positive direction code, the negative direction code, and the zero code are delayed toward the delay frame side so that the positive direction code, the negative direction code, and the 1. A received data identification circuit comprising: a waveform generation circuit that matches and outputs the phases of zero and zero signs. 2. A waveform generating circuit comprising: a first count circuit for delaying a signal of a forward direction from the data receiving circuit for a predetermined time; and a first circuit for receiving a signal of a forward direction from the data receiving circuit. A clamp circuit that receives an output signal of the first differentiator circuit and an output signal of the F-bit change point detection circuit, and outputs a signal for resetting the first count circuit; An L-bit identification circuit that receives an output signal of the point detection circuit and outputs an L-bit signal; a second count circuit that receives a signal of a negative sign from the data receiving circuit; and a negative direction from the data receiving circuit Input the sign signal,
A second differentiation circuit that outputs a signal for resetting the second count circuit; a reset circuit that receives an output of the F-bit change point detection circuit and an output of the L-bit identification circuit; A gate circuit for receiving a signal of a direction code and a negative direction code and outputting a reset signal; a third count circuit for receiving an output of the gate circuit; and a third count circuit for receiving an output signal of the gate circuit. A third differentiating circuit for outputting a reset signal for resetting, and a phase matching for inputting output signals of the first count circuit, the second count circuit, and the third count circuit, performing phase matching, and outputting the signals. The received data identification circuit according to claim 1, further comprising a circuit.