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JP2979752B2 - Manufacturing method of semiconductor quantum well box - Google Patents
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JP2979752B2 - Manufacturing method of semiconductor quantum well box - Google Patents

Manufacturing method of semiconductor quantum well box

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Publication number
JP2979752B2
JP2979752B2 JP19265591A JP19265591A JP2979752B2 JP 2979752 B2 JP2979752 B2 JP 2979752B2 JP 19265591 A JP19265591 A JP 19265591A JP 19265591 A JP19265591 A JP 19265591A JP 2979752 B2 JP2979752 B2 JP 2979752B2
Authority
JP
Japan
Prior art keywords
quantum well
semiconductor
well box
semiconductor quantum
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19265591A
Other languages
Japanese (ja)
Other versions
JPH04306897A (en
Inventor
俊介 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Sheet Glass Co Ltd
Original Assignee
Nippon Sheet Glass Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Sheet Glass Co Ltd filed Critical Nippon Sheet Glass Co Ltd
Priority to JP19265591A priority Critical patent/JP2979752B2/en
Publication of JPH04306897A publication Critical patent/JPH04306897A/en
Application granted granted Critical
Publication of JP2979752B2 publication Critical patent/JP2979752B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体量子井戸箱の製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor quantum well box.

【0002】[0002]

【従来の技術】厚さが数nm〜数10nmの範囲で、異なる
禁制帯幅をもつ2種類の超薄膜を周期的に積み重ねた半
導体積層構造(多重量子井戸構造)では、バルク半導体
にはない物理現象が生まれ、各種デバイスに応用されて
いる。たとえば、AlGaAs/GaAs多重量子井戸
構造を活性層に利用した半導体レ−ザでは、発振しきい
値電流の低減、スペクトルライン幅の低減、高出力化な
どの優れた特性が報告されてきた。前記の物理現象は、
多重量子井戸構造内で膜厚方向に周期化したポテンシャ
ルの底(量子井戸内部)に荷電粒子が閉じ込められる
(量子サイズ効果)ことに起因している。一方、膜厚方
向のみならず、面内方向にも量子井戸を形成する量子細
線構造あるいは量子井戸箱構造では、荷電粒子の閉じ込
め効果がさらに顕著となり、半導体レ−ザなどのデバイ
スの特性を向上させることができる。
2. Description of the Related Art A bulk semiconductor does not have a semiconductor stacked structure (multiple quantum well structure) in which two types of ultrathin films having different band gaps are periodically stacked in a thickness range of several nm to several tens nm. Physical phenomena are born and applied to various devices. For example, in a semiconductor laser using an AlGaAs / GaAs multiple quantum well structure for an active layer, excellent characteristics such as a reduction in oscillation threshold current, a reduction in spectral line width, and an increase in output have been reported. The physical phenomenon described above is
This is due to the fact that charged particles are confined (quantum size effect) at the bottom of the potential (inside the quantum well) periodicized in the film thickness direction in the multiple quantum well structure. On the other hand, in a quantum wire structure or a quantum well box structure in which quantum wells are formed not only in the film thickness direction but also in the in-plane direction, the effect of confining charged particles becomes more remarkable and the characteristics of devices such as semiconductor lasers are improved. Can be done.

【0003】量子サイズ効果の現れる一辺の長さが数nm
〜数10nmの半導体量子井戸箱を製造するために、従来
は電子ビ−ム露光技術に代表される超微細加工技術によ
って試みられていた。これは、膜厚と界面の急峻性の制
御に優れた半導体積層技術を利用する方法であり、まず
はじめにMOVPE法(有機金属気相成長法)やMBE
法(分子線エピタキシ法)によって積層構造の制御され
た半導体量子井戸構造を作製し、その後上記超微細加工
技術によって微細なグリッドパタ−ンをレジストなどで
形成し、これをマスクとして選択エッチングを行うこと
により、半導体量子井戸箱を製造しようとするものであ
る。(ジャ−ナル・オブ・バキュ−ム・サイエンス.テ
クノロジイ(J.Vac.Sci.Technol)B
4.358(1986))。
The length of one side at which the quantum size effect appears is several nm
Conventionally, in order to manufacture a semiconductor quantum well box of up to several tens of nanometers, an attempt has been made by an ultrafine processing technique represented by an electron beam exposure technique. This is a method that utilizes a semiconductor lamination technology that is excellent in controlling the film thickness and the steepness of the interface. First, a MOVPE (metal organic chemical vapor deposition) method or an MBE method
A semiconductor quantum well structure having a controlled laminated structure is formed by a method (molecular beam epitaxy), and then a fine grid pattern is formed with a resist or the like by the above-mentioned ultrafine processing technique, and selective etching is performed using this as a mask. This aims to manufacture a semiconductor quantum well box. (Journal of Vacuum Science Technology B)
4.358 (1986)).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
半導体量子井戸箱の製造方法においては、超微細加工技
術の加工精度が荒く、量子サイズ効果が現れる一辺の長
さが数nm〜数10nmで、かつ大きさの揃った量子井戸箱
を再現性良く製造することは困難であった。加工精度が
荒くなる原因は、選択エッチングの際のエッチング速度
の大きなばらつきやサイドエッチングなどにあった。
However, in the conventional method of manufacturing a semiconductor quantum well box, the processing accuracy of the ultrafine processing technique is rough, and the length of a side where a quantum size effect appears is several nm to several tens nm. And it was difficult to manufacture quantum well boxes of uniform size with good reproducibility. The causes of the rough processing accuracy were large variations in the etching rate during selective etching and side etching.

【0005】本発明はこのような事情に鑑みなされたも
ので、積層構造を選択エッチングするという従来技術と
は異なる技術的手段によって、量子サイズ効果が現れる
一辺の長さが数nm〜数10nmでかつ大きさの揃った半導
体量子井戸箱を、加工精度よく作製するものである。
The present invention has been made in view of such circumstances, and a technique for selectively etching a laminated structure, which is different from the conventional technique, has a side on which a quantum size effect appears, having a length of several nm to several tens of nm. A semiconductor quantum well box of uniform size is manufactured with high processing accuracy.

【0006】[0006]

【課題を解決するための手段】請求項1の半導体量子井
戸箱の製造方法は、第1の半導体材料上に金属超微粒子
を2次元的に規則正しく並べ、前記金属超微粒子間に第
1の半導体材料を選択成長させた後、前記金属超微粒子
を除去することによって形成される穴部に、前記第1の
半導体材料よりも禁制帯幅の小さな第2の半導体材料を
埋め込むことを特徴とする。
According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor quantum well box, wherein metal ultrafine particles are regularly arranged two-dimensionally on a first semiconductor material, and the first semiconductor material is interposed between the metal ultrafine particles. After selectively growing the material, a second semiconductor material having a smaller forbidden band width than the first semiconductor material is embedded in a hole formed by removing the ultrafine metal particles.

【0007】本発明の技術的手段の第1の特徴は、結晶
成長の初期過程において形成される超微粒子が、エネル
ギ−的により安定に存在できる位置に移動することを原
理として作られる金属超微粒子を、半導体量子井戸箱を
埋め込むための穴部を精度よく作製するために利用する
ことにある。
A first feature of the technical means of the present invention is that metal ultrafine particles formed on the principle that ultrafine particles formed in the initial stage of crystal growth move to a position where they can exist more stably in terms of energy. In order to accurately form a hole for embedding a semiconductor quantum well box.

【0008】第2の特徴は、前記穴部内の結晶面とそれ
以外の結晶面での結晶成長速度の違いを利用して、穴部
のみに目的とする半導体量子井戸箱を成長させることに
ある。
A second feature is that a target semiconductor quantum well box is grown only in the hole by utilizing the difference in the crystal growth rate between the crystal plane in the hole and the other crystal plane. .

【0009】[0009]

【作用】本発明によれば、大きさが数nm〜数10nmの範
囲で揃い、かつ2次元的に規則正しく配列した金属超微
粒子を利用することによって、金属超微粒子と同様の穴
部を障壁層に形成することができる。さらに、以上のよ
うに形成された穴部に半導体材料を選択成長させること
を利用して、穴部と同様に大きさが数nm〜数10nmの範
囲で揃い、かつ2次元的に規則的に配列した半導体量子
井戸箱を再現性良く製造することができる。またこの行
程を繰り返し行うことによって、3次元的に規則正しく
配列した半導体量子井戸箱を製造することができる。
According to the present invention, by using metal ultrafine particles having a size in the range of several nm to several tens nm and arranged two-dimensionally regularly, the same hole as the metal ultrafine particles can be formed in the barrier layer. Can be formed. Further, by utilizing the selective growth of the semiconductor material in the hole formed as described above, the size is uniform in the range of several nm to several tens nm in the same manner as the hole, and two-dimensionally regular. The arrayed semiconductor quantum well boxes can be manufactured with high reproducibility. By repeating this process, semiconductor quantum well boxes arranged three-dimensionally and regularly can be manufactured.

【0010】[0010]

【実施例】以下、本発明の一実施例を添付図面に基づい
て説明する。図1は本発明による半導体量子井戸箱の製
造手順を説明する図である。図1(a)に示すように、
まず始めに、面方位(100)のGaAs基板1上に障
壁層とするAlGaAs層2を100nmの厚さに通常の
MBE法によって成長した。次にMBEチャンバ内にシ
ランガスをチャンバ内圧力が5〜10Torrになるように
導入し、AlGaAs層2上にグリッドパタ−ン(縞間
隔30nm)で電子ビ−ムを照射し、シリコンを析出させ
た。照射に使用した電子ビ−ムは、加速電圧20kV、
ビ−ム電流2×10-7A、ビ−ム径4nmで、これにより
幅5nmのシリコングリッドパタ−ン3が形成された。図
1(b)に示すように、シリコンによるグリッドパタ−
ン3形成後、再びチャンバ内を超高真空状態に排気し、
金を5nmの厚さに蒸着してから240℃に加熱すると、
シリコングリッドパタ−ン3に整然と沿って一辺が約1
0nmの金超微粒子4が形成された。これは、金の超微粒
子の気相との界面エネルギ−よりもシリコン固相との界
面エネルギ−の方が低くく、安定に存在できるためと考
えられる。次に図1(c)、(d)に示すように、試料
をチャンバ外に取り出し、ふっ酸:硝酸:酢酸=1:
4:3の混合液でシリコングリッドパタ−ン3を選択エ
ッチングすることによって除去し、AlGaAs層2上
に一辺が約10nmの金超微粒子4のみを約10nmの間隔
で残した。図1(e)に示すように、その結果できた金
超微粒子4間の隙間にMBE法によってAlGaAs5
を選択成長した。その際の成長温度は400℃である。
AlGaAs5を選択成長した後再度チャンバ外に試料
を取り出し、金超微粒子4の選択エッチングを行った。
エッチング液には水とメタノ−ルの混合溶媒(40c
c:60cc)にヨ−ド(1.2g)とヨウ化アンモニ
ウム(8g)を溶解した液を使用した。図1(f)に示
すように、金超微粒子4をエッチングすることによって
できる規則正しく配列した直径10nm程度の穴部6に井
戸層とするGaAsをMBE法によって選択成長した。
その際の成長温度は350〜500℃であり、この時、
結晶成長速度の面方位依存性によって穴部6のみに選択
的にGaAsの成長が起こった。GaAsを選択成長し
た後、障壁層であるAlGaAs層8を全面に成長し
た。さらに以上のプロセスを繰り返すことによって、3
次元的に規則正しく配列したGaAs量子井戸箱7を製
造することができた。これをフォトルミネッセンスで評
価したところ、発光スペクトルのピ−ク位置が井戸幅1
0nmのGaAs量子井戸と比較して高エネルギ−側へシ
フトしており、GaAsが量子井戸箱として機能してい
ることを確認できた。
An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a view for explaining a procedure for manufacturing a semiconductor quantum well box according to the present invention. As shown in FIG.
First, an AlGaAs layer 2 serving as a barrier layer was grown on a GaAs substrate 1 having a plane orientation (100) to a thickness of 100 nm by a normal MBE method. Next, silane gas was introduced into the MBE chamber so that the pressure in the chamber was 5 to 10 Torr, and electron beams were irradiated onto the AlGaAs layer 2 with a grid pattern (stripes of 30 nm) to deposit silicon. . The electron beam used for irradiation was an accelerating voltage of 20 kV,
A silicon grid pattern 3 having a beam current of 2 × 10 -7 A and a beam diameter of 4 nm was formed with a width of 5 nm. As shown in FIG. 1B, a grid pattern made of silicon is used.
After forming the chamber 3, the chamber is again evacuated to an ultra-high vacuum state,
When gold is deposited to a thickness of 5 nm and heated to 240 ° C,
One side is approximately 1 along the silicon grid pattern 3
Ultrafine gold particles 4 having a thickness of 0 nm were formed. This is presumably because the interface energy between the ultrafine gold particles and the silicon solid phase is lower than the interface energy between the ultrafine gold particles and the gas phase, and the gold can be stably present. Next, as shown in FIGS. 1C and 1D, the sample was taken out of the chamber, and hydrofluoric acid: nitric acid: acetic acid = 1: 1.
The silicon grid pattern 3 was removed by selective etching with a 4: 3 mixture, leaving only the gold ultrafine particles 4 having a side of about 10 nm on the AlGaAs layer 2 at intervals of about 10 nm. As shown in FIG. 1E, a gap between the resulting ultrafine gold particles 4 was formed into AlGaAs 5 by MBE.
Select grown. The growth temperature at that time is 400 ° C.
After the selective growth of AlGaAs5, the sample was taken out of the chamber again, and the ultrafine gold particles 4 were selectively etched.
A mixed solvent of water and methanol (40 c
c: 60 cc) was used in which iodine (1.2 g) and ammonium iodide (8 g) were dissolved. As shown in FIG. 1F, GaAs serving as a well layer was selectively grown by MBE in a hole 6 having a diameter of about 10 nm, which was regularly arranged by etching the ultrafine gold particles 4.
The growth temperature at that time is 350 to 500 ° C.
GaAs was selectively grown only in the hole 6 due to the plane orientation dependence of the crystal growth rate. After selective growth of GaAs, an AlGaAs layer 8 as a barrier layer was grown on the entire surface. By repeating the above process, 3
The GaAs quantum well boxes 7 which were regularly arranged dimensionally could be manufactured. When this was evaluated by photoluminescence, the peak position of the emission spectrum was 1 well width.
As compared with the GaAs quantum well of 0 nm, the energy is shifted to the higher energy side, confirming that GaAs functions as a quantum well box.

【0011】本実施例では、GaAs/AlGaAs系
半導体量子井戸箱の作製方法について述べたが、これに
限ることなく、たとえば、InAs/GaInAs系な
どのIII−V族化合物半導体やII−VI族化合物半導体に
おいても同様の半導体量子井戸箱を製造することができ
る。
In this embodiment, a method of manufacturing a GaAs / AlGaAs semiconductor quantum well box has been described. However, the present invention is not limited to this. For example, a III-V group compound semiconductor such as an InAs / GaInAs group or a II-VI group compound semiconductor can be used. A similar semiconductor quantum well box can be manufactured for a semiconductor.

【0012】また本実施例では、結晶成長手段としてM
BE法を使用したが、これに限ることなく、MOVPE
法を使用することもできる。
In this embodiment, the crystal growth means is M
Although the BE method was used, the MOVPE method is not limited to this.
Laws can also be used.

【0013】さらに本実施例では、金属超微粒子として
金を使用したが、これに限ることなく、たとえば、アル
ミニウムなどの金属を使用することもできる。
Further, in this embodiment, gold is used as the ultrafine metal particles. However, the present invention is not limited to this. For example, a metal such as aluminum can be used.

【0014】この他本実施例では、グリッドパタ−ンに
シリコンを使用したが、これに限らず、たとえば、ガリ
ウムやゲルマニウムなどの金属、カ−ボンや窒素などの
化合物をグリッドパタ−ンの材料として使用することも
できる。
In this embodiment, silicon is used for the grid pattern. However, the present invention is not limited to this. For example, a metal such as gallium or germanium, or a compound such as carbon or nitrogen may be used as a material for the grid pattern. It can also be used as

【0015】[0015]

【発明の効果】本発明によれば、従来不可能であった一
辺の長さが数nm〜数10nmでかつ大きさの揃った半導体
量子井戸箱を3次元的に規則正しく配列させた構造で、
再現性良く容易に製造することができた。さらに本発明
により作製した半導体量子井戸箱を半導体レ−ザの活性
層に利用した結果、発振しきい値電流、スペクトルライ
ン幅などにおいて、従来の半導体レ−ザの性能を凌ぐ半
導体量子井戸箱レ−ザを作製することができた。
According to the present invention, there is provided a structure in which semiconductor quantum well boxes having a side length of several nm to several tens nm and having a uniform size, which are impossible in the past, are regularly arranged three-dimensionally.
It could be easily manufactured with good reproducibility. Further, as a result of utilizing the semiconductor quantum well box manufactured according to the present invention for the active layer of the semiconductor laser, the semiconductor quantum well box laser has a higher oscillation threshold current, spectral line width, etc. than the performance of the conventional semiconductor laser. -Then could be made.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1(a)〜(c)は本発明の実施例に係わる
半導体量子井戸箱の製造手順を説明する斜視図である。
図1(d)〜(f)は本発明の実施例に係わる半導体量
子井戸箱の製造手順を説明する断面図である。
FIGS. 1A to 1C are perspective views illustrating a procedure for manufacturing a semiconductor quantum well box according to an embodiment of the present invention.
FIGS. 1D to 1F are cross-sectional views illustrating a procedure for manufacturing a semiconductor quantum well box according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 AlGaAs層 3 シリコングリッドパタ−ン 4 金超微粒子 5 AlGaAs 6 穴部 7 GaAs量子井戸箱 DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 AlGaAs layer 3 Silicon grid pattern 4 Ultrafine gold particles 5 AlGaAs 6 Hole 7 GaAs quantum well box

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の半導体材料上に金属超微粒子を2
次元的に規則正しく並べ、前記金属超微粒子間に第1の
半導体材料を選択成長させた後、前記金属超微粒子を除
去することによって形成される穴部に、前記第1の半導
体材料よりも禁制帯幅の小さな第2の半導体材料を埋め
込むことを特徴とする半導体量子井戸箱の製造方法。
1. A method in which two ultrafine metal particles are formed on a first semiconductor material.
After the first semiconductor material is selectively grown between the metal ultrafine particles, the holes formed by removing the metal ultrafine particles are more forbidden than the first semiconductor material. A method for manufacturing a semiconductor quantum well box, wherein a second semiconductor material having a small width is embedded.
JP19265591A 1991-04-03 1991-04-03 Manufacturing method of semiconductor quantum well box Expired - Lifetime JP2979752B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19265591A JP2979752B2 (en) 1991-04-03 1991-04-03 Manufacturing method of semiconductor quantum well box

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19265591A JP2979752B2 (en) 1991-04-03 1991-04-03 Manufacturing method of semiconductor quantum well box

Publications (2)

Publication Number Publication Date
JPH04306897A JPH04306897A (en) 1992-10-29
JP2979752B2 true JP2979752B2 (en) 1999-11-15

Family

ID=16294852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19265591A Expired - Lifetime JP2979752B2 (en) 1991-04-03 1991-04-03 Manufacturing method of semiconductor quantum well box

Country Status (1)

Country Link
JP (1) JP2979752B2 (en)

Also Published As

Publication number Publication date
JPH04306897A (en) 1992-10-29

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