JP2990773B2

JP2990773B2 - Selection circuit

Info

Publication number: JP2990773B2
Application number: JP2248239A
Authority: JP
Inventors: 進一平野
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1990-09-18
Filing date: 1990-09-18
Publication date: 1999-12-13
Anticipated expiration: 2014-12-13
Also published as: JPH04127615A

Description

【発明の詳細な説明】〔産業上の利用分野〕本発明は半導体集積回路に関し、特に選択回路に関す
る。Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, and more particularly to a selection circuit.

[Conventional technology]

従来、この種の選択回路は２種類の論理ゲートの出力
信号を選択信号でマルチプレクスしていた。Conventionally, this type of selection circuit multiplexes output signals of two types of logic gates with selection signals.

第３図は従来の選択回路の一例を示す接続図で、入力
信号B1,C1のNAND論理出力信号とNOR論理出力信号とを選
択信号A1でマルチプレクスした場合の接続回路図であ
る。第３図において、11〜17はｐ−MOSトランジスタ、1
8〜24はｎ−MOSトランジスタである。また、第４図はこ
の選択回路の真理値である。両図から明らかなように、
選択信号A1が０のときにはNAND論理出力信号が、かつ選
択信号A1が１のときにはNOR論理出力信号が選択され
る。FIG. 3 is a connection diagram showing an example of a conventional selection circuit, and is a connection circuit diagram in a case where a NAND logic output signal and a NOR logic output signal of input signals B1 and C1 are multiplexed by a selection signal A1. In FIG. 3, 11 to 17 are p-MOS transistors, 1
8 to 24 are n-MOS transistors. FIG. 4 shows the truth values of the selection circuit. As is clear from both figures,
When the selection signal A1 is 0, the NAND logic output signal is selected, and when the selection signal A1 is 1, the NOR logic output signal is selected.

[Problems to be solved by the invention]

上述した従来の選択回路は、２種類の論理ゲートの出
力信号を選択するためにマルチプレクサ回路が必要にな
るため、回路が大きくなるうえに、低速になるという欠
点がある。The above-described conventional selection circuit requires a multiplexer circuit to select the output signals of the two types of logic gates, and thus has the disadvantage that the circuit becomes large and the speed becomes low.

[Means for solving the problem]

本発明の選択回路は、電源をソースに入力し第一のゲ
ート入力をもつ第一のｐ−MOSトランジスタと、前記第
一のｐ−MOSトランジスタのドレインをソースに入力し
第二のゲート入力をもつ第二のｐ−MOSトランジスタ
と、電源をソースに入力し第三のゲート入力をもつ第三
のｐ−MOSトランジスタと、前記第三のｐ−MOSトランジ
スタのドレインをソースに入力し前記第二のｐ−MOSト
ランジスタとドレインを共有し前記第二のゲート入力を
もつ第四のｐ−MOSトランジスタと、前記第三のｐ−MOS
トランジスタのドレインをソースに入力し前記第四のｐ
−MOSトランジスタとドレインを共有し前記第一のゲー
ト入力をもつ第五のｐ−MOSトランジスタと、接地をソ
ースに入力し前記第三のゲート入力をもつ第六のｎ−MO
Sトランジスタと、前記第六のｎ−MOSトランジスタのド
レインをソースに入力し前記第二のゲート入力をもつ第
七のｎ−MOSトランジスタと、接地をソースに入力し前
記第一のゲート入力をもつ第八のｎ−MOSトランジスタ
と、前記第八のｎ−MOSトランジスタのドレインをソー
スに入力し前記第七のｎ−MOSトランジスタとドレイン
を共有し前記第二のゲート入力をもつ第九のｎ−MOSト
ランジスタと、前記第八のｎ−MOSトランジスタのドレ
インをソースに入力し前記第九のｎ−MOSトランジスタ
とドレインを共有し前記第三のゲート入力をもつ第十の
ｎ−MOSトランジスタとを備え、前記第五のｐ−MOSトラ
ンジスタと前記第十のｎ−MOSトランジスタとの共有の
ドレインを出力する構成である。A selection circuit according to the present invention comprises a first p-MOS transistor having a first gate input with a power source input to a source, and a drain having the first p-MOS transistor having a source input to a second gate input. A second p-MOS transistor, a third p-MOS transistor having a power source input to the source and a third gate input, and a second p-MOS transistor having the drain input to the source A fourth p-MOS transistor sharing the drain with the p-MOS transistor of the third p-MOS transistor and having the second gate input;
The drain of the transistor is input to the source and the fourth p
A fifth p-MOS transistor sharing the drain with the MOS transistor and having the first gate input, and a sixth n-MO transistor having ground input to the source and having the third gate input.
An S transistor, a seventh n-MOS transistor having a source connected to the drain of the sixth n-MOS transistor and having the second gate input, and having the first gate input having a ground input to the source An eighth n-MOS transistor, and a ninth n-MOS transistor having a drain input to the source of the eighth n-MOS transistor, a drain shared with the seventh n-MOS transistor, and having the second gate input. A MOS transistor, and a tenth n-MOS transistor having a drain input to the source of the eighth n-MOS transistor, a drain shared with the ninth n-MOS transistor, and having the third gate input. , And a common drain of the fifth p-MOS transistor and the tenth n-MOS transistor.

また、前記第十のｎ−MOSトランジスタが前記第三の
ゲート入力に代替えして前記第一のゲート入力をもつ構
成であってもよい。Further, the tenth n-MOS transistor may have the first gate input instead of the third gate input.

〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

本発明の一実施例を示す第１図を参照すると、選択信
号Ａにより入力信号B,CのNAND論理かNOR論理かを選択出
力する回路に実施した場合であり、Ｃを第一のゲート入
力に、Ａを第二のゲート入力に、Ｂを第三のゲート入力
に、１〜５のｐ−MOSトランジスタをそぞれ第一〜第五
のｐ−MOSトランジスタに、６〜10のｎ−MOSトランジス
タをそれぞれ第六〜第十のｎ−MOSトランジスタにした
場合である。この選択回路の真理値を第２図に示す。Referring to FIG. 1 showing an embodiment of the present invention, this is a case where a selection signal A is applied to a circuit for selectively outputting NAND logic or NOR logic of input signals B and C, and C is a first gate input. A is set to the second gate input, B is set to the third gate input, 1 to 5 p-MOS transistors are respectively set to the first to fifth p-MOS transistors, and 6 to 10 n-MOS transistors are set. This is a case where the MOS transistors are respectively sixth to tenth n-MOS transistors. FIG. 2 shows the truth values of this selection circuit.

動作について説明すると、Ａ＝０の時、Ｂ＝Ｃ＝０な
らば、１→２または３→４（、→５）のｐ−MOSトラン
ジスタを通して出力Ｄは１に、Ｂ＝０、Ｃ＝１ならば、
３→４のｐ−MOSトランジスタを通して出力Ｄは１に、
Ｂ＝１、Ｃ＝０ならば、１→２（→４→５）のｐ−MOS
トランジスタを通して出力Ｄは１に、Ｂ＝Ｃ＝１なら
ば、８→10のｎ−MOSトランジスタを通して出力Ｄは０
となり、Ａ＝０の時、出力ＤはNAND論理となる。The operation will be described. When A = 0, if B = C = 0, the output D becomes 1 through a 1 → 2 or 3 → 4 (→ 5) p-MOS transistor, and B = 0, C = 1 Then
The output D becomes 1 through the 3 → 4 p-MOS transistor,
If B = 1 and C = 0, 1 → 2 (→ 4 → 5) p-MOS
The output D becomes 1 through the transistor, and if B = C = 1, the output D becomes 0 through the 8 → 10 n-MOS transistor.
When A = 0, the output D becomes NAND logic.

また、Ａ＝１の時、Ｂ＝Ｃ＝０ならば、３→５のｐ−
MOSトランジスタを通して出力Ｄは１に、Ｂ＝０、Ｃ＝
１ならば、８→９のｎ−MOSトランジスタを通して出力
Ｄは０に、Ｂ＝１、Ｃ＝０ならば、６→７（→９→10）
のｎ−MOSトランジスタを通して出力Ｄは０に、Ｂ＝Ｃ
＝１ならば、６→７または８→９（、→10）のｎ−MOS
トランジスタを通し出力Ｄは０となり、Ａ＝１の時、出
力ＤはNOR論理となる。Also, if A = 1 and B = C = 0, p → 3 → 5
The output D becomes 1 through the MOS transistor, B = 0, C =
If 1, the output D goes to 0 through the 8 → 9 n-MOS transistor, and if B = 1 and C = 0, 6 → 7 (→ 9 → 10)
The output D becomes 0 through the n-MOS transistor of B = C
If = 1, 6 → 7 or 8 → 9 (, → 10) n-MOS
The output D becomes 0 through the transistor, and when A = 1, the output D becomes NOR logic.

上記実施例においては、第十のｎ−MOSトランジスタ1
0のゲートに第三のゲート入力を接続した場合について
述べたが、代わりに第一のゲート入力を接続しても同様
に実施できる。この場合、Ａ＝０の時の動作は全く同一
であり、出力ＤはNAND論理となる。一方、Ａ＝１の時、
Ｂ＝Ｃ＝０ならば、３→５のｐ−MOSトランジスタを通
して出力Ｄは１に、Ｂ＝０、Ｃ＝１ならば、６→７（→
９→10）のｎ−MOSトランジスタを通して出力Ｄは０
に、Ｂ＝１、Ｃ＝０ならば、８→９のｎ−MOSトランジ
スタを通して出力Ｄは０に、Ｂ＝Ｃ＝１ならば、６→７
または８→９（、→10）のｎ−MOSトランジスタを通し
て出力Ｄは０となり、Ａ＝１の時、出力ＤはNOR論理と
なる。In the above embodiment, the tenth n-MOS transistor 1
Although the case where the third gate input is connected to the zero gate has been described, the same can be implemented by connecting the first gate input instead. In this case, the operation when A = 0 is exactly the same, and the output D becomes NAND logic. On the other hand, when A = 1,
If B = C = 0, the output D becomes 1 through the 3 → 5 p-MOS transistor, and if B = 0, C = 1, 6 → 7 (→
9 → 10) The output D is 0 through the n-MOS transistor.
When B = 1 and C = 0, the output D becomes 0 through the 8 → 9 n-MOS transistor, and when B = C = 1, 6 → 7
Alternatively, the output D becomes 0 through an n-MOS transistor of 8 → 9 (→ 10), and when A = 1, the output D becomes NOR logic.

〔The invention's effect〕

以上説明したように、本発明によれば、非論理ゲート
構成とすることにより、より少ない回路構成素子数で高
速な選択回路を構成できる。As described above, according to the present invention, a high-speed selection circuit can be configured with a smaller number of circuit components by adopting a non-logic gate configuration.

このような本発明の選択回路は、UP−DOWNカウンタ回
路のキャリー部に利用すると効果がある。Such a selection circuit of the present invention is effective when used in a carry section of an UP-DOWN counter circuit.

[Brief description of the drawings]

第１図は本発明の選択回路の一実施例を示す回路図、第
２図は第１図の選択回路の真理値を表わした図、第３図
及び第４図は従来の選択回路を示す図である。１〜５……ｐ−MOSトランジスタ、６〜10……ｎ−MOSト
ランジスタ。FIG. 1 is a circuit diagram showing an embodiment of the selection circuit of the present invention, FIG. 2 is a diagram showing truth values of the selection circuit of FIG. 1, and FIGS. 3 and 4 show a conventional selection circuit. FIG. 1-5 ... p-MOS transistor, 6-10 ... n-MOS transistor.

Claims

(57) [Claims]

A first p-MOS transistor having a first gate input and a power input to a source;
A second p-MOS transistor having a drain input to the source and having a second gate input; a third p-MOS transistor having power input to the source and having a third gate input; A drain of the p-MOS transistor is input to a source, and a fourth p-type transistor having a drain shared with the second p-MOS transistor and having the second gate input
A MOS transistor, a fifth p-MOS transistor having a drain input to the source of the third p-MOS transistor as a source, sharing a drain with the fourth p-MOS transistor, and having the first gate input; A sixth n-MOS transistor having ground input to the source and having the third gate input, and a seventh n-MOS transistor having the source connected to the drain of the sixth n-MOS transistor and having the second gate input. −MO
An S-transistor, an eighth n-MOS transistor having a ground input to the source and having the first gate input, and a seventh n-MOS transistor having the drain of the eighth n-MOS transistor input to the source A ninth n-MOS transistor sharing the drain with the second gate input, and the drain of the eighth n-MOS transistor being input to the source and sharing the drain with the ninth n-MOS transistor. A tenth n-MOS transistor having the third gate input, and outputting a common drain of the fifth p-MOS transistor and the tenth n-MOS transistor. circuit.

2. The selection circuit according to claim 1, wherein said tenth n-MOS transistor has said first gate input instead of said third gate input.