JP2991164B2 - Multi-layer wiring evaluation structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring evaluation structure for evaluating wiring formed on a semiconductor device.
More specifically, the present invention relates to a multilayer wiring evaluation structure for performing an electromigration test of the wiring having a via hole.

[0002]

2. Description of the Related Art One of the causes of defects in semiconductor devices such as LSIs is the increase in resistance or disconnection of wiring due to electromigration (hereinafter referred to as "EM"). The EM lifetime of a semiconductor device is generally calculated by the Bragg formula t50 = AJ- ⁿ * exp (kT / Ea) from the lifetime obtained by performing an accelerated test (high current density, high temperature) and obtaining the test result. is expected. Here, t50 is the average EM life, A
Is a structure dependent constant, J is a current density, n is a current density dependent coefficient (usually n = 2), and k is a Boltzmann constant (8.6173)
8 × 10 ⁻⁵ ), T is the absolute temperature [k], and Ea is the activation energy [ev]. Note that the above-described accelerated test is performed not using an actual semiconductor device but using a multilayer wiring evaluation structure dedicated to the test.

Here, a conventional multilayer wiring evaluation structure will be described with reference to FIGS. 7 and 8. FIG. FIG. 7 shows “Pro
c. IEEE 1991 Int. Conferenc
e on Microelectronics Tes
t Structures Vol. 4, No. 1, M
1991, pp. 251 to 256, is a cross-sectional view showing a conventional multilayer wiring evaluation structure. FIG. 8 shows a lower wiring, an upper wiring, and a via hole of the multilayer wiring evaluation structure shown in FIG. It is a perspective plan view shown. As shown in FIG. 7, in a conventional multilayer wiring evaluation structure 101, a lower conductor layer 103 provided on an upper surface of a lower interlayer insulating film 102 is provided.
Are formed with a plurality of lower wirings 104. Further, an upper interlayer insulating film 105 is laminated on the upper surface of the lower conductor layer 103, and a plurality of upper wirings 107 are formed on the upper conductor layer 106 provided on the upper surface of the upper interlayer insulating film 105. Note that the lower wiring 104 and the upper wiring 107 are A
1 alloy.

Further, as shown in FIGS. 7 and 8, an end 104a of each lower layer wiring 104 and an end 107a of each upper layer wiring 107 are connected to a via hole 10 made of an Al alloy.
8 are connected. Thus, in the multilayer wiring evaluation structure 101, a chain wiring in which the plurality of lower wirings 104 and the plurality of upper wirings 107 are connected in series by the via holes 108 is formed.

Since the via hole 108 has a high aspect ratio in accordance with the high integration of the LSI, a W plug structure in which W (tungsten) is buried inside the via hole 108 is formed. When a plurality of chain wirings are provided in parallel, in order to reduce the wiring pitch between the chain wirings, the via hole 108 of the multilayer wiring evaluation structure 101 is provided with a lower wiring 104 which is a connection portion with the via hole 108. End 104a or upper layer wiring 10
A borderless via in which the “Al thickening” at the end portion 107 a of the No. 7 is eliminated and the Al margin is reduced is applied.

FIG. 9 is a cross-sectional view showing, on an enlarged scale, a part of the multilayer wiring evaluation structure shown in FIG. As shown in FIG.
In the multilayer wiring evaluation structure 101, an EM test is performed by passing a current through a chain wiring composed of the upper wiring 104, the lower wiring 107, and the via hole.

In the multilayer wiring evaluation structure 101 as described above, the W buried in the via hole 108 prevents the flow of Al atoms by EM. For this reason, when the current continues to flow, as shown in FIG.
9, the multilayer wiring evaluation structure 101 becomes defective due to an increase in resistance or disconnection. In the multilayer wiring evaluation structure 101 in which a dissimilar metal such as the W plug structure described above exists in the Al alloy wiring (that is, the via hole 108) connecting the lower wiring 104 and the upper wiring 107, the lower wiring 104 and the upper wiring 107 themselves are not used. A defect at the connection between each of the wirings 104 and 107 and the via hole 108 occurs earlier than a defect. Therefore, the EM life of the multilayer wiring evaluation structure 101 depends on the time until a failure occurs in the connection portion.

Each wiring 104, 107 and via hole 108
Wiring evaluation structure 10 due to a defect occurring at the connection portion with
It is known that the EM lifetime of 1 is affected by the Al margin provided in the connection portion. Multilayer wiring evaluation structure 1
When an electric current is applied to 01, Al atoms are moved, and eventually an Al elimination portion 109 (see FIG. 9) is generated at each end 104a, 107a. However, the aforementioned Al margin is
It functions as an Al atom supply source for supplementing the Al atoms in places where the atoms have been moved and disappeared. Therefore, the EM life of the multilayer wiring evaluation structure 101 increases as the Al margin increases.

[0009] In addition, a defect that occurs at a connection portion between each of the wirings 104 and 107 and the via hole 108 is caused by a defect in each of the wirings 104 and 1.
Since it is due to the movement of Al atoms at 07, the EM life of the wiring structure is also affected by the wiring width of each of the wirings 104 and 107 connected to the via hole 108. Therefore, the multilayer wiring evaluation structure 101 used for the EM test is:
The wiring width of each wiring 104, 107, and each wiring 104,
It is desirable that both the Al margins at the connection between the via 107 and the via hole 108 are formed to be equal to the wiring structure in an actual semiconductor device.

[0010]

In the above-described multilayer wiring evaluation structure, the wiring width and the film thickness of each lower wiring and each upper wiring are formed to be equal, and each lower wiring and each upper wiring is connected to the via hole. The Al margin in the connection portion is provided equally in all the connection portions. for that reason,
When an EM test is performed using such a multilayer wiring evaluation structure, it is immediately determined whether the location of a defect due to the disappearance of Al is a via hole connection part on the upper wiring side or a via hole connection part on the lower wiring side. Therefore, it is necessary to process the tested multilayer wiring evaluation structure and observe its cross section.

As a method of inspecting the location where the defect has occurred, there is an inspection method as disclosed in Japanese Patent Application Laid-Open No. 4-290242. That is, by observing the secondary electron images of the upper wiring and the lower wiring, a defective via hole due to a disconnection or the like caused by the disappearance of Al can be found. It can be determined whether the wiring side or the lower wiring side. However, in this case, it is necessary to remove the insulating film formed on the wiring and the like, so that many steps are required for the inspection. Also, W
In the case of via holes in which high-melting-point metal is buried, most of the causes of defective via holes are caused by high resistance and not disconnection. Can not.

Accordingly, the present invention tests by distinguishing between the EM life at the connection between the wiring formed in the lower conductor layer and the via hole and the EM life at the connection between the wiring formed in the upper conductor layer and the via hole. It is an object of the present invention to provide a multi-layer wiring evaluation structure that can be used.

[0013]

In order to achieve the above object, a multilayer wiring evaluation structure according to the present invention is characterized in that a lower conductor layer having a plurality of wirings and an upper conductor layer having a plurality of wirings are formed of an insulating layer. A multilayer wiring evaluation structure having a chain wiring in which the wiring of the lower conductor layer and the wiring of the upper conductor layer are alternately connected in series via a plurality of via holes provided in the insulating layer. When the plurality of via holes are alternately arranged as a first via hole and a second via hole in the order of arrangement in the chain wiring, a connection part of the wiring with the first via hole is formed from the connection part by electromigration. A margin portion including the same metal as the metal to be lost and having a size larger than the via hole is provided, and the second via hole of the wiring is provided.
The margin part is not provided in the connection part with the tool
It is characterized by the following.

In the multilayer wiring evaluation structure configured as described above, the connection portion between the via hole having no margin portion and each wiring is closer to the connection portion between the via hole provided with the margin portion and each wiring. However, the EM life is short. Therefore, depending on the direction of the current flowing through the multilayer wiring evaluation structure, a connection portion between the wiring formed in the lower conductor layer and a via hole having no margin portion or a wiring and a margin portion formed in the upper conductor layer is provided. An EM test is performed on one of the connection portions with the unconnected via holes.

Further, the multilayer wiring evaluation structure of the present invention
The lower conductor layer on which the wiring is formed and a plurality of wirings are formed.
And the upper conductor layer are laminated via an insulating layer,
The wiring of the body layer and the wiring of the upper conductor layer are provided on the insulating layer.
Are connected alternately in series via multiple via holes
In a multilayer wiring evaluation structure having a chain wiring
The plurality of via holes are arranged in the order of arrangement in the chain wiring.
Alternately, the first via hole and the second via hole
A connection portion between the wiring and the first via hole,
Erased from the connection by electromigration
Contains the same metal as the lost metal and is larger than the via hole
A large margin part is provided, and the wiring
The connection portion with the second via hole has an electro-
Metal that disappears from the connection due to migration
The same metal and smaller than the margin
A housing portion is provided. This
Since the EM life of the connection between each via and the via hole provided with the smaller margin portion is shorter, the EM test of the multilayer wiring evaluation structure depends on the direction of the current flowing through the multilayer wiring evaluation structure. Either the connection between the wiring formed in the lower conductor layer and the via hole provided with the smaller margin portion, or the connection between the wiring formed in the upper conductor layer and the via hole provided with the smaller margin portion An EM test is performed on one of them.

Further, the margin portion may be provided around the connection portion.

Further, the margin portion is the chain
Extend the chain wiring so as not to exceed the wiring width of the wiring.
When a plurality of chain wirings are provided in parallel, the wiring pitch between the chain wirings and the wiring pitch of the wiring structure in an actual semiconductor device are matched.

Further, a structure may be employed in which tungsten is buried inside the via hole.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a schematic configuration of a first embodiment of a multilayer wiring evaluation structure of the present invention.
FIG. 2 is a perspective plan view showing a lower wiring, an upper wiring, and a via hole of the multilayer wiring evaluation structure shown in FIG.

As shown in FIG. 1, in the multilayer wiring evaluation structure 1, the lower conductor layer 3 provided on the upper surface of the lower interlayer insulating film 2 is formed.
Are formed with a plurality of lower wirings 4. Further, an upper interlayer insulating film 5 is laminated on the upper surface of the lower conductor layer 3, and a plurality of upper wirings 7 are formed on the upper conductor layer 6 provided on the upper surface of the upper interlayer insulating film 5.

The end 4a of each lower wiring 4 and the end 7a of each upper wiring 7 are connected by a first via hole 8a, and the end 4b of each lower wiring 4 and the end 7b of each upper wiring 7 are connected.
b is connected by the second via hole 8b.
Thereby, in the multilayer wiring evaluation structure 1, the plurality of lower wirings 4 and the plurality of upper wirings 7 are connected to the plurality of via holes 8a, 8b.
Form a chain wiring connected in series.

As shown in FIG. 1 and FIG.
In the first via hole 8a connecting the end 4a of the upper layer wiring 7 and the end 7a of the upper wiring 7, the via hole 8a and each end 4a, 7
An Al margin 9 of 0.6 μm is provided around four sides of the connection portion with a. On the other hand, a second via hole 8 connecting end 4b of lower wiring 4 and end 7b of upper wiring 7 is formed.
b is Al at the connection between the wirings 4 and 7 and the via hole 8b.
This is a borderless via with no margin. That is, in the multilayer wiring evaluation structure 1 of the present embodiment, the via holes 8a provided with the Al margin 9 and the via holes 8b provided with no Al margin are alternately arranged.

In the multilayer wiring evaluation structure 1 of the present embodiment, the wiring width of the lower wiring 4 and the upper wiring 7 is 0.4 μm.
m, and the outer diameter of the via holes 8a, 8b is formed to be 0.4 μm.

FIG. 3 is a sectional view showing a detailed configuration of the multilayer wiring evaluation structure shown in FIG.

As shown in FIG. 3, the lower wiring 4 formed on the upper surface of the lower interlayer insulating film 2 includes a first TiN film 10 having a thickness of 50 nm and a first AN film 10 having a thickness of 400 to 500 nm.
lCu film 11 and first Ti film 12 having a thickness of 20 nm
And a second TiN film 13 having a thickness of 50 nm.

Further, the upper interlayer insulating film 5 has a depth of 80
Via holes 8 a and 8 b having a thickness of 0 nm and a diameter of 0.4 μm are formed so as to reach the lower wiring 4. Beer hole 8
a and 8b have a thickness of 3 on the inner surfaces of the via holes 8a and 8b.
A third TiN film 14 having a thickness of 0 to 50 nm is formed, and W (tungsten) is buried in the via holes 8a and 8b, so that a W plug structure 15 is formed. Note that W is buried in the via holes 8a and 8b by CVD (Chemica) on the upper surface of the upper interlayer insulating film 5.
1 Vapor Deposition method
Is grown, and the W grown in portions other than the via holes 8a and 8b is removed by CMP (Chemical Mecha).
The removal is carried out by a chemical polishing method.

The upper wiring 7 formed on the upper surface of the upper interlayer insulating film 5 includes a fourth TiN film 16 having a thickness of 50 nm and a thickness of 400 to 50, similarly to the lower wiring 4 described above.
A second AlCu film 17 having a thickness of 0 nm, a second Ti film 18 having a thickness of 20 nm, and a fifth TiN film 1 having a thickness of 50 nm
9.

It should be noted that the first in which an Al margin is provided.
As described above, the via holes 8a and the second via holes 8b having no Al margin are alternately arranged.

As described with reference to the conventional multilayer wiring evaluation structure, in the present multilayer wiring evaluation structure 1, the via holes 8a,
Since the flow of Al atoms due to EM is prevented by the W embedded in the multilayer wiring structure 8b, when the current continues to flow through the multilayer wiring evaluation structure 1, the end of each of the wirings 4, 7 where the current flows into the W plug structure 14. In this case, Al gradually disappears, and eventually an Al disappearing portion occurs in each of the wirings 4 and 7.

Therefore, the above-described multilayer wiring evaluation structure 1
In the configuration described above, when a current flows in the direction A shown in FIG. 1, Al disappears at the end 7b of the upper layer wiring 7 and the end 4a of the lower layer wiring 4. Here, as shown in FIG. 1, an Al margin is provided at a connection portion between the end 4a of the lower wiring 4 and the first via hole 8a, whereas the end 7a of the upper wiring 7 is provided.
No Al margin is provided at the connection between the second via hole 8b and the second via hole 8b. Therefore, the end 4a of the lower wiring 4
In this case, the disappeared Al is supplemented by the Al margin, whereas the disappeared Al is not supplemented at the end 7b of the upper wiring 7. As a result, between the end 7b of the upper wiring 7 and the end 4a of the lower wiring 4, the end 7b of the upper wiring 7 is closer to the EM.
Since the life is shortened, when a current flows in the A direction,
The EM life at the connection between the via hole 8b where the Al margin is not provided and the upper wiring 7 is tested.

When a current is passed in the direction B shown in FIG.
A at the end 7a of the upper wiring 7 and the end 4b of the lower wiring 4
1 loss occurs. In this case, for the same reason as described above, the end 4b of the lower wiring 4 has a shorter EM life than the end 7a of the upper wiring 7, so that when a current is supplied in the B direction, Then, the EM life at the connection between the via hole 8b having no Al margin and the lower wiring 4 is tested.

FIG. 4 shows a case where a current is applied to the multilayer wiring evaluation structure shown in FIG.
FIG. 9 is an evaluation result diagram showing an EM test result when a current flows from a direction.

From the test results shown in FIG. 4, in the multilayer wiring evaluation structure 1 of the present embodiment, when the current is applied to the multilayer wiring evaluation structure 1 from the direction A shown in FIG. It can be seen that the EM life is shorter than when a current is applied to the structure 1. Therefore, it can be said that the EM life of the multilayer wiring evaluation structure 1 depends on the EM life at the end 7 b of the upper wiring 7.

As described above, the multilayer wiring evaluation structure 1 is formed by connecting the first via hole 8a having the Al margin at the connection portion with each of the wirings 4 and 7 and the Al via at the connection portion with each of the wirings 4 and 7.
With a configuration in which the second via holes 8b having no margin are alternately arranged, the connection portion between the first via hole 8a and the lower wiring 4 or the connection portion depending on the direction of the current flowing through the wiring structure 1 An EM test can be performed on one of the connection portions between the second via hole 8a and the upper wiring 7.

In this embodiment, a via hole having an Al margin at a connection portion with each wiring and a via hole having no Al margin at a connection portion with each wiring are alternately arranged. Although shown, a via hole provided with an Al margin and a via hole provided with an Al margin smaller than the Al margin may be alternately arranged.

As a result, the EM life of the via hole having a smaller Al margin is shorter than that of the via hole, and therefore, one of the connection portion between the via hole and the lower wiring or the connection portion between the via hole and the upper wiring. An EM test can be performed for

(Second Embodiment) FIG. 5 is a sectional view showing a second embodiment of the multilayer wiring evaluation structure of the present invention, and FIG.
FIG. 3 is a perspective plan view showing a lower wiring, an upper wiring, and a via hole of the multilayer wiring evaluation structure shown in FIG. However, the lower interlayer insulating film 22, the lower conductive layer 23, the lower wiring 24, the upper interlayer insulating film 25, the upper conductive layer 26, the upper wiring 27, and the via holes 28a and 28 shown in FIG.
The respective configurations such as b, Al margin 29, and W plug structure (not shown) are the same as those of the multilayer wiring evaluation structure 1 shown in FIG.
A configuration different from the above will be described.

As shown in FIGS. 5 and 6, in the first via hole 28a, the Al margin 29 at the connection portion with each wiring 24, 27 is provided only in the direction in which each wiring 24, 27 is extended. I have. In the main line evaluation structure 21, the Al margin 29 is provided to be 0.6 μm.

The multilayer wiring evaluation structure 2 configured as described above
1 as well as the multilayer wiring evaluation structure 1 of the first embodiment, the second direction depends on the direction of the current flowing through the wiring structure 21.
An EM test can be performed on either the connection between the via hole 28b and the lower wiring 24 or the connection between the second via hole 28b and the upper wiring 27.

Further, the multilayer wiring evaluation structure 2 of the present embodiment
In FIG. 1, as shown in FIG. 6, the Al margin 29 provided in the first via hole 28a has a size not exceeding the wiring width of the chain wiring formed by the wirings 24 and 27 and the via holes 28a and 28b. Is provided. Therefore, when a plurality of chain wirings are provided in parallel,
The wiring pitch between the chain wirings can be matched with the wiring pitch of the wiring structure of the actual semiconductor device. Therefore, the multilayer wiring evaluation structure 21 used for the test is used.
Can be configured to be closer to the wiring structure of an actual semiconductor device, so that the EM life of the wiring structure of an actual semiconductor device can be more accurately predicted.

[0042]

As described above, in the multilayer wiring evaluation structure of the present invention, the first via holes and the second via holes are alternately arranged, and the margin portion is provided at the connection portion between the wiring and the first via hole. A second via hole in the wiring
Since no margin is provided at the connection portion between the wiring and the second via hole, the EM life at the connection portion between the wiring formed in the lower conductor layer and the second via hole, and the connection between the wiring formed on the upper conductor layer and the second via hole are reduced. The test can be performed while distinguishing from the EM lifetime at the connection portion with the EM.

Further, a margin portion is arranged in the chain wiring.
By providing a width not exceeding the line width in the direction in which the chain wiring extends , the multilayer wiring evaluation structure can be configured to be closer to the wiring structure of an actual semiconductor device. EM lifetime of the wiring structure can be more accurately predicted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a schematic configuration of a first embodiment of a multilayer wiring evaluation structure of the present invention.

FIG. 2 is a perspective plan view showing a lower wiring, an upper wiring, and a via hole of the multilayer wiring evaluation structure shown in FIG. 1;

FIG. 3 is a cross-sectional view showing a detailed configuration of the multilayer wiring evaluation structure shown in FIG.

FIG. 4 is an evaluation result diagram showing an EM test result of the multilayer wiring evaluation structure shown in FIG. 3 and the like;

FIG. 5 is a sectional view showing a second embodiment of the multilayer wiring evaluation structure of the present invention.

6 is a perspective plan view showing a lower wiring, an upper wiring, and a via hole of the multilayer wiring evaluation structure shown in FIG. 5;

FIG. 7 is a cross-sectional view showing a conventional multilayer wiring evaluation structure.

8 is a perspective plan view showing a lower wiring, an upper wiring, and a via hole of the multilayer wiring evaluation structure shown in FIG. 7;

9 is a cross-sectional view showing a part of the multilayer wiring evaluation structure shown in FIG. 7 in an enlarged manner.

DESCRIPTION OF SYMBOLS 1,21 Multilayer wiring evaluation structure 2,22 Lower interlayer insulating film 3,23 Lower conductor layer 4,24 Lower wiring 4a, 4b, 7a, 7b, 24a, 24b, 27a, 2
7b End 5,25 Upper interlayer insulating film 6,26 Upper conductor layer 7,27 Upper wiring 8a, 28a First via hole 8b, 28b Second via hole 9,29 Al margin 10 First TiN film 11 First AlCu film 12 First Ti film 13 Second TiN film 14 Third TiN film 15 W plug structure 16 Fourth TiN film 1 17 Second AlCu film 18 Second Ti film 19 Fifth TiN film

Claims (5)

(57) [Claims] A lower conductor layer on which a plurality of wirings are formed and an upper conductor layer on which a plurality of wirings are formed are laminated via an insulating layer, and a wiring of the lower conductor layer and a wiring of the upper conductor layer are formed. In a multilayer wiring evaluation structure having a chain wiring alternately connected in series via a plurality of via holes provided in the insulating layer, the first via holes alternately arrange the plurality of via holes in the arrangement order in the chain wiring, When a second via hole is formed, a connection portion between the wiring and the first via hole includes:
A margin portion containing the same metal as the metal lost from the connection portion by electromigration and having a size larger than the via hole is provided, and
The margin portion is provided at a connection portion with the second via hole.
A multilayer wiring evaluation structure characterized by not being provided . And a lower conductor layer having a plurality of wires formed thereon.
The upper conductor layer with the number of wirings
A wiring of the lower conductor layer and a wiring of the upper conductor layer
Through a plurality of via holes provided in the insulating layer
Multi-layer wiring with chain wiring alternately connected in series
In the evaluation structure, the plurality of via holes are arranged in the order of arrangement in the chain wiring.
Alternately, the first via hole and the second via hole
A connection portion between the wiring and the first via hole,
Erased from the connection by electromigration
Contains the same metal as the lost metal and is larger than the via hole
A margin portion having a large size is provided, and a connection portion between the wiring and the second via hole includes the same metal as the metal lost from the connection portion by electromigration and has a size larger than the margin portion. Multilayer wiring characterized by having a small margin area
Valence structure. 3. The multilayer wiring evaluation structure according to claim 1, wherein the margin portion is provided around the connection portion. 4. The arrangement of the chain wiring according to claim 4, wherein
The multilayer wiring evaluation structure according to claim 3, wherein the multilayer wiring evaluation structure is provided with a width not exceeding a line width in a direction in which the chain wiring extends . 5. The multilayer wiring evaluation structure according to claim 1, wherein tungsten is buried inside said via hole.