JP2998657B2 - Driver circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a driver circuit, and more particularly to a driver circuit for independently transmitting two or more signals.

[0002]

2. Description of the Related Art Generally, in order to transmit a plurality of signals, a plurality of driver circuits respectively corresponding to the plurality of signals are provided.
These driver circuits operate independently of each other. That is, as shown in FIG. 4, (n + 1) lines (n>
0) of the input signal 121 is (n + 1) driver circuits 5
-0 to 5-n buffer circuits 51-0 to 51-n
(Buffer circuits 51-1 to 51-n are not shown), and (n + 1) buffer circuits 51-0 to 51-n
Is output as the driver output signal 122 as it is.

[0003] (n + 1) buffer circuits 51-0 to 5-5
1-n operate independently of each other irrespective of the value of the input signal 121, and each of the (n + 1) driver circuits 5-0 to 5-n operates while the entire driver circuit system is activated. Buffer circuits 51-0 to 51-n are always activated.

As described above, all the buffer circuits 51-
A buffer circuit included in a clock signal generation circuit that generates signals having a phase relationship opposite to each other with respect to one input signal, in order to solve the case where 0 to 51-n are activated. Is provided with another buffer circuit, and when a phase difference between the waveforms of the output signals output from the clock signal generation circuit and having a phase relationship opposite to each other is detected, the buffer There is also a method of outputting.

That is, as shown in FIG. 5, the driver circuit 6 includes a clock signal generation circuit 61 for generating a clock signal based on a clock input signal 131, a buffer circuit 62 including inverters 62a to 62d, and a NOR ( N
OR) circuits 63 and 68, inverters 64 to 67, a latch circuit 69, and a clock output signal 1
And a multiplexer 70 that outputs the signal 32. This technology is disclosed in Japanese Patent Application Laid-Open No. 3-167616.
No. 6,009,045.

[0006]

In the conventional driver circuit described above, when a plurality of types of signals are handled at the same time, a sufficient driving capability is required in each of the driver circuits mainly because the signal state transitions. It is time. At other times, that is, when the state of the signal does not fluctuate for a certain period, there is no problem even if the driving capability is relatively low.

However, in the conventional driver circuit, each buffer circuit corresponding to all input signals operates independently of each other. Therefore, in order to maintain each driver output signal at a normal value, all the buffer circuits are controlled. Since it is necessary to always supply power and maintain normal operation, when the driver circuit system is in the active state, the buffer circuit is always in the active state, and constant power is always consumed regardless of the state of the input signal. Would.

In the technique disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-167616, a buffer circuit having a high drive capability is used to correct a phase shift due to rounding of the waveforms of two buffer output signals having opposite phases. Since it is provided separately from a normal buffer circuit included in the circuit, the circuit configuration becomes redundant.

In addition, the above technique dynamically controls the switching of the driver circuit only when a difference between the output signals of two buffer circuits included in the clock signal generation circuit that outputs the normal phase and the negative phase is detected. If no difference is detected between the waveforms of the two output signals at the same time, for example, it may be impossible to expect a sufficient drive capability.

A technique similar to the technique described in the above-mentioned Japanese Patent Application Laid-Open No. 3-167616 is disclosed in Japanese Patent Application Laid-Open No. 5-167616.
There are techniques disclosed in JP-A-347566 and JP-A-4-270978.

The technique disclosed in Japanese Patent Application Laid-Open No. Hei 5-347566 has a structure in which when a plurality of signals input to a multiplexer are switched, their outputs are temporarily switched to a separately provided reference voltage having a fixed potential. ing. Therefore, a reference voltage having a fixed potential must be separately provided. In addition, since the above technique aims at suppressing the disturbance of the waveform of the output signal, it does not contribute to the reduction of the power consumption of the circuit.

Further, the technique disclosed in Japanese Patent Application Laid-Open No. Hei 4-270978 is a technique for responding to a plurality of input signals with one comparator. It aims to lower prices. for that reason,
It is difficult to apply this technique to a circuit that obtains a plurality of output signals from a plurality of input signals.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to prevent unnecessary constant power consumption for keeping the buffer circuit active at all times when the driver system is active. It is to provide a circuit.

[0014]

Driver circuit according to the invention To achieve the above object, according to a driver circuit comprising a plurality of output circuits for each independently transmitting a plurality of digital signals, before
At least one of the plurality of digital signals is a reference
The reference input signal set as
Outputs other than the output circuit that receives the reference input signal
The above-mentioned base is determined according to the correlation with the digital signal to each of the power circuits.
Means for activating the output circuit each other than the output circuit for receiving the reference input signal independently, the reference input signal and the reference
To each output circuit other than the output circuit that receives the input signal
The reference input signal is input according to the correlation with the digital signal.
Means for independently deactivating each output circuit other than the output circuit serving as the output and outputting an output signal of another output circuit from the output circuit.

Another driver circuit according to the present invention is a driver circuit including a plurality of output circuits for independently transmitting a plurality of digital signals, wherein at least one of the plurality of digital signals is used as a reference. A comparison means for comparing the set reference input signal with an input signal to the own circuit, and when a power supply to the own circuit is suppressed when a match is detected by the comparison means, and when a mismatch is detected by the comparison means, means for returning the power supply to the self-circuit, mismatch the output signal of <br/> output circuit for receiving the reference input signal when a match is detected by said comparison means output Toshikatsu the comparing means of the self circuit among the plurality of output circuits and switching means for outputting an input signal as to its own circuit when but detected
And a said reference input signal to the output circuit each other than the output circuit for receiving.

That is, the driver circuit of the present invention uses at least one input signal of a plurality of input signals as a reference input signal in order to reduce the power consumption of the entire driver circuit transmitting two or more independent signals, An input signal to each buffer circuit is compared with its reference input signal, and a signal for controlling power supply to the buffer circuit in the driver circuit and a signal for controlling connection switching means of the driver output signal are generated from the comparison result. There is a means to do.

That is, the input signal to the buffer circuit is compared with the reference input signal, and when they match, the power supply to the buffer circuit is stopped or suppressed, and the power consumption is suppressed. At the same time, the buffer circuit corresponding to the reference input signal is also used as a substitute circuit for the corresponding buffer circuit, and this is connected to the driver output signal of the corresponding driver circuit by the driver output switching means, so that the normal driver circuit can be used. Operation is guaranteed.

On the other hand, when the state changes from this state to a state where the reference input signal and the respective input signals do not match, the corresponding buffer circuit is immediately activated, and the driver changes before the signal state transition is transmitted to the buffer circuit. By connecting the buffer output signal to the driver output signal of the corresponding driver circuit by the output switching means, it is ensured that the state transition of the signal can be dealt with in a state where the sufficient drive capability has been recovered.

Therefore, when only a relatively small drive capability is required, it is possible to stop or suppress excessive power supply to the buffer circuit so as to prevent inconsistency in the signal transmission operation for all signals. The power consumption can be reduced according to the correlation of the input signal to the circuit.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention. FIG. 1A shows a configuration of a driver circuit according to an embodiment of the present invention.
FIG. 2B shows the configuration of the timing control circuit 21-1 shown in FIG.

In these figures, the present invention relates to (n + 1)
It comprises (n + 1) sets of driver circuits for transmitting the input signals 101 as (n + 1) driver output signals 102. That is, the driver circuit of the present invention includes one set of reference driver circuit 1 and n sets of driver circuits 2-1 to 2
-N.

The reference driver circuit 1 includes a buffer circuit 11
And a delay circuit 12.
Realizes the delay time td1. Driver circuits 2-1 and 2
-N indicates timing control circuits 21-1 to 21-n (timing control circuits 21-1 to 21-n are not shown) and delay circuits 22-1 to 22-n (delay circuits 22-2 to 22-n).
Is not shown), and a power controllable buffer circuit 23-1.
23-n (buffer circuits 23-2 to 23-n are not shown) and output changeover switches 24-1 to 24-n (output changeover switches 24-2 to 24-n are not shown). ing.

The delay circuits 22-1 to 22-n have a delay time t
d2 is realized. Timing control circuits 21-1 to 21-
n is an input signal IN0 to the reference driver circuit 1 and an input signal IN corresponding to each of the driver circuits 2-1 to 2-n.
1 to INn, each of which can be controlled in power.
This circuit generates a control signal CTRL for controlling the operation of each of 3-1 to 23-n and a control signal SW for controlling the output changeover switches 24-1 to 24-n.

The timing control circuits 21-1 to 21-n include delay circuits 21b-1 to 21b-n and 21c-1 to 21c.
−n, 21f-1 to 21f-n (delay circuits 21b-2 to 21f-2
21b-n, 21c-2 to 21c-n, 21f-2 to 2
1f-n are not shown) and a logic circuit for synthesizing respective control signals using these, that is, exclusive OR circuits 21a-1 to 21a-n (exclusive OR circuit 21a-2).
To 21a-n are not shown) and an OR circuit 21d-
1 to 21d-n, 21e-1 to 21e-n (OR circuit 2
1d-2 to 21d-n and 21e-2 to 21e-n are not shown).

The delay circuits 21b-1 to 21b-n, 21c
-1 to 21c-n and 21f-1 to 21f-n realize delay times td3, td4 and td5, respectively. Control signal CT
RL is a control signal for activating or deactivating each of the buffer circuits 23-1 to 23-n.
W is the output of the driver circuits 2-1 to 2-n, one of the output of each of the power controllable buffer circuits 23-1 to 23-n and the output of the buffer circuit 12 of the reference driver circuit 1. Output changeover switch 24 for connection
These are control signals for -1 to 24-n.

The power controllable buffer circuit 23-1
23-n, the time required for the operation to stabilize when transitioning from the inactive state to the active state is represented by Ts
t, the time from when the output signal changes with the change in the input signal to when the output signal is sufficiently stabilized is Ttr, and the time required for the driver output changeover switches 24-1 to 24-n to change the connection is Tsw. Td1 = td2 (1) td1> td5 (2) td3>td4> td5 (3) td3 + td5> td1 (4) td5> Tst (5) td3 + td5- td1> Ttr (6) td1-td5> Tsw (7) td4-td5> Tsw (8) The respective delay times td1 to td satisfy the relational expression:
Adjust 5

The input signal IN which is a part of the input signal 101
When p and INq (1 ≦ p ≦ n, 1 ≦ q ≦ n) have the same value for a certain period, all the power controllable buffer circuits 23-1 to 23-n operate simultaneously during that period. It is not necessary that the buffer circuits 23-p and 23-p which can control the power corresponding to one of the input signals INp and INq.
The output of q can be used as output signals OUTp and OUTq that are part of the driver output signal 102.

For example, if the output signal of the power controllable buffer circuit 23-p corresponding to the input signal INp is output as both output signals OUTp and OUTq at this time, the power control corresponding to the input signal INq can be performed. The buffer circuit 23-q is temporarily unnecessary, and at this time, by stopping or suppressing the power supply to the buffer circuit 23-q corresponding to the input signal INq, the power consumption of the entire driver circuit system can be reduced.

The timing control circuits 21-1 to 21-n perform an exclusive OR circuit 21a-1 on the input signal IN0 to the reference driver circuit 1 and the input signals IN1 to INn to its own circuit.
21a-n, and the comparison result is generated as a signal DIFF. Here, the signal DIFF is logically “0”.
, The input signal IN0 and the input signals IN1-I
NN indicates that the logic is the same as Nn, and the signal DIFF
Is logically "1", it is assumed that the logics of these input signals IN0 and IN1 to INn do not match.

The power controllable buffer circuit 23-
Each of 1 to 23-n becomes inactive when the control signal CTRL is "0", and becomes active when the control signal CTRL is "1". Further, the driver output circuit 2-
Outputs 1 to 2-n are connected to the output of the buffer circuit 12 of the reference driver circuit 1 when the control signal SW is "0", and the driver circuits 2-1 to 2-n when the control signal SW is "1".
The outputs of the power-controllable buffer circuits 23-1 to 23-n are connected.

When the signal DIFF changes from "0" to "1", the control signal CTRL simultaneously changes from "0" to "1", and the power controllable buffer circuits 23-1 to 23-n
Activate each. In addition, power controllable buffer circuits 23-1 to 23-n that have transitioned from the inactive state to the active state
OUT1 which is the driver output signal before the output of
OUTn is not switched, the control signal SW is set to “1” after the delay time td5 has elapsed.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. FIG. 2A shows that the input signal IN0 to the reference driver circuit 1 does not change and the driver circuit 2-
When the input signal INm to m (1 <m <n) changes [When the input signal INm changes from low level (L) to high level (H), or the input signal INm changes from high level to low level In the case of the above).

FIG. 2B shows a case where the input signal IN0 to the reference driver circuit 1 changes without changing the input signal INm to the driver circuit 2-m (the input signal IN0 changes from a low level to a high level). (When the input signal IN0 changes from high level to low level)
3 shows changes of each signal.

According to FIG. 2, the input signals IN0, IN
The change in the correlation of m is guided to the power controllable buffer circuit 23-m with a delay of the delay time td1. This is td1>
Since td5> Tst, the output of the buffer circuit 12 of the reference driver circuit 1 is transmitted after the power controllable buffer circuit 23-m is completely activated. Since (td1-td5)> Tsw, the output signal OUTm in the driver circuit 2-m is output.
The connection between the buffer circuit 23-m and the power controllable buffer circuit 23-m is completed.

Therefore, each of the reference driver circuit 1 and the driver circuit 2-m can output a signal with sufficient driving capability. When the signal DIFF changes from “1” to “0”, the control signal SW changes from “1” to “0” after the delay time (td3 + td5),
The control signal CTRL changes from “1” to “0” after the delay time (td3 + td4), and stops or suppresses the power supply to the power controllable buffer circuit 23-m.

((Td3 + td4)-(td3 + td)
5))> Tsw, the output signal OUTm is set to the reference driver before the power controllable buffer circuit 23-m is stopped or suppressed by the control signal CTRL to be in an output disabled state. The output is switched to the output of the buffer circuit 12 in the circuit 1.

Also, (td3 + td5-td1)> Tt
r, the change of the output by the control signal SW is transmitted to the buffer circuit 23-m in which the change in the correlation between the input signals IN0 and INm can be controlled, and the reference driver circuit 1
And after each of the driver circuits 2-m outputs a signal with sufficient drive capability.

FIG. 3 is a block diagram showing the configuration of one embodiment of the present invention. FIG. 3A shows the configuration of a driver circuit according to one embodiment of the present invention, and FIG. 3B shows the configuration of the timing control circuit 41-1 of FIG. 3A.

Referring to the figure, one embodiment of the present invention comprises 16 sets of driver circuits for transmitting 16 input signals 111 as 16 driver output signals 112. That is, the driver circuit according to one embodiment of the present invention includes one set of the reference driver circuit 3 and 15 sets of the driver circuits 4-1 to 4-4.
-15.

The reference driver circuit 3 includes a delay circuit 31 and a buffer circuit 32. The delay circuit 31 has a delay time td
1 is realized. The driver circuits 4-1 to 4-15 include timing control circuits 41-1 to 41-15 (timing control circuits 42-1 to 41-15 are not shown) and a delay circuit 42.
-1 to 42-15 (delay circuits 42-2 to 42-15 are not shown) and buffer circuits 43-1 to 4-4 which can control power.
3-15 (buffer circuits 43-2 to 43-15 are not shown) and output changeover switches 44-1 to 44-15 (output changeover switches 44-2 to 44-15).

The output changeover switches 44-1 to 44-
Reference numeral 15 denotes inverters 44a-1 to 44a-15 (the inverters 44a-2 to 44a-15 are not shown) and transistors 44b-1 to 44b-15, 44c-1 to 44c-
15 (inverters 44b-2 to 44b-15, 44c-
2-44c-15 are not shown).
Transistors 44b-1 to 44b-15, 44c-1
44c-15 is a combination of P-channel and N-channel transistor elements.

Timing control circuits 41-1 to 41-15
Are input signals IN0 to the reference driver circuit 3 and input signals IN1 to IN1 corresponding to the driver circuits 4-1 to 4-15.
Buffer circuits 43-1 to 43-3 that can control power from IN15
This circuit generates a control signal CTRL for controlling the operation of 43-15 and a control signal SW for controlling the output changeover switches 44-1 to 44-15.

Timing control circuits 41-1 to 41-15
Are delay circuits 41b-1 to 41b-15 and 41c-1 to 4
1c-15, 41f-1 to 41f-15 (delay circuit 41
b-2 to 41b-15, 41c-2 to 41c-15, 4
1f-2 to 41f-15 are not shown) and a logic circuit for synthesizing the respective control signals using them, that is, exclusive OR circuits 41a-1 to 41a-15 (exclusive OR circuits 41a-41). Nos. 2 to 41a-15 are not shown) and NOR circuits 41d-1 to 41d-15 and 41e-1.
41e-15 (the NOR circuits 41d-2 to 41d-15,
41e-2 to 41e-15 are not shown) and the inverter 4
1g-1 to 41g-15, 41h-1 to 41h-15
(Inverters 41g-2 ~ 41g-15, 41h-2 ~
41h-15 are not shown).

The delay circuits 42-1 to 42-15 realize the delay time td2, and the delay circuits 41b-1 to 41b-15,
41c-1 to 41c-15, 41f-1 to 41f-15
Realize delay times td3, td4, and td5, respectively.

The control signal CTRL is a control signal for activating or deactivating the power controllable buffer circuits 43-1 to 43-15, and the control signal SW is the output of the driver circuits 4-1 to 4-15. And output changeover switches 44-1 to 44-1 for connecting one of the outputs of the power controllable buffer circuits 43-1 to 43-15 and the output of the buffer circuit 32 of the reference driver circuit 3.
5 is a control signal.

The power controllable buffer circuit 43-1
43 to 15-15, when the state shifts from the inactive state to the active state, the time required for stabilizing the operation is represented by Tst,
If the time from when the output signal changes with the change in the input signal until the output signal is sufficiently stabilized is Ttr, and the time required for the driver output changeover switches 44-1 to 44-15 to change the connection is Tsw, Tst = 2.0 ns, Ttr = 1.0 ns, Tsw =
It has a characteristic of 0.5 ns.

At this time, the delay times td1 to td5 are adjusted such that td1 = 3.5 ns td2 = 3.5 ns td3 = 4.0 ns td4 = 3.5 ns td5 = 2.5 ns. This is due to the above-mentioned conditional expressions (1) to
Satisfies all of (8).

In this embodiment, the input signal INm (1 ≦ m ≦
In the driver circuit 4-m corresponding to 15), the timing control circuit 41-m generates an exclusive OR of the input signals IN0 and INm as a signal DIFF. That is, when the signal DIFF is logically "0", the input signal IN
0 indicates that the logic of the input signal INm matches, and when the signal DIFF is logically “1”, it indicates that the logic of the input signal IN0 does not match the logic of the input signal INm.

The signal DIFF and this are represented by (td3 + td4)
A control signal CTRL is obtained by performing an OR operation with a signal delayed by (= 7.5 ns). This control signal CTRL
Controls the power supply of the power controllable buffer circuit 43-m. When this is logically "0", the power controllable buffer circuit 43-m is cut off the power supply and stops operating.
When this is logically "1", power is supplied and activated.

The signal DIFF and this signal are expressed as td3 (= 4.0n).
s) and the control signal SW
Generate When the control signal SW is logically “0”, the output signal OUTm is output from the buffer circuit 3 of the reference driver circuit 3.
2 is connected to the output of the driver circuit 4-m when it is logically "1".
m outputs are connected.

When the signal DIFF changes from "0" to "1", the control signal CTRL simultaneously changes from "0" to "1" to activate the buffer circuit 43-m.
Further, in order to guarantee that the output is not switched before the output of the buffer circuit 32 is stabilized, td5 (= 2.5n
After s), the control signal SW is set to “1”.

According to FIG. 2, the change in the correlation between the input signals IN0 and INm is guided to the power controllable buffer circuit 43-m with a delay of td1, which is td1 (= 3.5n).
Since s)> Tst (= 2.0 ns), the signal is transmitted after the power controllable buffer circuit 43-m is completely activated.

At this time, (td1-td5) (= 1.0
ns)> Tsw (= 0.5 ns), the connection between the output OUTm of the driver circuit 4-m and the output of the power controllable buffer circuit 43-m has already been completed, and the buffer of the reference driver circuit 3 has been completed. The output load of the circuit 32 is reduced. Therefore, the reference driver circuit 3 and the driver circuit 4-m operate independently, and output signals with sufficient driving capability.

When the signal DIFF changes from "1" to "0", the control signal SW changes from "1" to "0" after td3 + td5, and the control signal CTRL changes to (td
3 + td4) (= 7.5 ns), then “1” to “0”
, The power controllable buffer circuit 43-m
Is stopped or suppressed.

Further, ((td3 + td4)-(td3
+ Td5)) (= 1.0 ns)> Tsw (= 0.5 n
s), the power controllable buffer circuit 43
The output signal OUTm is switched to the output of the buffer circuit 32 in the reference driver circuit 3 before -m is turned off or suppressed by the control signal CTRL so that the output becomes impossible.

Further, (td3 + td5-td1)
(= 3.0 ns)> Ttr (= 1.0 ns), the output switching by the control signal SW is performed by the input signal IN.
The change in the correlation between 0 and INm is transmitted to the power controllable buffer circuit 43-m, and is performed after each of the reference driver circuit 3 and the driver circuit 4-m outputs a signal with sufficient drive capability.

Therefore, for example, in a driver system for transmitting two or more independent signals, many signals having the same output value can be output with a small number of buffer circuits during a period in which the input signal does not fluctuate. Power consumption can be reduced by stopping or suppressing the power supply to the excess buffer circuit.

As described above, the plurality of input signals IN0-IN
n, a plurality of buffer circuits 12, 23-1 to 23-n, 32, 43-1 for independently outputting IN0 to IN15, respectively.
43 to 15-15, a plurality of buffer circuits 12, 23-1 to 23-n, 3 according to the correlation of the plurality of input signals IN0 to INn, IN0 to IN15.
2, 43-1 to 43-15 are independently activated, and a plurality of input signals IN0 to INn and IN0 to IN1 are activated.
5, a plurality of buffer circuits 23-1 to 23-
n, 43-1 to 43-15 are deactivated independently and the buffer circuits 23-1 to 23-n, 43-1 to 43-43 are deactivated.
By outputting the output signals of the other buffer circuits (output signals of the buffer circuits 12 and 32 of the reference driver circuits 1 and 3) from -15, if only a relatively small drive capability is required, signals for all signals are output. Since power supply to an excessive buffer circuit can be stopped or suppressed so that inconsistency does not occur in the transmission operation, power consumption can be reduced according to the correlation of input signals to the driver circuit.

[0059]

As described above, according to the present invention, in a driver circuit including a plurality of output circuits for independently outputting a plurality of digital signals, a plurality of output circuits are provided in accordance with the correlation of the plurality of digital signals. By independently activating each, independently deactivating each of the plurality of output circuits according to the correlation of the plurality of digital signals, and outputting the output signal of another output circuit from the output circuit,
There is an effect that unnecessary constant power consumption for always keeping the buffer circuit active when the driver system is active can be prevented.

[Brief description of the drawings]

FIG. 1A is a diagram illustrating a configuration of a driver circuit according to an embodiment of the present invention, and FIG. 1B is a diagram illustrating a configuration of a timing control circuit of FIG.

FIG. 2A is a diagram illustrating a change in each signal when an input signal to another driver circuit changes without changing an input signal to a reference driver circuit in the embodiment of the present invention;
FIG. 3B is a diagram illustrating a change in each signal when an input signal to a reference driver circuit changes and an input signal to another driver circuit does not change in the embodiment of the present invention.

FIG. 3A is a diagram illustrating a configuration of a driver circuit according to an embodiment of the present invention, and FIG. 3B is a diagram illustrating a configuration of a timing control circuit of FIG.

FIG. 4 is a circuit diagram showing an example of a conventional driver circuit.

FIG. 5 is a circuit diagram showing another example of a conventional driver circuit.

[Description of Reference Symbols] 1,3 Reference driver circuits 2-1 to 2-n, 4-1 to 4-15 Driver circuits 11, 21b-1, 21c-1, 21f-1, 22
1, 31, 41b-1, 41c-1, 41f-1, 42
-1 Delay circuit 12, 23-1, 32, 43-1 Buffer circuit 24-1, 44-1 Switch circuit 21-1, 41-1 Timing control circuit 21a-1, 41a-1 Exclusive OR circuit 21d- 1,21e-1 OR circuit 41d-1,41e-1 NOR circuit 41g-1,41h-1 Inverter

Claims (4)

(57) [Claims] 1. A driver circuit comprising a plurality of output circuits for independently transmitting a plurality of digital signals , wherein at least one of the plurality of digital signals is provided.
One of the reference input signals set as a reference and the plurality of outputs.
An output circuit of the input circuit, the input circuit receiving the reference input signal
The output circuits other than the output circuit that receives the reference input signal in accordance with the correlation with the digital signal to each output circuit other than the output circuit
Means for independently activating each of the paths, and the reference input signal
An output circuit other than an output circuit that receives the reference input signal
The reference input according to the correlation with each digital signal
Means for independently deactivating each output circuit other than the output circuit to which a signal is input, and outputting an output signal of another output circuit from the output circuit. 2. A driver circuit comprising a plurality of output circuits for independently transmitting a plurality of digital signals, wherein at least one of the plurality of digital signals is provided.
Comparing means for comparing a reference input signal set as a reference with an input signal to the own circuit; and when the comparing means detects a match, power supply to the own circuit is suppressed and a mismatch is detected by the comparing means. Means for restoring power supply to the own circuit when the signal is output, and when a match is detected by the comparing means, an output signal of an output circuit which receives the reference input signal as an input is used as an output of the own circuit. wherein the switching means for outputting an input signal as to its own circuit when the detected
Driver circuit, characterized in that it comprises the output circuit of each non <br/> output circuit for receiving the reference input signal of the plurality of output circuits. 3. The driver circuit according to claim 2, wherein each of the plurality of output circuits includes a buffer circuit. 4. The driver circuit according to claim 2, wherein each of the plurality of output circuits includes a unit for delaying the output of the digital signal until the switching operation of the switching unit is completed. .