JP3010657B2 - Amplitude equalizer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a variable amplitude equalizer used in a signal transmission system.

[Conventional technology]

In general, the characteristics, distortion, and the like of a signal transmission path are not fixed but often involve some kind of fluctuation. For example, amplitude distortion occurs and fluctuates due to selective fading in a wireless transmission path. In order to automatically remove such distortions and maintain the quality of the transmitted signal, for example, an automatic amplitude equalizer is required, for example, a configuration as proposed in Japanese Patent Application No. 54-156610. Are known.

FIG. 2 is a block diagram showing an example of a conventional amplitude equalizing circuit. In the figure, an input signal input to an input IN is branched by a first signal branching circuit 21, one of which is delayed by a first delay circuit (delay time τ) 22, and further a second signal branching circuit 23 Is branched. Second signal branch circuit
One signal branched at 23 is delayed by a second delay circuit (delay time τ) 25, and is combined at a second combining circuit 24 with the other signal branched at the first signal branching circuit 21. You. The combined signal is input to the pulse amplitude variation circuit 26, it is varied in a desired degree of amplification and attenuation α by a control signal S _c.

The other signal branched by the second signal branching circuit 23 is combined with a signal from the polarity / amplitude variable circuit 26 in a second combining circuit 28 and output to an output OUT as an output signal.

Here, the input signal is e ^jwt , the first delay circuit 22 and the second
Each delay time in the delay circuit 25 is τ, and the polarity amplitude variable circuit 26
Control signal S to the amplitude or attenuation obtained by _c alpha, if the signal to be synthesized by the second synthesis circuit 28, respectively and A _2, B _{2 ^{in, A 2 = α (e jwt}} + e -jw (t- ^2τ) ) B ₂ = e ^{jw (t−τ)} , so the signal at the output OUT is C ₂ = A ₂ + B ₂ = e ^−jwτ (1 + 2αcosωτ). Therefore, the transfer function T representing the input / output characteristics
₂ (ω) is expressed by the following equation.

T ₂ (ω) = (1 + 2αcosωτ) e− ^jwτ Here, the characteristics of the amplitude, phase and delay time are represented by S
₂ (ω), θ ₂ (ω) and D ₂ (ω) _{S 2 (ω) = 1 +} 2αcosωτ θ 2 (ω) = ωτ D 2 (ω) = dθ 2 (ω) / dω = τ (= const.) And made.

Therefore, by changing α, the amplitude characteristic changes, but the delay time is always constant, and no delay distortion occurs. That is, it is possible in principle to equalize only the amplitude versus frequency characteristics without causing delay distortion.

[Problems to be solved by the invention]

However, in the above-described conventional amplitude equalizer, the delay amount Δτ generated in the polarity / amplitude variable circuit 26 is not taken into consideration. Therefore, the signal A ₂ of the delay amount τ + Δτ and the delay amount and the signal B _{2 of} τ is synthesized, and as a result, the signal C ₂ ′ at the output OUT becomes C ₂ ′ = e ^jwt (1 + e− ^jwΔτ 2αcosωτ) e− ^jwτ . As a result, there is a problem that a desired amplitude frequency characteristic cannot be obtained, and a delay distortion is generated due to a change in α, thereby deteriorating the performance as an equalizer.

An object of the present invention is to provide an amplitude equalizer that does not cause delay distortion.

[Means for Solving the Problems] The amplitude equalizer of the present invention is provided with a third delay circuit that delays the signal branched by the first and second signal branch circuits by a delay time Δτ. And the output signal of the polarity amplitude variable circuit having a delay time Δτ is synthesized by the second synthesizing circuit and output.

[Action]

According to this configuration, since the signals from the first and second signal branch circuits are delayed by the third delay circuit to the same delay amount as the output signal from the polarity / amplitude variable circuit, delay distortion is eliminated. This prevents the performance of the equalizer from deteriorating due to delay distortion.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, an input signal input to an input IN and having an amplitude distortion characteristic within a certain frequency band is branched by a first signal branch circuit 11, one of which is a first delay circuit (delay time τ) 12
And the signal is further branched by the second signal branch circuit 13. One of the signals branched by the second signal branch circuit 13 is delayed by a second delay circuit (delay time τ) 15,
In the second combining circuit 14, the signal is combined with another signal branched by the first signal branching circuit 11. The synthesized signal is input to the polarity / amplitude variable circuit 16, and the required delay time Δ
is variably controlled in amplitude and attenuation α is controlled by a control signal S _c in tau.

The other signal branched by the second signal branch circuit 13 is delayed by a third delay circuit (delay time Δτ) 17, and the signal from the polarity amplitude variable circuit 16 is delayed by a second synthesis circuit 18. And output as an output signal to the output OUT.

In this case, the delay time Δτ of the polarity amplitude variable circuit 16
And the delay time Δτ of the third delay circuit 17 is selected to be equal.

According to this configuration, ^assuming that each signal synthesized by the second synthesis circuit 18 is A ₁ and B ₁ , A ₁ = α (e ^jwt + e ^{jw (t−2τ)} ) e ^−jwΔτ B ₁ = e ^{jw (t−τ)} · e− ^jwΔτ . Thus, the composite signal C ₁ at the output OUT of the second combining circuit 18 becomes _{^{C 1 = e jwt e -jw (}} τ + Δτ) (1 + 2αcosωτ). Therefore, the transfer function T ₁ (ω) is expressed by the following equation.

T ₁ (ω) = (1 + 2αcosωτ) e− ^{jw (τ + Δτ)} The characteristics of the amplitude, phase and delay time are S ₁ (ω) and θ, respectively.
₁ (ω) and D ₁ (ω), S ₁ (ω) = 1 + 2αcosωτ θ ₁ (ω) = ω (τ + Δτ) D ₁ (ω) = dθ ₁ (ω) / dω = τ + Δτ (= const.) As is clear from these equations, α is changed. This makes it possible to realize an equalizer in which the amplitude characteristic changes but no delay distortion occurs.

〔The invention's effect〕

As described above, according to the present invention, the output signal of the first and second signal branch circuits combined with the output signal of the variable polarity amplitude circuit in the second combining circuit is converted by the third delay circuit into the variable polarity amplitude circuit. Since the delay is the same as that in the above, it is possible to prevent fluctuations in the required amplitude frequency characteristics due to the delay time of the polarity amplitude variable circuit and delay distortion, thereby preventing the performance of the equalizer from deteriorating. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the amplitude equalizer of the present invention,
FIG. 2 is a block diagram of a conventional amplitude equalizer. 11,21 ... first signal branch circuit, 12,22 ... first delay circuit, 13,23 ... second signal branch circuit, 14,24 ... first synthesis circuit, 15,25 ... ... a second delay circuit, 16, 26 ... a polarity amplitude variable circuit, 17 ... a third delay circuit, 18, 28 ... a second synthesis circuit.

Claims (1)

(57) [Claims] 1. A first signal branching circuit for branching an input signal having an amplitude distortion characteristic within a certain frequency band, and a first signal branching circuit for delaying one of the branched signals by a delay time τ determined by the frequency band. , A second signal branching circuit for branching the delayed signal, a second delay circuit for delaying one of the signals branched by the second signal branching circuit by a delay time τ, A first synthesizing circuit for synthesizing the delayed signal of the second delay circuit and another signal branched by the first signal branching circuit; A polarity / amplitude variable circuit controlled by time Δτ, a third delay circuit for delaying the other signal branched by the second signal branching circuit by delay time Δτ,
And a second synthesizing circuit for synthesizing the signal from the delay circuit and the signal from the polarity amplitude variable circuit.