JP3013675B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument, a multimedia device, a game device, an audio processing device, a video processing device, and a signal processing device built in a computer.

[0002]

2. Description of the Related Art As is well known, an output signal of a sound source built in an electronic musical instrument or an analog signal obtained by playing an acoustic musical instrument or the like is converted into an analog / digital (A / D) signal using a DSP (digital signal processor). 2.) An effect imparting device for imparting various effects to a converted signal has been developed. Conventionally, in this type of effect imparting device, when switching the type of effect to be imparted during a performance, the output sound of the effect circuit relating to the switching is first silenced, and the silencing is released after the switching operation is completed. . This is to prevent noise at the time of switching. However, when the switching is performed by the above method, the sound is interrupted at the time of the switching, so that the effect switching during the performance involves unnaturalness.

[0003] Therefore, the applicant, when switching the effect,
By setting the balance of wet (sound with effect) / dry (direct sound without effect) dry = 100%, only the sound with effect is muted, and the direct sound is set to be through. We proposed a method to prevent the sound interruption.

[0004]

However, according to the above-mentioned method proposed by the applicant, when only one effect is simultaneously given to the output signal, the type of the effect can be changed without noise or sound interruption. Although it is possible to switch, if a plurality of effects are given at the same time and one of the effects is switched, the following problem occurs.

[0005] That is, the effect is provided by executing a microprogram corresponding to each effect in the DSP. Therefore, when switching the effect to be provided, it is necessary to rewrite the microprogram executed in the DSP. If the steps of the microprogram are executed during the rewriting of the microprogram, the correspondence between the instruction code and the address cannot be maintained, and the data at the address that should not be accessed may be rewritten. Therefore, when a plurality of effects are given at the same time, a plurality of microprograms are executed in a time-sharing manner. There is a risk of rewriting the contents of the delay RAM and the register. Such rewriting of erroneous data results in noise appearing in other sound effects.

In order to avoid such inconvenience, it is necessary to satisfy the following conditions. That is, (1) When rewriting a certain step of the microprogram, the data of the step must be rewritten at a time. (2) The data in the coefficient register and the address register corresponding to the above steps must be rewritten simultaneously.

However, it is impossible to simultaneously rewrite the corresponding steps of the microprogram, the coefficient register and the address register for the following reasons. That is, generally, a CPU (central processing unit) has an 8-bit or 16-bit data line, but the bit length of a microprogram is usually larger than the number of data lines, and the coefficient register and the address register are micro-processors. This is because it is provided independently of a register for storing a program (micro program register).

In order to satisfy the above conditions (1) and (2), a transfer buffer is provided between the data bus of the CPU and the microprogram register, coefficient register and address register. A method is conceivable in which data is sequentially written and rewriting is performed collectively when all data has been written. However, when this method is adopted, there is a problem that the device configuration becomes complicated.

The present invention has been made in view of such a background, and a signal processing apparatus which does not cause a malfunction such as writing to an erroneous data storage area even when an execution program is changed during processing. It is intended to provide.

[0010]

To solve the problems described above SUMMARY OF THE INVENTION The present invention provides a signal processing apparatus for performing repeatedly in a time division multiple programs including various instruction steps, at least one of the plurality of programs being executed Program rewriting means for rewriting one program into a program to be executed after the change, and at least one program during a rewriting operation by the program rewriting means.
Finger that instructs to invalidate the data write instruction contained in the
Instructing means for generating indication data, and the instructing instruction
Depending on the instruction data unit, the invalid to invalidate the data write command is included in at least one pro <br/> grams
; And a means, to the at least one program
Contains an invalidation control instruction in advance, and the invalidation means
Responding to the instruction of the invalidation instruction means,
Also has the invalidation control instruction included in one program.
Enabling the at least one program
Is invalidated . Further, the present invention provides the plurality of programs,
Each includes an invalidation control instruction, and the invalidation
Indicating means for rewriting among the plurality of programs.
Invalidation control embedded in the program being attempted
Generating instruction data indicating an instruction;
Enables the invalidation control instruction indicated by the instruction data
It is characterized by that. The present invention also relates to a method including a branch instruction.
It stores a fixed number of micro-instructions and
Microinstruction storage means for outputting micro instructions cyclically
The microinstruction output by the microinstruction storage means.
And decoding means for encoding, and outputs a control signal, operation life
Performing arithmetic processing in accordance with the control signal corresponding to the instruction.
Calculating means, and various data including a calculation result by the calculating means.
A data storage means used to store data, the effective or no
Branch instructing means for generating branch control data for instructing a branch
The decoding means decodes the first branch instruction;
If the branch control data indicates valid, then
To the branch destination address corresponding to the first branch instruction
Write data to the data storage means only during the period
First branch control means for invalidating the control signal for instructing
And characterized in that: The present invention further provides
The decoding means decodes the second branch instruction;
If the branch control data indicates invalid, then
To the branch destination address corresponding to the second branch instruction
Write data to the data storage means only during the period
Branch control means for invalidating the control signal for instructing
It is characterized by having. The present invention also provides a
Stores a series of a predetermined number of microinstructions, including branch instructions
Also, micro that outputs each micro instruction cyclically
Instruction storage means and a micro instruction storage means
Decode instructions that decode clock instructions and output control signals
And an operation processing section according to the control signal corresponding to the operation instruction.
Calculating means for performing the calculation, and calculating the calculation result by the calculating means.
Data storage means used for storing various data including
Multiple branch control data, each indicating valid or invalid
The branch instructing means for generating data and the decoding means
Decode one of the number of branch instructions,
And the decoded one of the plurality of branch control instructions is
Indicates that the branch control data corresponding to the branch instruction
From that point, the decoded branch instruction
Only during the period up to the corresponding branch destination address,
The control signal instructing data writing to the storage means
Branch control means for invalidating
You.

According to the present invention, while the program rewriting means rewrites at least one program among the plurality of programs being executed to a program to be executed after the change, the invalidation instruction means keeps the at least One professional
Command to invalidate the data write instruction included in the program
Instruction data. The invalidation means is an invalidation instruction hand.
The at least one program according to the instruction data of the column.
Invalidate the data write instruction included in the RAM. sand
That is, the at least one program is invalidated in advance.
A control command, wherein the invalidating means includes
The at least one program according to the instruction of the
Activating the invalidation control instruction included in the program
The data included in the at least one program.
Invalidates the data write instruction.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. A: Overall Configuration FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In this figure, 1 is a panel switch.
The panel switch 1 includes switches for designating various effects (hereinafter, referred to as effects) such as reverb, chorus, and distortion, and other operators. Reference numeral 2 denotes a panel interface which detects an operation of the panel switch 1 and transmits an operation signal corresponding to the operation to the bus B.
Send to US1.

Reference numeral 3 denotes a keyboard which is depressed and released by an operator. The keyboard interface 4 detects a key press / release operation on each key of the keyboard 3 and sends an operation signal corresponding to the operation to the bus BUS1.

Reference numeral 5 denotes a CPU (Central Processing Unit) for controlling each unit of the device connected via the bus BUS1.
The operation of the CPU 5 will be described later. 6 is R
An OM (Read Only Memory), which stores various control programs executed by the CPU 5 and microprograms executed when a DSP (digital signal processor) 9 described later applies various effects to musical sounds. 7
Is a RAM (Ra) used as a work area of the CPU 5.
ndom Access Memory) in which various register values and calculation results are temporarily stored.

Next, reference numeral 8 denotes a sound source. This sound source 8 is C
A tone signal corresponding to a tone control parameter supplied from the PU5 via the bus BUS1 is generated and output. D
The SP 9 executes a microprogram transferred from the ROM 6 via the bus BUS1 to perform signal processing on the tone signal supplied from the sound source 8 and to provide various effects. The details of the configuration of the DSP 9 will be described later.

Also, 10L and 10R are D / A (digital / analog) provided corresponding to left and right two channels.
It is a converter. The D / A converter 10L converts the signal-processed digital tone signal supplied from the left channel of the DSP 9 into an analog signal, and outputs the analog signal. On the other hand, D /
The A converter 10R converts the digital tone signal after signal processing supplied from the right channel of the DSP 9 into an analog signal and outputs this. Further, LSP and RSP are sound systems provided corresponding to the two channels on the left and right, respectively, and generate sounds in accordance with analog tone signals supplied from the D / A converters 10L and 10R, respectively.

B: Configuration of DSP 9 Next, the configuration of the DSP 9 will be described in detail. FIG.
FIG. 3 is a block diagram showing a configuration of the DSP 9. In this figure, the DSP 9 is composed of an effect imparting section 91 for performing various signal processing on a tone signal supplied from the sound source 8 and a write command control section 92 for controlling effect switching. Hereinafter, these units 91 and 92 will be described in detail.

(1) Configuration of Effect Giving Unit 91 The effect giving unit 91 includes an input register 11, a data register 12, an arithmetic circuit 13, an interpolation circuit 14, a coefficient register 15, an LFO (low frequency oscillator) 16, a latch circuit 17, A delay RAM 18 provided outside the DSP 9;
Address register 19, address control circuit 20 and D
It is composed of an SP data bus BUS2.

The input register 11 receives a tone signal supplied from the sound source 8 in response to a write command WR based on a microprogram, and stores the signal. The data register 12 stores the arithmetic result supplied from the arithmetic circuit 13 via the bus BUS2 and the bus BUS from the delay RAM 18.
2 is temporarily stored. The data register 12 is used to write, read, or specify an address according to various instructions such as a write instruction WR based on a microprogram.

Next, the arithmetic circuit 13 is composed of a multiplier and an adder. The arithmetic circuit 13 receives the tone signal supplied from the input register 11, the data supplied from the data register 12, the coefficient supplied from the coefficient register 15 via the interpolation circuit 14, and the modulated waveform data supplied from the LFO 16. And performs signal processing based on the microprogram, and transfers the processing result to the bus BU.
Send to S2.

The interpolation circuit 14 has a coefficient register 15
Is subjected to interpolation processing in accordance with the interpolation rate supplied from the CPU 5 (see FIG. 1) via the bus BUS1, and the interpolation value is output to the arithmetic circuit 13.
Note that the coefficient stored in the coefficient register 15 is
Can be rewritten by a rewrite command supplied from the device via the bus BUS1. As a result, it is possible to control the timbre by changing the coefficients used in the filter operation or the like.

Further, the LFO 16 generates a modulation waveform such as a triangular wave, a sawtooth wave, and a sine wave to perform amplitude modulation, delay time modulation, and the like, and outputs this to the arithmetic circuit 13 and the address control circuit 20.

Next, the latch circuit 17 fetches, via the bus BUS2, the musical tone signals of the left and right two channels subjected to the signal processing by the arithmetic circuit 13, and latches them. The output of the latch circuit 17 is supplied to the D / A converters 10L and 10L.
After being supplied to R (see FIG. 1) and converted into an analog signal, sound is generated from the sound systems LSP and RSP (see FIG. 1).

The delay RAM 18 is a memory used to generate a delay signal. This delay RAM1
8 are supplied from the address control circuit 20 based on a microprogram. Since the delay RAM 18 has a large capacity, it is usually provided outside the DSP 9.

Further, the address register 19 has a delay R
A relative address is stored assuming that the head address of the AM 18 is "0", and this relative address is output at an access timing according to the execution of the microprogram.
In addition, the address control circuit 20 includes an address register 19
And the address offset corresponding to the head address of the delay RAM 18 are added, and the sum is output to the delay RAM 18 as an absolute address.

(2) Configuration of Write Command Control Unit 92 Next, the write command control unit 92 includes a microprogram register 21, a program decoder 22, a flag register 23, a jump step register 24, a comparator 25,
Program counter 26, AND gates 27, 31, 3
4, 36, OR gates 28 and 29, a delay circuit 30, and inverters 32, 33 and 35. What
Note that the CPU 5 and the flag register 23 are the same as those of the present invention.
Jump step register 24, comparison
Unit 25, program counter 26, AND gate 27,
31, 34, 36, OR gates 28, 29, delay circuit 3
0 and inverters 32, 33, 35 disable the present invention.
It corresponds to a means.

The microprogram register 21 has R
A microprogram corresponding to a plurality of effects supplied from the OM 6 (see FIG. 1) via the bus BUS1 is stored. The program decoder 22 uses this register 2
Various instructions output from 1 are decoded, and the decoding result is output.

The flag register 23 stores jump flags f0 to fn corresponding to each effect. Here, the jump flags f0 to fn are flags indicating conditions for determining whether a jump instruction included in a microprogram corresponding to each effect is valid or invalid. These jump flags f0 to fn are written from the CPU 5 via the bus BUS1. The jump command is a command that invalidates all write commands included in the program until the process proceeds to a step (hereinafter, referred to as a jump step) of a microprogram designated by the command. The jump instruction includes a jump instruction jft which is valid when the value of the corresponding jump flag is "1" and invalid when the value is "0", and a valid value when the value of the jump flag is "0". Jump instruction jf which becomes invalid when is "1"
There are two types of f.

For example, as shown in FIG. 5, in step 50 of the microgram, when a jump instruction jft is executed, first, a jump flag f indicated by the instruction is executed.
It is determined whether the value of 0 is “1”. Here, if the value of the flag f0 is “1”, the micros corresponding to the flag f0 included in the range (R in the drawing) from the next step (in this case, step 51) to the jump step 70 indicated by the instruction. All write instructions of the gramogram are invalidated. On the other hand, in the case of the jump instruction jff, when the value of the jump flag indicated by the instruction is “0”, all the write instructions up to the jump step specified by the instruction are invalidated.

That is, when the program decoder 22 decodes the jump instruction jft (jft = 1), the data of the jump step specified by the instruction jft is supplied to the jump step register 24, and the data is stored. At this time, the value "1" is supplied to the first input terminal of the AND gate 27, and the flag select signal specifying the jump flag stored in the same step of the microprogram including the jump instruction jft is sent to the flag register 23. Supplied to

Here, for example, if the jump flag f0 is specified by the select signal and the flag value is "1", the value "1" is supplied to the second input terminal of the AND gate 27, and As a result, the output of the AND gate 27 becomes the value “1”. As a result, the output of the OR gate 28 has the value “1”, and the output of the OR gate 29 has the value “1”. Then, the output value “1” of the OR gate 29 passes through the delay circuit 30 to the second value of the AND gate 31.
It is supplied to the input end.

On the other hand, when the output of the OR gate 28 becomes "1", the data of the jump step stored in the jump step register 24 is supplied to the comparator 25. The comparator 25 compares the jump step data supplied from the jump step register 24 with the count value of the program counter 26 that counts the progress of the steps of the microprogram based on the clock signal φ. Outputs a value "0", and outputs a value "1" when they match.

That is, the output of the comparator 25 has the value "0" from the time when the step of the jump instruction jft is executed to the time when the execution step proceeds to the jump step.
This is inverted by the inverter 32, and the value “1” is supplied to the first input terminal of the AND gate 31. As a result,
The output of the AND gate 31 takes the value “1”, which is inverted by the inverter 33 and the first
The value "0" is supplied to the input. As a result, the write command WR output from the program decoder 22 to the effect applying unit 91 is invalidated until the execution step proceeds to the jump step.

When the execution step proceeds to the jump step, the output of the comparator 25 takes the value "1".
The value "0" is supplied to the first input terminal of the ND gate 31, whereby the output of the AND gate 31 becomes the value "0",
A value “1” is supplied to a first input terminal of the AND gate 34. As a result, the invalidity of the write command WR is released, and thereafter, the write command WR becomes valid.

On the other hand, when the program decoder 22 decodes the jump instruction jff, the value of the jump flag is supplied to the AND gate 36 via the inverter 35, so that the flag value serving as the jump condition is changed to the jump instruction jft. Is the reverse of the case. That is, since the jump instruction jft and the jump instruction jff can be selectively used depending on the contents of the microprogram, the degree of freedom of the program is improved.

C: Overall Operation Next, referring to FIG. 1 again, the overall operation of this embodiment will be described. First, when the device is powered on, C
The PU 5 loads a control program from the ROM 6 and executes it. Thus, after performing various initialization processes, the CPU 5 scans each key of the keyboard 3 and various operators of the panel switch 1, and detects these operation events and operation states. Then, the CPU 5 outputs the tone control parameters to the sound source 9 according to the detection result, and outputs various control data such as a microprogram to the DSP 9.

Thus, the tone generator 9 generates a tone signal corresponding to the tone control parameter supplied from the CPU 5, and the DSP 9 converts the tone signal output from the tone generator 9 based on various control data supplied from the CPU 5. Adds various effects such as reverb, chorus, and distortion. The left and right two-channel tone signals to which the effect is added by the DSP 9 are converted to the D / A converter 1.
After passing through 0L and 10R, the sound system LSP, RS
It is pronounced from P. The above-described operation (excluding the initialization process) is repeated while the power is on.

D: Operation at Effect Change Next, the operation at the time of effect change according to this embodiment will be described with reference to FIG. First, when an effect change event occurs on the panel switch 1, the CPU 5
The effect change processing routine shown in FIG. 3 is started, and steps S1 to S15 of this routine are executed. Less than,
The processing of steps S1 to S15 performed by the CPU 5 will be described separately in the following (1) to (5).

(1) Falling-down processing of the effect before the change When the processing of the CPU 5 proceeds to step S1, the coefficients for determining the wet / dry balance of the effect to be changed become wet = 0 and dry = 1. Set to.
At this time, the interpolation circuit 14 performs interpolation between the coefficient value set up to then and the newly set coefficient value (in this case, wet = 0, dry = 1) according to a predetermined interpolation rate, Wet / dry balance gradually changes. Thereby, the effect to be changed is faded out.

When the process proceeds to step S2, the effect to be changed is completely faded out, and a time wait is performed until the wet / dry balance becomes wet = 0 and dry = 1.

Next, in step S3, the value f0 of the flag register 23 corresponding to the effect to be changed is inverted from "0" to "1". Thereby, the write command WR based on the microprogram corresponding to the effect to be changed is invalidated.

(2) Program Change Processing Next, when the process proceeds to step S4, a microprogram corresponding to the effect given after the change is loaded from the ROM 6, and the microprogram corresponding to the effect to be changed is stored. Overwrites the area of the existing microprogram register 21. At this time, the address register 1 used when the microprogram is executed is
9 and the contents stored in the coefficient register 15 are also rewritten to contents corresponding to the effect given after the change.

Next, at step S5, the value f0 of the flag register 23 corresponding to the effect to be changed is inverted from the value "1" set at step S3 to the value "0". As a result, the invalidity of the write command WR set in step S3 is released, and the write command WR based on the microprogram corresponding to the effect given after the change is executed.

(3) Data Register Clearing Process Next, proceeding to step S6, it is determined whether or not the data register 12 needs to be cleared with the change of the effect. That is, when the data register 12 is used as an area for storing the delay element in the filtering process performed to give the effect to be changed, the area needs to be cleared.

If the data register 12 needs to be cleared, the result of the determination in step S6 is "Ye
s ", and proceeds to steps S7 and S8. Step S
In steps S7 and S8, the filter input is set to "0" in order to clear the delay element stored in the data register 12.
A predetermined coefficient value is written to the coefficient register 15. And
In step S9, after time-waiting until the delay element stored in the data register is cleared,
Proceed to step S10.

That is, in the effect to be changed, for example, when the processing corresponding to the primary digital filter shown in FIG.
In order to clear the delay element stored in 2, the filter input is set to "0" and the multiplier coefficient is set to "1". Thereby, the filter output becomes “0” by at least one sampling, and the delay element is cleared.

In the effect to be changed, for example, when a process corresponding to the secondary digital filter shown in FIG. 4B is performed, the filter input is cleared in order to clear the delay element of the data register 12. “0” and the multiplier coefficient are “1”. This allows at least two
The filter output becomes “0” by the sampling of the number of times, and the delay element is cleared.

On the other hand, if the data register 12 is not used in the filter processing performed to give the effect to be changed, it is not necessary to clear the data register 12, and the result of the determination in step S6 is "No". Then, the process directly proceeds to step S10 without performing the process of clearing the data register 12.

(4) Processing for Clearing Delay RAM 18 Next, when the process proceeds to step S10, it is determined whether or not the delay RAM 18 needs to be cleared in accordance with the change of the effect. That is, if a predetermined area of the delay RAM 18 is used at the time of executing the microprogram corresponding to the effect to be changed, it is necessary to clear the area.

Then, with the effect to be changed, the delay RA
If the area of M18 has been used, the determination result of step S10 is "Yes", and the process proceeds to step S11.
In step S11, the used delay RAM 1
Clear area 8 Then, in step S12, after time-waiting until the clearing process of the delay RAM 18 is completed, the process proceeds to step S13.

Here, when the DSP 9 has a function of clearing the memory at a high speed, the time wait processing in the step S12 is unnecessary.
It is necessary to clear the input by setting the input to "0" and time-waiting for a time corresponding to the delay time.

On the other hand, a delay RAM
If the area No. 18 is not used, the determination result of step S10 is “Yes”, and the process directly proceeds to step S13 without performing the processing of clearing the delay RAM 18.

(5) Effect start-up processing after change In step S13, since the clearing coefficient is set in the coefficient register 15 in the above-described clearing processing of the data register 12 (step S8), the effect is applied again after the change. The coefficient corresponding to the effect to be effected is stored in the coefficient register 15.
Write to.

Next, at step S14, the set value of the wet / dry balance of the effect applied after the change is set from the wet / dry balance (wet = 0, dry = 1) set at step S1. Set the interpolation rate when shifting to.

Then, in step S15, the interpolation circuit 1
In step 4, interpolation is performed according to the interpolation rate set in step S14, and the wet / dry balance gradually matches the set value of the effect provided after the change. Here, the set value of the interpolation rate and the set value of the wet / dry balance are stored in the RAM 7 as effect parameters.

The above-described operation is performed every time an event of an effect change occurs in the panel switch 1.

E: Conclusion As described above, according to the present embodiment, while the effect for which switching is instructed is faded out and removed from the output sound, the switching is instructed among a plurality of effects currently being given. The program for providing the effect is rewritten to a program for providing a new effect after switching.
At this time, since a data write operation due to the execution of the program being rewritten is avoided, it is possible to prevent a malfunction such as destruction of a data storage area accessed at the time of execution of a program corresponding to another effect that is not switched. it can.

F: Application Example In this embodiment, the wet / dry balance of the switched sound effect is set to wet = 0 and dry = 1 to completely remove the sound from the output sound. However, the present invention is not limited to this. The wet / dry balance may be set at any ratio as long as the noise due to the switching is negligible, for example, wet = 0.2 and dry = 0.8.

In the above-described embodiment, the effector that gives an effect to a given tone signal has been described as an example. However, the present invention is not limited to such an effector field, and performs signal processing by executing a plurality of programs. Then, the present invention can be applied to other devices. That is, even when applied to another signal processing device, by changing a program while avoiding a write instruction during a program change, a normal signal processing is performed without adversely affecting the execution of another program. be able to.

[0060]

As described above, according to the present invention, execution of a rewritten program destroys a data storage area accessed when another program not instructed to be changed is executed. Since malfunction can be prevented, the program can be changed while normal signal processing is performed without adversely affecting the execution of another program not instructed to change. Further, according to the present invention, it is not necessary to provide a transfer buffer or the like in order to collectively rewrite the steps of the program in order to avoid a malfunction at the time of switching, so that the device configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a DSP according to the embodiment.

FIG. 3 is a flowchart showing an effect change processing routine of a control program executed by a CPU 5 in the embodiment.

FIG. 4 is a block diagram showing an example of effect filter processing according to the embodiment; FIG. 4A shows a first-order digital filter, and FIG. 4B shows a second-order digital filter;

FIG. 5 is a conceptual diagram showing an operation when a write instruction of a microprogram is invalidated by execution of a jump instruction in the embodiment.

[Explanation of symbols]

1 Panel switch 2 Panel interface
3 ... keyboard, 4 ... keyboard interface, 5 ... CP
U, 6 ROM, 7 RAM, 8 sound source 9, 9
DSP, 10L, 10R ... D / A converter, 11 ... Input register, 12 ... Data register, 13 ...
Arithmetic circuit, 14 ... interpolation circuit, 15 ... coefficient register,
16 LFO, 17 Latch circuit, 18 Delay R
AM, 19 ... address register, 20 ... address control circuit, 21 ... microprogram register, 22 ...
... program decoder, 24 jump step register, 25 comparator, 26 program counter
27, 31, 34, 36 ... AND gate, 28, 29
... OR gate, 30 delay circuit, 32, 33, 35
…… Inverter, LSP, RSP …… Sound system

Claims (5)

(57) [Claims] 1. A signal processing apparatus for repeatedly executing a plurality of programs consisting of various instruction steps in a time-division manner, wherein at least one of the plurality of running programs is to be executed after being changed. a program rewriting means for rewriting, during the rewrite operation by the program rewriting means, said
Write data contained in at least one program
Invalidation finger that generates instruction data for instructing instruction invalidation
And shows means in response to the instruction data of the deactivation instruction means, the less
And invalidating means for invalidating a data write command included in one program, wherein the at least one program has an invalidation control command in advance.
And the invalidation means responds to the instruction of the invalidation instruction means.
The at least one program includes
By activating the activation control command, the at least
Invalidate the data write instruction included in one program
A signal processing device characterized in that: 2. The program according to claim 2, wherein :
An invalidation control instruction is included, and the invalidation instructing means includes, among the plurality of programs,
Embedded in the program you are trying to rewrite
The instruction data to generate indicating the disabling control instruction was, the invalid
Means for invalidating the instruction indicated by the instruction data.
The signal of claim 1, wherein the signal is activated.
Processing equipment . (3) A series of predetermined number of microphones including branch instructions
B.
Micro instruction storage means for outputting; Decode microinstructions output by microinstruction storage means
Decoding means for outputting a control signal The arithmetic processing is performed according to the control signal corresponding to the arithmetic instruction.
Computing means, For storing various data including the calculation result by the calculation means
Data storage means used; Generates branch control data indicating valid or invalid
Ki instruction means, The decoding means decodes the first branch instruction, and
If the branch control data indicates valid,
Period up to the branch destination address corresponding to the first branch instruction
Only instructs data writing to the data storage means.
First branch control means for invalidating the control signal to be commanded.
A signal processing device comprising: (4) The signal processing device according to claim 3.
hand, Further, the decoding means decodes the second branch instruction.
And the branch control data indicates invalid, the
From the time of the branch destination address corresponding to the second branch instruction
Data written to the data storage means only during
Second branching system for invalidating the control signal for instructing writing
A signal processing device comprising control means. (5) A series of a predetermined number of
Micro instructions are stored and each micro instruction is cycled.
Micro-instruction storage means for cyclically outputting; Decode microinstructions output by microinstruction storage means
Decoding means for outputting a control signal The arithmetic processing is performed according to the control signal corresponding to the arithmetic instruction.
Computing means, For storing various data including the calculation result by the calculation means
Data storage means used; Multiple branch control data, each indicating valid or invalid
Branch instructing means for generating data; The decoding means detects any one of a plurality of branch instructions.
Branch instructions and decode the plurality of branch control instructions.
The branch control corresponding to the decoded branch instruction
If the control data indicates validity, the deco
The period up to the branch destination address corresponding to the loaded branch instruction
Write data to the data storage means only during
Branch control means for invalidating the control signal to be commanded.
A signal processing device comprising: