JPS588011B2 - Microprogram Seigiyohoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system often used in small electronic computers such as minicomputers.

To branch to each processing routine of the macro instruction when executing the macro instruction by the microprogram, use ■R.
A method of providing a decoder (ROM) that is accessed by the operation code section of the decoder, temporarily transferring the address read from the decoder to the MPC, and then reading the microprogram for executing the macro instruction from the memory. Or, jump to the memory address indicated by the operation code part of the macro instruction, and then jump to the microprogram address to execute the macro instruction written at that address. There are several ways to do this, but the former method requires a separate decoder, and the latter requires two steps to actually execute the macro instruction, which slows down the processing speed.

The present invention has been made to improve these difficulties, and
A detailed description will be given below with reference to the drawings.

In the figure, 1 is an IR into which macro instructions are introduced, and 2 is a memory in which microprograms are stored, which is comprised of a ROM.

3 is an MBR that temporarily stores the microprogram read out from the memory 2; 4 is a signal generation circuit that generates various control signals based on the contents of the register; 5 is an access address of the memory 2; In the specified MPC, the MPC
The contents of 5 and at least the operation code portion of IR1 are applied to the memory 2 as an address input to the memory 2 as appropriate by a switching circuit 6 that switches based on a signal from the signal generating circuit 4.

Also, the content read from the memory 2 is MMB3.
At the same time, the signal is directly introduced into the MPC 5 via the gate 7 which opens and closes depending on the signal from the signal generating circuit 4.

Gate 1 opens because the operation code part of the macro instruction in IR1 is used as the address input to memory 2, and the contents stored at the address in memory 2 corresponding to the operation code part are read out from memory 2. Only when you come.

Note that the memory address 2 specified by the operation code section of the macro instruction contains only the starting address of the microprogram for executing the process corresponding to the operation code section.

When the macro instruction to be executed is introduced into IR1,
The switching circuit 6 switches to the IRI side, the operation code section of the macro instruction becomes the address input to the memory 2, and the memory 2 is accessed.

Since only the start address of the microprogram for executing the macro instruction is written in the memory 2 address accessed at this time, the start address is transferred to the MPC5 via gate 7 and switched to the MPC5 side. The contents of the MPC 5, that is, the starting address of the microprogram for executing the macro instruction, are applied to the memory 2 as an address input to the memory 2 through the switching circuit 6, and the microprogram for executing the macro instruction is accessed. ,
The data is read out to the MBR 3 and applied to the signal generation circuit 4 to generate a signal for executing the microprogram, and at the same time, the contents of the MPC 5 are incremented by 1 to sequentially access the microprogram.

As is clear from the above description, when branching to each processing routine of a macro instruction, the present invention directly accesses the address where the start address of the microprogram for executing that instruction is introduced in the operation code section of R. At the same time, the first address read by the access operation is applied directly to the MPC, so there is no need to provide a separate decoder and execution of macro instructions can be executed in one step, increasing processing speed. It is.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration when implementing the method of the present invention, in which 1 is an IR, 2 is a memory, 3 is an MBR, 4 is a signal generation circuit, 5 is an MPC, 6 is a switching circuit, 7 is a gate, are shown respectively.

Claims (1)

[Claims] 1. An instruction register (hereinafter referred to as IR) into which macro instructions are introduced, a memory in which microprograms are stored, and a memory buffer register (hereinafter referred to as MBR) in which the microprograms read from the memory are temporarily stored. (abbreviated)), a signal generation circuit that generates various control signals based on the contents of the register, and a microprogram counter (hereinafter abbreviated as MPC) that specifies the access address of the memory. The operation code section of the IR and the contents of the MPC are switched as appropriate by the signal from the signal generation circuit, and serve as address inputs to the memory, and the address of the memory accessed by the operation code section of the IR is stored in the operation code section. Introduce the starting address of the microprogram to execute the corresponding process, and set the starting address read from the memory only when the operation code section of R accesses the memory as an address input.
A microprogram control method that is directly installed in a PC and sequentially reads and executes microprograms in memory according to the contents of the MPC.