JP3014839B2 - Pd ultrafine wires for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Pd ultrafine wire for a semiconductor device, more specifically, 0.1 mm for wire bonding or bump electrode for connecting an electrode on a semiconductor chip to an external lead.
It relates to an ultrafine Pd wire of φ or less.

[0002]

2. Description of the Related Art Conventionally, as a wire bonding wire for a semiconductor element of this type, for example, a tip of an Au wire hanging down from a tip of a capillary is melted by an electric torch to form a ball, and the ball is formed on a chip electrode of the semiconductor element. There is a type in which a chip electrode and an external lead are connected by bonding to the external lead in a loop shape, bonding the chip electrode to the external lead, and pressing and cutting the external lead.

[0003]

However, such a conventional Au wire for bonding has a very high purity Au wire.
(99.99% by weight or more), the high-temperature tensile strength is low, and when the resin is sealed after bonding, there is a problem that a wire (Au wire) is caused to flow by the resin to cause a short circuit. . On the other hand, in recent years,
It is required to keep the loop height as low as possible with the reduction in thickness of the SI package. However, the conventional Au wire has a low high-temperature tensile strength, and if a low loop is forcibly attempted to be stretched, the wire breaks. Was not satisfied.

Furthermore, when used for bump electrodes, the conventional Au wire has a problem that the cutting position (neck cutting position) immediately above the ball varies and the bump height is not constant.

In view of the above circumstances, the present invention has found that it is useful to add a predetermined element to Pd. The object of the present invention is to provide a Pd ultrafine wire which can reduce the loop height at the time of operation (low loop) and, when used for bump electrodes, keep the bump height constant to improve the durability and reliability of the semiconductor device. And

[0006]

According to the present invention, the ultrafine Pd wire for a semiconductor device according to the present invention has a high purity Pd or a Pd alloy having a boiling point lower than the melting points of these base materials. P
d to 25 to 10,000 atppm and Zr,
3. The method according to claim 2, wherein one or more of Y, rare earth elements, Ca, Sr, and Hf are contained at 10 to 200 at ppm.
According to the method, a low-boiling element having a boiling point lower than the melting point of these base materials and not forming a solid solution with Pd is added to high-purity Pd or a Pd alloy.
From 5 to 500 atppm and Zr, Y, rare earth element, Ca, S
According to claim 3, one or two or more of r and Hf are contained in the high purity Pd or Pd alloy having a boiling point lower than the melting point of these base materials.
The low-boiling element I which forms a solid solution with d and the low-boiling element II which does not form a solid solution with Pd have their contents Ia and IIa,

(Equation 2) 5 to 10,000 atppm and one or more of Zr, Y, rare earth elements, Ca, Sr, and Hf under 10 to 200a
It is characterized by containing tppm.

The high-purity Pd contains unavoidable impurities.
99.9% or more, and Pd alloy is Pd with Au
(10 at% or less), Ag (5 at% or less), Pt (20 at% or less), Rh (8 at% or less), Ru, Os, Ir (1 at%)
The following), one containing one or more selected from Cu, Mo, Fe, etc. is used. The low-boiling element I having a boiling point lower than the melting point of the base material and forming a solid solution with Pd is, for example, Zn, Cd, Hg, Li, Mg, Sb, Te, Bi, Y
The low-boiling element II having a boiling point lower than the melting point of the base material and not forming a solid solution with Pd is, for example, P, S, As, Tl or the like.

[0008]

The reason for limiting each component in the Pd ultrafine wire for a semiconductor device will be described. Low-boiling elements having a boiling point lower than the melting point of the base material evaporate and scatter from the melted ball during ball formation, but cannot evaporate from the neck, but tend to vaporize and produce stress, and among them, form a solid solution with Pd The low-boiling element I is difficult to escape from Pd and its content cannot be satisfied if its content is less than 25 atppm. On the other hand, if it is more than 10,000 atppm, the embrittlement phenomenon of the busbar is observed, so that the wire drawing becomes difficult, When forming the ball, the amount remaining in the ball without scattering increases, and the ball becomes too hard, which may cause chip cracking during bonding.

The low-boiling element II which does not form a solid solution with Pd is P
When the content is less than 5 atppm, the properties cannot be satisfied. On the other hand, when the content is more than 500 atppm, the embrittlement phenomenon of the bus is observed, so that the wire drawing becomes difficult and the ball is not scattered in the ball. 5 to 50 as the amount of residue on the ball increases and the ball becomes too hard, causing chip cracking.
0 atppm.

The lower limit of the total content of the low-boiling element I which forms a solid solution with Pd and the low-boiling element II which does not form a solid solution with Pd is defined as Ia and IIa.

(Equation 3) If the content is less than 5 atppm under the above condition, the characteristics cannot be satisfied. on the other hand,
The upper limit of the total content of the low-boiling element I which forms a solid solution with Pd and the low-boiling element II which does not form a solid solution with Pd is determined by setting the contents to I
a, IIa,

(Equation 4) In the condition of 10000atppm or more, since the embrittlement phenomenon of the busbar can be seen, the wire drawing becomes difficult,
Since the amount remaining without scattering in the ball increases and the ball becomes too hard and causes chip cracking, the content is set to 10,000 atppm under the above conditions.

The high-purity Pd or Pd alloy contains 25 to 10,000 atppm of a low-boiling element having a boiling point lower than the melting point of the base material and forming a solid solution with Pd, or a low-boiling element not forming a solid solution with Pd. Or low-boiling element I and low-boiling element II in their content I
a, IIa,

(Equation 5) Under the conditions described above, a low boiling point element in the ball is evaporated and scattered during the formation of the ball, thereby preventing the absorption of gas peculiar to the metal, thereby obtaining a good ball for joining and forming the ball in the neck portion. The low-boiling elements cannot evaporate, but generate stress due to vaporization, and the breaking strength of the neck part is improved compared to the bus bar where no stress is generated. Does not occur.

The above-mentioned additional elements Zr, Y and rare earth elements (L
a, Ce, Pr, and other elements with atomic numbers 57 to 71), Ca, S
The atomic radii of r and Hf are 1.15 times or more the atomic radius of the base material Pd (1.37 angstroms) or more, and when added to the base material Pd, the crystal lattice of the Pd alloy is greatly distorted. It has the property of increasing strength, especially breaking strength and high temperature tensile strength, and is therefore effective in suppressing wire flow during resin sealing. In addition, Z
r, Y, rare earth elements, Ca, Sr, and Hf refine the crystal grains in the neck portion during ball formation, and improve the breaking strength and high-temperature strength of the neck portion due to a synergistic effect with the addition of a low boiling point element. Therefore, it is possible to reduce the loop of the wire and to stabilize the neck breaking position when forming the bump. However, this Zr, Y, rare earth element, Ca, S
When the content of one or more of r and Hf is less than 10 atppm, the loop height of the wire is set to a desired value (170 μm).
), And the required effects such as inconsistent neck break position during bump formation cannot be obtained.
In the case of exceeding, the workability at the time of wire drawing becomes too hard and the workability at the time of wire drawing deteriorates, and the ball becomes too hard at the time of ball formation, causing adverse effects such as chip cracking. 200atppm.

[0013]

EXAMPLES Examples of the present invention will be described with reference to the case where the bus is a high-purity Pd line.
o. 1 to 102 Pd lines were prepared. Each sample was melt-cast with its composition (including unavoidable impurities), then subjected to groove roll processing, annealed in the middle, and then drawn into a bus having a wire diameter of 25 μm by wire drawing. Further sufficient stress removal was performed.

[0014]

[Table 1]

[0015]

[Table 2]

[0016]

[Table 3]

In Tables 1 to 3, the additive elements Zn, C
Although d and Hg are a part of the low-boiling element I shown above, and the additional elements P and S are a part of the low-boiling element II shown above, the other exemplified elements have the same tendency. Are omitted. The addition amount of low boiling elements I and II is 25 to 10,000 atp.
pm or 5-10000 atppm, but the characteristics in the above range for Pd are described in the earlier application of the present applicant (Japanese Patent Application No. 2-146499).
And the additive element Z in the above range.
Since the characteristics for r, Y, rare earth elements, Ca, Sr, and Hf tend to be the same, the case of low-boiling element I in the above range is 500 atppm, and the case of low-boiling element II is 5 at ppm.
The case of 0 atppm was used as an example. The sample No. 101
Is high purity (99.99%) without adding the low boiling elements I, II and Zr, Y, rare earth elements, Ca, Sr and Hf.
Pd line, sample No. 102 is high purity (99.999%) Au
It is a comparative example showing the case of a line.

Each sample was tested for breaking strength, high-temperature tensile strength (related to wire flow), drawability, loop height, presence or absence of chip cracking, and stability of neck breaking. The loop height is a value obtained by measuring the distance from the semiconductor chip to the top end of the loop as a result of bonding each sample to the electrodes of the semiconductor chip and the external leads in a loop by a ball bonding method. The high-temperature tensile strength was measured at 250 ° C for each sample with a gauge length of 100 mm.
This is the value of the breaking strength obtained by performing a tensile test in the temperature atmosphere after holding for 0 second. The presence / absence of chip cracking was measured by measuring a predetermined number of samples of each sample at the rate at which cracks occurred in the chips when the balls were formed and bonded to a semiconductor chip by thermocompression bonding. The stability of neck breaking was determined by subjecting each sample to a semiconductor chip by thermocompression bonding, pulling up and cutting the ball, and measuring the height from just above the ball to the cutting position (neck height). As a result of the measurement, a case where the variation in the neck height is ± 10 μm or less is regarded as stable.
Each mark is marked with a mark, and the case exceeding the mark is marked as unstable with a mark x. The measurement results of the above test are shown in Tables 4 to 6 below.

[0019]

[Table 4]

[0020]

[Table 5]

[0021]

[Table 6]

As is clear from Tables 4 to 6, one or more of Zr, Y, rare earth elements, Ca, Sr, and Hf are added to 10
According to the product of the present invention to which -200 atppm was added, as compared to the comparative product (sample Nos. 101 and 102) on the assumption that there is no adverse effect on the wire drawing processability at the time of wire production and no chip cracking at the time of bonding. It was confirmed that the high-temperature tensile strength was sufficiently improved to suppress wire flow, that the loop height was formed to less than the desired 170 μm, and that the neck break position was stable. Is done.

Next, when the bus is Pd, the Au, Ag, Pt,
The case of a Pd alloy to which Rh or the like has been added will be described.
An example of the Pd-Au alloy wire will be described with reference to FIG.

Samples Nos. 7 to 9 having the component compositions shown in Tables 7 to 9 below were used for the same reasons as in the above-mentioned Examples. 1 to 102 Pd-Au alloy wires were prepared.

[0025]

[Table 7]

[0026]

[Table 8]

[0027]

[Table 9]

Tables 10 to 12 show the results of tests on the above-mentioned samples for the breaking strength, high-temperature tensile strength, drawability, loop height, presence / absence of chip cracking, and bonding characteristics of neck break stability.

[0029]

[Table 10]

[0030]

[Table 11]

[0031]

[Table 12]

From Tables 10 to 12, as in the above-described embodiment,
According to the product of the present invention, the comparative product (sample No. 101, 1
02), it was confirmed that the high-temperature tensile strength was sufficiently improved and the wire flow was suppressed, and that the loop height was formed to be less than the desired 170 μm and that the neck breaking position was stable. Is confirmed.

[0033]

According to the present invention, in addition to low boiling elements I and II, Z
one or two of r, Y, rare earth element, Ca, Sr, Hf
Since a predetermined amount or more of the seed is contained, the breaking strength and high-temperature tensile strength of the Pd wire are strengthened, the wire flow during resin sealing is suppressed, and the loop during bonding can be reduced, and the bump during forming the bump can be formed. Since the position where the neck is cut is fixed, the bump bonding is reliably and stably performed.

Therefore, it is possible to provide a Pd ultrafine wire for a semiconductor element, which is useful for improving the durability and reliability of the semiconductor device and reducing the thickness of the LSI package by reducing the loop.

Claims (3)

(57) [Claims] 1. A high-purity Pd or Pd alloy containing 25 to 10,000 atppm of a low-boiling element I having a boiling point lower than the melting point of these base materials and forming a solid solution with Pd and Zr, Y, rare earth element, Ca,
A Pd ultrafine wire for a semiconductor element, wherein one or more of Sr and Hf are contained at 10 to 200 atppm. 2. A high-purity Pd or Pd alloy containing 5-500 atppm of a low-boiling element II having a boiling point lower than the melting point of these base materials and not forming a solid solution with Pd, and Zr, Y, rare earth elements, Ca,
A Pd ultrafine wire for a semiconductor element, wherein one or more of Sr and Hf are contained at 10 to 200 atppm. 3. A high-purity Pd or Pd alloy containing a low-boiling element I having a boiling point lower than the melting point of the base material and forming a solid solution with Pd and a low-boiling element II not forming a solid solution with Pd. , IIa, 5 to 10,000 atppm and one or more of Zr, Y, rare earth elements, Ca, Sr, and Hf under 10 to 200a
An ultrafine Pd wire for a semiconductor device, characterized by containing tppm. .