JP3016342B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a MOSFET (Metal Oxide Semiconductor).
r Field Effect Transistor).

[0002]

2. Description of the Related Art As MOSFETs are miniaturized, phenomena such as a decrease in threshold voltage due to a short channel effect, a decrease in punch-through breakdown voltage, and an increase in S coefficient occur, resulting in a problem of an increase in leak current. ing. One of the causes of this problem is that the miniaturization of the MOSFET is performed only in the horizontal direction with respect to the substrate, but not in the depth direction. Therefore, MO
In accordance with the miniaturization of the SFET, it is necessary to reduce the depth of the source / drain diffusion layer near the gate electrode (form a shallow pn junction), and also to miniaturize in the depth direction.

The conventional method of forming a source / drain diffusion layer is a method in which impurity ions are implanted and then heat treatment is performed to activate the impurity ions.
Since it is difficult to form an n-junction, a formation method by solid phase diffusion has been studied. As a diffusion source for solid-phase diffusion, when diffusing n-type impurities, PSG (phospho-silicon) is used.
When a p-type impurity is diffused, BSG (boro-silicate glass) is often used (eg, cate glass) film (for example, 30p-ZG-12, Spring Meeting of the Japan Society of Applied Physics, 1994).
A method using a boron penetration effect in which a film or a polysilicon film doped with boron at a high concentration is formed on a thin oxide film and then subjected to a heat treatment (for example, Spring Meeting of the Japan Society of Applied Physics in 1994, 29p-ZG-9, etc.) ) Are being considered.

[0004] By using this solid phase diffusion, a shallow pn junction can be formed.
CMOS integrated circuit (L
SI), an n-type MOSFET and a p-type M
It is necessary to devise a method of separately producing the OSFET. 13 (A) to 13 (C) and FIGS. 14 (A) to 14 (D) show a conventional method of manufacturing a CMOS LSI in consideration of the above.
It is explained together with.

[0005] First, as shown in FIG. (A), p made of silicon ^- by introducing n-type impurities into a portion of the substrate 1 n ^-
Forming a well 2, p ^- substrate 1 surface p ^- substrate 1 and the n ^-
A field oxide film 3 is formed at a boundary portion between the well 2 and electrically isolated, and a gate oxide film 4 and a gate electrode 5 are formed on the respective regions 1 and 2. The manufacturing steps up to this point are the same as those of a CMOS
This is the same as the LSI manufacturing process.

Next, as shown in FIG. 1B, in order to form a source region 8 and a drain region 9 of the p-type MOSFET in the n ^- well 2, a portion (p ^- substrate) where an n-type MOSFET is formed is formed. After forming a Si ₃ N ₄ insulating film 6 on (1) above, a BSG film 7 which is a diffusion source containing a p-type impurity is entirely formed. Then, by performing heat treatment, BS
The p-type impurity is diffused only in a portion where the G film 7 is in direct contact with the n ^- well 2, and a source region 8 and a drain region 9 which are p ⁺ regions are formed as shown in FIG.

[0007] Thereafter, as shown in FIG.
_After removing the ₃ N ₄ insulating film 6 and the BSG film 7, as shown in FIG. 4E, this time, a Si ₃ N ₄ insulating film is formed on the portion (on the n ⁻ well 2) where the p-type MOSFET is to be formed. After the film 10 is formed, a PSG film 11 which is a diffusion source entirely including an n-type impurity is formed. Further, when heat treatment is performed, P
An n-type impurity is diffused only in a portion where the SG film 11 is in direct contact with the p ⁻ substrate 1, and a source region 12 and a drain region 13 which are n ⁺ regions are formed as shown in FIG. Then, as shown in FIG. 2D, the CMO is removed by removing the Si ₃ N ₄ insulating film 10 and the PSG film 11.
SLSI can be manufactured. Note that n-type MOSF
The p-type MOSFET may be formed after forming the ET.

[0008]

In the above-described conventional manufacturing method, the heat treatment is performed to diffuse the p-type impurity of the BSG film 7, and then the n-type impurity of the PSG film 11 is diffused. Since the heat treatment is performed again, p
Type impurities diffuse again and spread more than necessary,
It was difficult to form a shallow junction at this part. Such a problem occurs not only in the case of a CMOS LSI but also in the case of a bipolar transistor. For example, in a case where npn or pnp transistors coexist, it occurs when each emitter region must be formed with a shallow junction.

Japanese Patent Laid-Open Publication No. Hei 4-188632 discloses a technique for solving such a problem. This technique uses polysilicon as a solid-phase diffusion source, and ion-implants impurities into the polysilicon. After the implantation, heat treatment is performed to diffuse impurities into the substrate. Then, at the time of ion implantation, a n-type MOSF
Although the diffusion source for the ET and the diffusion source for the p-type MOSFET are manufactured separately, this method can use only polysilicon as the diffusion source and uses other materials as the diffusion source. I couldn't. Therefore, an object of the present invention is to form a shallow pn junction in both an n-type region and a p-type region on the surface of a semiconductor substrate by a method using a solid-phase diffusion source that does not limit the material.

[0010]

According to another aspect of the present invention, there is provided a semiconductor device in which a pn junction is formed in each of the regions of a semiconductor substrate on which a first conductivity type region and a second conductivity type region are formed. A method of manufacturing a device, wherein a first film having a diffusion coefficient of an impurity smaller than a diffusion coefficient of the semiconductor substrate is formed on an entire surface of the semiconductor substrate, and
A second step of forming a second film made of an insulator or a semiconductor containing impurities of a second conductivity type over the entire surface of the first film, and leaving at least a portion on at least the second conductivity type region. A third step of removing the second film by using an insulating material containing a second conductivity type impurity, covering the first film and the second film formed on the surface of the semiconductor substrate. Alternatively, a fourth step of forming a third film made of a semiconductor and heat treatment are performed to diffuse impurities from the second film and the third film through the first film to the semiconductor substrate. It is another object of the present invention to provide a method for manufacturing a semiconductor device, comprising the steps of:

[0011]

In order to form a shallow pn junction in both the n-type region and the p-type region of the semiconductor substrate, when introducing p-type impurities and n-type impurities into the respective regions, conventionally, heat is separately applied. Since it had to be diffused, the impurity introduced first was further diffused by the subsequent thermal diffusion to form a shallow pn.
A bond could not be formed. According to the present invention, a shallow pn junction is formed in both the n-type region and the p-type region of the semiconductor substrate by simultaneously performing the thermal diffusion of the respective impurities.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. 1 (A) to 1 (E)
FIG. 2 is a process chart showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention, and is a view showing a cross section of the semiconductor device in each step.

First, as shown in FIG. 1A, an n ^- well 22 is formed by introducing an n-type impurity into a part of a p ^- semiconductor substrate 21 such as silicon. Then, as shown in FIG. 1B, a p-type insulating film (for example, a BSG film) or a semiconductor film (for example, boron-doped polysilicon) containing a p-type impurity (acceptor) is formed on the entire surface of the substrate 21. A diffusion source 23 is formed.

As shown in FIG. 1C, the p-type diffusion source 2 is left except for the p-type diffusion source 23 where a p ⁺ -type region is to be formed.
3 is removed, and an insulating film (for example, P) containing an n-type impurity (donor) is formed on the entire surface as shown in FIG.
An n-type diffusion source 24 such as an SG film or a semiconductor film (for example, phosphorus-doped polysilicon) is formed. Thereafter, for example, RTA (Rapid Thermal Anneal) at 1000 ° C., 3
When the impurity is diffused by performing a heat treatment for 0 second, the p ⁺ -type region 25 is formed on the surface of the substrate 21 as shown in FIG.
And n ⁺ -type region 26 can be formed simultaneously, and n ⁻
A shallow pn junction is formed between the well 22 and the p ⁺ type region 25 and between the p ⁻ semiconductor substrate 21 and the n ⁺ type region 26. At this time, the heat treatment is performed only once, so that either of the regions 25 and 26 does not become deep. Also,
The order of forming the p-type diffusion source 23 and the n-type diffusion source 24 may be reversed.

The p ⁺ type region 25 and the n ⁺ type region 26
When it is desired to form a portion where neither of them is formed, the p-type diffusion source 23 including the portion is removed, and then the n-type diffusion source 2 is formed.
4 is formed on the entire surface, and n
After removing the diffusion source 24, heat treatment is performed to diffuse the impurities. In this manner, as shown in FIG. 2, a portion where neither the p ⁺ type region 25 nor the n ⁺ type region 26 is formed can be formed.

Further, by forming an insulator or the like to the portion not forming both p ⁺ -type region 25 and n ⁺ -type regions 26, optionally set forming portion of the p ⁺ -type region 25 and n ⁺ -type region 26 can do. This embodiment is shown in FIGS.
This will be described together with (C). First, as shown in FIG. 1A, an n ^- well 22 is formed by introducing an n-type impurity into a part of a p ^- semiconductor substrate 21 such as silicon. Then, as shown in FIG. 3B, the p ⁺ -type region 25 on the surface of the substrate 21 is formed.
A film 27 that does not transmit impurities such as an insulator is formed in a portion where neither the n ⁺ type region 26 nor the n ⁺ type region 26 is formed.

Thereafter, as in the above-described embodiment, a p-type diffusion source 23 such as an insulating film or a semiconductor film containing a p-type impurity is formed over the entire surface of the substrate 21 to form a p ⁺ -type region. P-type diffusion source 23
Is removed. Further, an n-type diffusion source 24 such as an insulating film or a semiconductor film containing an n-type impurity is formed on the entire surface thereof,
When the heat treatment is performed, the p ⁺ -type region 25 is formed on the surface of the substrate 21 where the film 27 is not formed, as shown in FIG.
And n ⁺ -type region 26 can be formed.

In the case where the film 27 that does not allow impurities to pass through is a thick oxide film 28 such as a field oxide film, FIG.
It becomes as shown in. By the method described above, the p ⁺ -type region 25 and the n ⁺ -type region 26 can be formed at an arbitrary shallow place. However, if the p-type diffusion source (first film) 23 is formed first, Is also formed with an n-type diffusion source (second film) 24, so that impurities may diffuse through the contact surface between the p-type diffusion source 23 and the n-type diffusion source 24 during thermal diffusion. There is. In this case, as shown in FIG. 5, the n-type impurity of the n-type diffusion source (second film) 24 is supplied via the p-type diffusion source (first film) 23 formed earlier to the n ⁻ well 22 ( Diffusion into the substrate 21) may hinder the formation of the p ⁺ -type region 25 (pn junction). In order to solve this, as shown in FIG. 6, the thickness of the p-type diffusion source 23 as the first film may be made sufficiently large.

Further, even if the thickness of the first film is sufficiently large, there is a possibility that impurities diffusing between the first film and the second film reach the surface of the substrate 21 at the boundary surface of the first film. is there. That is,
As shown in FIG. 7A, a p-type diffusion source (first film) 23
If the boundary surface is positioned closer to the p ⁺ -type region 25 forming part of the oxide film 28 (d ₁ is small) is, n-type diffusion source in contact with the boundary surface n-type (second film) 24 Impurities may diffuse into the portion where p ⁺ -type region 25 is formed. Conversely, as shown in FIG. 7B, a p-type diffusion source (first film)
23 is located at a position close to the portion of the oxide film 28 where the n ⁺ -type region 26 is formed (small d ₂ ),
In some cases, the p-type impurity of the p-type diffusion source (first film) 23 diffuses into the n ⁺ -type region 26 formation portion via the p-type diffusion source (second film) 24.

As one method for solving these problems, as shown in FIG. 7C, the boundary surface of the p-type diffusion source (first film) 23 is formed by forming the p ⁺ -type region 25 forming portion and n ⁺ (D) where the horizontal distance from the mold region 26 formation portion is sufficiently far
₁ and d ₂ ). That is, the distance d ₁ is made larger than the distance over which the n-type impurity flowing from the second film diffuses in the first film during the heat treatment, and
A p-type impurity introduced from the membrane to increase the distance d ₂ than the distance to diffuse through the second layer.

As another method, the first film and the second film
May be completely separated from each other so that they do not contact each other (the contact surface is eliminated). A first method for realizing this is to remove a portion of the second film on the first film which is in contact with the boundary between the second film and the first film, as shown in FIG. In this manner, diffusion of the impurities can be prevented. This second film removing step is performed when removing the n-type diffusion source 24 as the second film in order to form a portion where neither the p ⁺ -type region 25 nor the n ⁺ -type region 26 are formed. What is necessary is just to remove the first film and the vicinity of the boundary surface thereof, without increasing the number of steps.

As a second method for completely separating the first film and the second film, as shown in FIG. 9, a p-type diffusion source (first film) 23 is formed, After removing the portion, a film 29 that does not transmit impurities such as an insulating film such as a nitride film or a semiconductor film is formed, and a p-type diffusion source including a boundary surface (first
The film 29 which does not allow impurities to pass through other portions except for the periphery of the film 23) is removed, and then the n-type diffusion source (second film) 24 is removed.
To form In the second method, the distance in the horizontal direction can be shortened instead of increasing the number of steps, and further miniaturization can be achieved. When the first method or the second method is used, since the first film and the second film are completely separated from each other, it is not necessary to increase the thickness of the first film.

Further, when the impurities of the diffusion sources 23 and 24 are easily diffused in the substrate 21 and the depths of the regions 25 and 26 become deeper than desired, as shown in FIG. By forming a thin film 30 in which impurities are unlikely to diffuse between the well 21 and the diffusion sources 23 and 24, the diffusion depth can be adjusted, and the regions 25 and 26 can be adjusted.
Can be made shallower. For example, since the diffusion coefficient of boron is smaller in a silicon oxide film than in a silicon substrate and diffusion is difficult, a silicon oxide of 100 A (angstrom) or less is provided between the p-type diffusion source 23 containing boron and the well 22. By forming the film 30, the p ⁺ type region 25 can be made shallow (a shallow pn junction is formed). The diffusion of boron through a thin silicon oxide film is called "boron penetration effect".
It is generally known as

A method of manufacturing a CMOS LSI using the method of manufacturing a semiconductor device of the present invention described above will be described.
This will be described briefly with reference to FIGS. 11, p made of silicon ^- by introducing n-type impurity n the part of the substrate 31 ^- to form a well 32, p ^- substrate 31 surface p ^-
A field oxide film 33 is formed at a boundary between the substrate 31 and the n ^- well 32 to electrically isolate the field oxide film 33, and a gate oxide film 34 and a gate electrode 35 are formed on the respective regions 31, 32. The manufacturing process up to this point is the same as the normal CMOS LSI manufacturing process.

Next, the p-type diffusion source 37 is formed thick and
^{A part of} the field oxide film 33 which is in direct contact with the surface of the p ^- substrate 31 is removed so that the surface of the well 32 is left, and an n-type diffusion source 41 is formed on the entire surface. After that, when heat treatment is performed to diffuse the impurities,
n ^- on both sides of the gate electrode 35 in the well 32 are formed a source region 38 and drain region 39 and p ⁺ region, p ^- on both sides of the gate electrode 35 of the surface of the substrate 31 is n ⁺ region A source region 42 and a drain region 43 are formed.

FIG. 12 shows a case where a boron-doped polysilicon 40 is used as a p-type diffusion source and a PSG film 44 is used as an n-type diffusion source. In this case, since a "boron penetration effect" is used to form a shallow p ⁺ region, a thin oxide film 36 is formed on the portion of the n ^- well 32 where the source region 38 and the drain region 39 are formed. Is formed. Since the oxide film 36 is usually formed by thermal oxidation, it is necessary to perform thermal oxidation before forming the PSG film 44. If the PSG film 44
Is formed as a first film, and the PSG on the n ^- well 32 is formed.
If the oxide film 36 is formed by thermal oxidation after the removal of the film 44, impurities (phosphorus) are diffused from the PSG film 44 during the thermal oxidation, and the impurities of the boron-doped polysilicon 40 are thermally diffused. In addition, there is a disadvantage that the phosphorus is further diffused and the source region 42 and the drain region 43 formed on the surface of the p ⁻ substrate 31 are deepened. Therefore, this oxide film 36 is desirably formed by performing a heat treatment in a step after the gate electrode 35 is formed.

[0027]

According to the method of manufacturing a semiconductor device of the present invention, a shallow pn junction is formed in both an n-type region and a p-type region on the surface of a semiconductor substrate by a method using a solid-phase diffusion source that does not limit the material. Therefore, the depth of the source / drain diffusion layer near the gate electrode can be reduced (a shallow pn junction is formed) in accordance with the miniaturization of the MOSFET. To solve the problem of an increase in leakage current due to phenomena such as a decrease in threshold voltage, a decrease in punch-through breakdown voltage, and an increase in S coefficient,
There is an effect that a high-density CMOS LSI can be manufactured.

[Brief description of the drawings]

FIGS. 1A to 1E are process diagrams showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a partially modified state of the first embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIGS. 3A to 3C are diagrams for explaining another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a diagram for explaining another example of the embodiment shown in FIG. 3 (C).

FIG. 5 is a diagram for explaining the features of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a diagram showing an improved example of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 7A and 7B are views for explaining features of the method for manufacturing a semiconductor device of the present invention, and FIG. 7C is a view showing an improved example thereof.

FIG. 8 is a diagram showing a first method of another improved example of the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a view showing a second method of another improved example of the method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a diagram for explaining an embodiment using the boron penetration effect of the method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a diagram for explaining a method of manufacturing a CMOS LSI using the present invention.

FIG. 12 is a diagram for explaining a method of manufacturing a CMOS LSI using the present invention.

13A to 13C are process diagrams showing a conventional example.

14A to 14D are process diagrams showing a conventional example.

[Explanation of symbols]

1,21,31 p ^- substrate 2,22,32 n ^- well 3,33 field oxide film 4,34 gate oxide film 5,35 gate electrode 6,10 Si ₃ N ₄ insulating film 7 BSG film (p-type diffusion source ) 8, 12, 38, 42 Source region 9, 13, 39, 43 Drain region 11, 44 PSG film (n-type diffusion source) 23, 37 p-type diffusion source (first film) 24, 41 n-type diffusion source (Second film) 25 p ⁺ type region 26 n ⁺ type region 27, 29 Film that does not allow impurities to pass through 28, 30, 36 Oxide film 40 Boron-doped polysilicon

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/225 H01L 21/8238 H01L 27/092

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device, wherein a pn junction is formed in each of the regions of a semiconductor substrate on which a first conductivity type region and a second conductivity type region are formed, the method comprising: Forming a first film smaller than the diffusion coefficient of the semiconductor substrate over the entire surface of the semiconductor substrate.
A first step and a second step of forming a second film made of an insulator or a semiconductor containing an impurity of a second conductivity type over the entire surface of the first film; A third step of removing the second film while leaving a part thereof, and covering the first film and the second film formed on the surface of the semiconductor substrate, removing impurities of a second conductivity type. A fourth step of forming a third film made of an insulator or a semiconductor including the semiconductor film, and performing a heat treatment so that impurities from the second film and the third film to the semiconductor substrate through the first film are formed. And a fifth step of diffusing the semiconductor device. 2. The semiconductor device according to claim 1, wherein the p-type region and the n-type region are electrically separated from each other.
A method of manufacturing a semiconductor device for forming an OSFET, comprising: forming a gate insulating film and a gate electrode in each of the regions of the semiconductor substrate; and forming a thermal oxide film on the n-type region; Forming boron-containing polysilicon over the entire surface of the semiconductor substrate; removing the polysilicon while leaving at least a portion on the n-type region; silicon containing phosphorus over the entire surface of the semiconductor substrate Forming an oxide film; and performing a heat treatment to diffuse boron and phosphorus from a portion of the polysilicon and the silicon oxide film in contact with the semiconductor substrate to the semiconductor substrate. Manufacturing method of a semiconductor device.