JP3028063B2 - Carrier phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier phase locked loop, and more particularly to a carrier phase locked loop for a demodulator for receiving a modulated wave used in a communication system having a large carrier frequency variation such as non-geostationary orbit satellite communications. About.

[0002]

2. Description of the Related Art In a satellite communication system which requires burst transmission in real time, such as voice, high-speed carrier phase synchronization is required for a burst signal transmitted from a ground station, satellite or terminal. . However, Doppler
An offset occurs in the carrier frequency due to shift, drift of the local oscillator on the transmitting side or on the satellite, etc., and this carrier frequency becomes an obstacle in establishing high-speed synchronization. Conventionally, the synchronization technique for the carrier frequency offset has established the synchronization by the method described below.

FIG. 3 shows a conventional first-order phase locked loop (hereinafter, referred to as a “first phase locked loop”).
FIG. 3 is a block diagram illustrating an example of a carrier phase synchronization circuit using a PLL. A voltage controlled oscillator (VCO) 20 that oscillates upon receiving a detection output signal and a control voltage that have undergone quasi-synchronous detection.
Are compared in phase in a phase comparator 17, and the output signal from the phase comparator 17 is input to a phase detector 18 to output phase error information. The phase error information is smoothed by the loop filter 19 and input to the voltage controlled oscillator 20 as a control signal.

The received signal has a carrier frequency offset Δω
(= 2πΔf), when a phase detector having a sine wave characteristic is used, the first-order nonlinear differential equation showing the response of the phase error θ _e (t) is dθ _e (t) / dT = Δω− K sin θ _e (t) (1) Here, K is a loop gain. At this time, in order for the phase of the carrier to be synchronized and to be in a steady state, d
θ _e (t) / dT = 0, and from equation (1), | Δω / K | = | 2πΔf / K | ≦ 1 (2) This is because the frequency offset Δf is
Locking is not performed in a range exceeding K / 2π. Increasing the loop gain K widens the range of carrier frequencies that can be captured, but increasing the loop gain cannot reduce the phase jitter of the reproduced carrier under low C / N operating conditions. Therefore, this primary PLL
However, there is a limit to the carrier frequency range that can be initially captured. 1
The carrier phase locked loop circuit using the next PLL can be realized with a simple circuit and does not require adjustment, so that an inexpensive demodulator can be provided. However, phase synchronization is achieved when the initial frequency error is outside the frequency pull-in range of the PLL as described above. There was a major drawback that you couldn't.

FIG. 4 is a block diagram showing an example of a carrier phase locked loop disclosed in Japanese Patent Application Laid-Open No. 5-41717, which realizes frequency pulling when a frequency error is large, which is a problem of the conventional carrier phase locked loop using PLL. FIG. When the frequency error is detected by the frequency error detection circuit 27 and the frequency error is larger than a predetermined value, the frequency error detection circuit 27, an automatic frequency control (hereinafter, referred to as AFC) loop filter 28, a sample hold circuit 29, a numerical control Oscillator 30, multiplier 21, low-pass filter 22, multiplier 2
3. An AFC loop is formed by the phase detector 24. On the other hand, when the frequency error becomes smaller than a predetermined value, the output control voltage of the AFC 28 is held by the sample / hold circuit 29, and the loop filter 25 and the numerical control oscillator 2
6. A PLL loop is formed by the multiplier 23 and the phase detector 24, and switching to the PLL operation is performed. This operation enables high-speed frequency tracking even if a large frequency error exists.

[0006]

In a conventional carrier phase locked loop circuit using a PLL, the AFC
And the PLL loop, it was possible to establish a high-speed frequency pull-in and establish a stable phase synchronization even when the frequency error is large. However, when a received signal such as a non-geostationary orbit satellite communication, particularly a low-orbit satellite communication has a large time variation of frequency detuning, the frequency error detected by the PLL varies with time. The operation of switching the loop only by itself becomes practically ineffective, and there are problems of high-speed frequency tracking and establishment of stable carrier phase synchronization.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed and stable carrier phase synchronization for a demodulator of a non-geostationary-orbit satellite communication system, particularly a communication system having a large time variation of frequency detuning in a received signal such as a low-orbit satellite communication. It is to provide a method and a circuit.

[0008]

In order to solve the above-mentioned problems, the present invention has the following means as a carrier phase synchronization method of the present invention.

In a carrier phase synchronizing circuit for reproducing a carrier from an input signal, a multiplier for an automatic frequency control loop for multiplying the input signal by an output of a first voltage controlled oscillator to suppress a frequency error, and the automatic frequency control loop A multiplier for a carrier phase locked loop that multiplies the output of the multiplier for use with the output of the second voltage controlled oscillator to regenerate a carrier, and a phase detector that obtains phase error information from the output of the multiplier for the carrier phase locked loop. Receiving the output of the phase detector,
A second loop filter that outputs a control voltage for controlling the voltage-controlled oscillator of the first embodiment, and a first loop filter that receives an output of the second loop filter and outputs a control voltage for controlling the first voltage-controlled oscillator. is composed of a, calculates a temporal change amount of the output of the second loop filter, wherein
Control generated based on the judgment result of the magnitude of time change
Control means for inputting a signal to first and second loop filters to control a loop band, a frequency control width, and a control time interval of the automatic frequency control loop and the carrier phase locked loop are provided.

[0010] Further, the control means may control the second loop.
A delay element for delaying a filter output unit time, the second
And from the loop filter output of the second subtracter for subtracting the unit time delayed signal, and a filter for averaging the output signal of the subtractor is a variation per unit time of the frequency error, the averaged frequency error It is constituted by a data discriminator which discriminates a change amount per unit time and generates a control signal of a loop band, a frequency control width, and a control time interval of the automatic frequency control loop and the carrier phase locked loop.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a carrier phase synchronization circuit according to an embodiment of the present invention. The components of the carrier phase locked loop circuit are used in a satellite communication for transmitting a digitally modulated PSK signal, especially in the carrier frequency due to a Doppler shift and a drift of a local oscillator of a transmitter of a satellite earth station or a local oscillator of a satellite body. A circuit that establishes carrier phase synchronization in real time processing at high speed and over a wide frequency range when a large offset exists.

The configuration comprises a first low-pass filter (LPF) 1 for removing harmonic components of an input quasi-synchronous quadrature signal.
An analog / digital (A / D) converter 2 for sampling a quasi-synchronous quadrature signal passed through the LPF 1; a sampling clock oscillator 3 for supplying a sampling clock to the A / D converter 2; The first numerically controlled oscillator (N
A first complex multiplier 4 for performing frequency conversion by complex-multiplying the frequency of the sampling signal sampled by the A / D converter 2 with a signal output by the first NCO 5; A second LPF 6 for limiting the frequency-converted signal of the complex multiplier 4 in the Nyquist band;
A memory 7 for storing data information necessary for the filtering operation of the LPF 6; a second NCO 9 whose oscillation frequency is controlled by a control value from the PLL filter 11; a frequency of a signal whose Nyquist band is limited by the second LPF 6 A second complex multiplier 8 for performing frequency conversion by performing complex multiplication with a signal output from the second NCO 9; and performing phase detection on the signal whose frequency has been converted by the second complex multiplier 8 to obtain phase error information. A phase detector 10 for outputting; a PLL filter 11 for smoothing phase error information output from the phase detector 10; a first NCO from the smoothed phase error information.
AFC12 that outputs a control value for controlling the oscillation frequency of 5
A delay element 13 for delaying the smoothed phase error information by a unit time; and a subtracter 14 for subtracting the smoothed phase error information delayed by a unit time by the delay element 13 from the smoothed phase error information. A filter 15 for averaging the variation of the phase error per unit time, which is the output of the subtractor 14, and a data discrimination of the variation of the phase error per unit time averaged by the filter 15, and the AFC 12 and the PL
A data discriminator 16 for generating a control signal for controlling the L filter 11;

The quasi-synchronous quadrature input signal has its harmonic components removed by the first LPF 6, and the carrier frequency offset due to the Doppler shift or the drift of the local oscillator on the transmitting or receiving side of the satellite earth station or the local oscillator of the satellite main body. A frequency component Δω appears. The quasi-synchronous quadrature input signal from which the harmonic components have been removed is subjected to analog / digital conversion by the A / D converter 2, and the digitized quasi-synchronous quadrature input signal is controlled in oscillation frequency ω ₁ by a control value output from the AFC 12. The output signal of the NCO 5 is subjected to complex multiplication and frequency conversion. The frequency-converted quasi-synchronous quadrature input signal s (nT) output from the AFC complex multiplier 4 is expressed as s (nT) = cos ｛(Δω-ω ₁ ) nT + φ (nT)｝ + j sin ｛(Δω-ω ₁ ) NT + φ (nT)｝ (3), which is an input signal of the PLL. At this time, the residual angular frequency error Δω ₁ due to the AFC is Δω ₁ (nT) = Δω (nT) −ω ₁ (nT) (4) Further, a first-order difference equation showing a response of a phase error θ _e (nT) detected by a first-order PLL when a phase detector having a sine wave characteristic is used, where a loop gain is K and Δ
Using ω ₁ , θ _e (nT) −θ _e (nT−T) = Δω ₁ (nT) −K sin θ _e (nT) (5) FIG. 2 is a block diagram showing the nonlinear differential equation given by equation (5). In addition, NCO
Is proportional to the output frequency, but the correspondence between the output phase and the output phase is expressed by integration because the frequency-phase relationship is an integral relationship.

Output signal g (nT) of PLL filter 36
From equation (5), g (nT) = K [Δω ₁ (nT) − {θ _e (nT) −θ _e (nT−T)}] (6) Since the time change amount of the phase corresponds to the angular frequency, g (nT) = K ｛Δω ₁ (nT) −ω _e (nT)｝ = Kω ₂ (nT) (7), and the output of the PLL filter 11 The signal g (nT) is proportional to the oscillation frequency ω ₂ of the second NCO 9.

A large time variation occurs in the carrier offset frequency of the quasi-synchronous quadrature input signal due to the Doppler shift caused by the movement of the non-geostationary orbit satellite, and the variation in the offset frequency increases the residual frequency error in the AFC. If the residual frequency error in the AFC exceeds the frequency pull-in range and the synchronization holding range in the PLL, the phase synchronization is not locked in the PLL. In order to provide stable phase synchronization, it is necessary to control the residual frequency error in the AFC within the frequency pull-in range and the synchronization holding range in the PLL.

In the present invention, control is performed by the following method in order to keep the residual frequency error in the AFC within the frequency pull-in range and the synchronization holding range in the PLL.

When the amount of change in the residual frequency error in the AFC exceeds a certain threshold, the loop band, the frequency control width, and the control time interval of the AFC and the PLL are increased. In this result, AFC
Control time is shortened as the frequency tracking range of
Therefore, the residual frequency error in the AFC is suppressed at high speed. PLL
Then, the residual frequency in AFC is expanded
Control is performed so that phase synchronization is maintained even when the number error is large.
I will. Conversely, when the time variation of the residual frequency error in the AFC becomes small, the loop band, the frequency control width, and the control time interval of the AFC and the PLL are reduced. As a result, AFC
And the control time becomes longer
To keep it stable. PLL reduces the loop bandwidth
Control to suppress the effects of noise.
You. As described above, the time when the frequency error of the received signal is large
Provide carrier phase synchronization that is stable and less affected by noise even in the presence of fluctuations .

The above operation will be described based on the carrier phase synchronization circuit shown in FIG.

The oscillation frequency of the second NCO 9 is controlled to be a residual frequency error in the AFC, and the output value of the PLL filter 11 is proportional to the oscillation frequency of the second NCO 9. The amount of change in the output value over time corresponds to the change in the residual frequency error in the AFC. Therefore, the change amount of the residual frequency error in the AFC is represented by the time change amount Δg (nT) of the output value g (nT) of the PLL filter 11, where Δg (nT) is Δg (nT) = g (nT) −g (NT−T) (8) Δg (nT) is calculated by the delay element 13 and the subtractor 14, passes through an averaging circuit 15 for averaging the output signal of the subtractor 14, and inputs the filtered output signal of the subtracter 14 to a data discriminator 16. Data discriminator 16
Is input to the AFC loop filter 12 and the PLL loop filter 11, and as a result, the AFC and PLL
Of the loop band, frequency control width, and control time interval.

[0020]

As described above, according to the present invention, it is possible to perform high-speed frequency tracking for a reception modulation wave having a large time variation of frequency detuning such as a non-geostationary orbit satellite and realize stable phase synchronization. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a primary PLL of the present invention.

FIG. 3 is a block diagram of a carrier phase locked loop circuit using a conventional PLL.

FIG. 4 is a block diagram of a conventional carrier phase synchronization circuit using AFC and PLL.

[Explanation of symbols]

 Reference Signs List 1 LPF 2 A / D converter 3 Sampling clock oscillator 4 AFC complex multiplier 5 AFC numerically controlled oscillator 6 Nyquist filter 7 Memory 8 PLL complex multiplier 9 PLL numerically controlled oscillator 10 Phase detector 11 PLL filter 12 AFC loop filter Reference Signs List 13 delay element 14 subtractor 15 averaging circuit 16 data discriminator 17 phase comparator 18 phase detector 19 loop filter 20 voltage controlled oscillator 21 phase comparator 22 LPF 23 phase comparator 24 phase detector 25 PLL filter 26 PLL voltage controlled oscillator 27 frequency error detector 28 AFC 29 sample / hold circuit 30 AFC voltage controlled oscillator

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (4)

(57) [Claims] 1. A carrier phase locked loop circuit for recovering a carrier from an input signal, comprising: a multiplier for an automatic frequency control loop for multiplying the input signal by an output of a first voltage controlled oscillator to suppress a frequency error; A carrier phase locked loop multiplier for multiplying an output of the control loop multiplier and an output of the second voltage controlled oscillator to regenerate a carrier, and phase detection for obtaining phase error information from the output of the carrier phase locked loop multiplier A second detector for receiving the output of the phase detector and outputting a control voltage for controlling the second voltage controlled oscillator
And a first loop filter that receives the output of the second loop filter and outputs a control voltage that controls the first voltage-controlled oscillator. The output of the second loop filter A time change amount is calculated and generated based on the determination result of the magnitude of the time change amount.
Control means for inputting the obtained control signal to first and second loop filters to control a loop band, a frequency control width, and a control time interval of the automatic frequency control loop and the carrier phase locked loop. Carrier phase synchronization circuit. 2. The control means according to claim 2, wherein
A delay element for delaying a filter output by a unit time ;
A subtractor for subtracting a signal delayed unit time from the loop filter output, a filter for averaging the output signal of the subtractor is a variation per unit time of the frequency error, the averaged frequency error unit time discriminated said automatic frequency control loop and loop bandwidth of the carrier phase locked loop the variation in the frequency control range, according to claim 1, characterized in that it is constituted by a data discriminator for generating a control signal for controlling the time interval Carrier phase synchronization circuit. 3. The carrier phase synchronization circuit according to claim 1, wherein said input signal is a quasi-synchronous orthogonal signal and has a large carrier frequency fluctuation. 4. The control means according to claim 1, wherein the time variation of the frequency error exceeds a predetermined value for each of a loop band, a frequency control width, and a control time interval of the automatic frequency control loop and the carrier phase locked loop. 3. The carrier phase synchronization circuit according to claim 1, wherein the phase synchronization is maintained by widening, and the phase synchronization is narrowed when the time variation of the frequency error is smaller than a predetermined value.