JPH0624312B2 - Automatic frequency controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used as a device for automatically controlling the frequency of an oscillator in a communication device and the like.

According to the present invention, in a circuit for loop-controlling the output frequency of an oscillator by a digital processing circuit, the fact that the output frequency of the oscillator is controlled to a desired value is performed by utilizing the change in the polarity of the frequency error signal, thereby achieving accurate synchronization. The state determination can be performed.

[Conventional technology]

FIG. 7 is a block diagram of a conventional digital automatic frequency control circuit. The input signal having the frequency deviation given to the input terminal 11 is input to the first frequency conversion circuit 12, mixed with the output signal of the voltage controlled oscillator 13, and the input signal frequency and the output signal frequency of the voltage controlled oscillator 13 are mixed. The output signal with the difference frequency is obtained and sent to the output terminal 21. This output signal is branched and input to the second frequency conversion circuit 14, mixed with the output signal of the fixed oscillator 15 that oscillates the reference frequency, the output signal frequency of the first frequency conversion circuit 12 and the output of the fixed oscillator 15. The frequency of the difference from the signal frequency,
Obtain two output signals S and C whose phases are orthogonal to each other. The two quadrature output signals S and C are error information, and unnecessary wave components such as harmonics and noise are removed by the low-pass filters 16 and 17, and are input to the AD conversion circuits 18 and 19, respectively, and converted into digital signals. To be converted. This digital signal is input to the frequency error detection circuit 22 and an output signal corresponding to the polarity of the frequency error is obtained.

This output signal is input to the digital loop filter 23 to reduce errors due to noise, etc.
Entered in 24. The switching circuit 24 switches between a steady mode in which a normal automatic frequency control operation is performed and a sweep mode in which the output signal frequency of the voltage controlled oscillator 13 is swept. In the steady mode, the output signal of the switching circuit 24 is the output of the digital loop filter 23, and in the sweep mode, the output signal of the switching circuit 24 is added to the output signal of the clock oscillator 25. The sweep mode and the steady mode are switched by the switching control signal from the switching control signal input terminal 26.

In the steady mode, the output signal of the switching circuit 24 is input to the digital integrator 27. The output of the digital integrator 27 is DA
The conversion circuit 28 converts the digital signal into an analog signal and inputs it to the voltage controlled oscillator 13 as a control signal so that the frequency error is controlled to be minimum.

In this way, a feedback loop for controlling the output signal frequency of the fixed oscillator 15 and the output signal frequency of the first frequency conversion circuit 12 to coincide with each other is configured.

In the sweep mode, the output signal of the switching circuit 24 is the output signal of the clock oscillator 25 and has a constant frequency. When this output signal is input to the digital integrator 27, converted from a digital signal to an analog signal by the DA conversion circuit 28, and input to the voltage controlled oscillator 13 as a control signal, the output signal frequency of the voltage controlled oscillator 13 is constant. It will sweep at a constant speed in the direction.

When the input signal at the terminal 11 is a burst signal which is intermittent in time, the frequency error Δ is detected only during the time when the burst signal exists. Therefore, if the duty ratio occupied by the burst signal is δ, the operating clock of the automatic frequency control circuit is δ · Δ
And the operating clock frequency decreases. Therefore, in the digital automatic frequency control circuit, the TDMA communication (Tim
When used in a burst demodulator used for e-division multiple access, the pull-in time becomes 1 / δ times longer. Therefore, in order to speed up the pull-in time, the output signal frequency of the voltage controlled oscillator 13 is swept at the start of pull-in, and
A method of approaching the vicinity of = 0, detecting the approaching, and switching from the sweep mode to the steady mode AFC operation is adopted.

That is, in the conventional digital automatic frequency control circuit, there is a method of supplying a switching control signal for switching between the sweep mode and the steady mode from the outside as a control signal. In addition to this, the frequency error detection circuit 22 obtains an edge detection pulse from rising and falling edges, measures the period of this edge detection pulse, and performs frequency synchronization detection,
As a result, a method of switching between the sweep mode and the steady mode has been adopted.

[Problems to be solved by the invention]

If the input signal is a burst signal that is intermittent in time,
The frequency error information is detected only when the burst signal is present. The edge detection pulse to be detected is missing at the time when the burst signal does not exist. Therefore, if the cycle of this edge detection pulse becomes larger than the cycle of the true error frequency and exceeds the size of the frequency synchronization determination cycle, it is determined that synchronization has occurred despite the fact that the frequency error is actually large. However, there is a defect that pseudo frequency synchronization may occur such as switching to the steady mode.

It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a digital automatic frequency control circuit capable of accurately detecting a synchronization state with a simple circuit configuration.

[Means for solving problems]

The present invention converts the frequency error information orthogonally converted into the base band into a binary digital signal, detects the polarity of the frequency error from the rising and falling edges of this digital signal, and changes the polarity within a predetermined time. It is characterized in that frequency synchronization is determined and detected when N times (N is an integer of 2 or more) can be counted.

In addition, according to the result of this frequency synchronization judgment detection, the sweep mode in which the control frequency is swept at a constant speed is switched to the steady mode in which the frequency is loop-controlled in accordance with the frequency error that is successively detected. To do.

Further, the sweep speed can be switched, the constant of the loop filter for removing the noise component can be switched, and the result of frequency synchronization determination can be used.

The conventional digital automatic frequency control circuit uses the edge detection pulse to detect the frequency synchronization, but the present invention is characterized in that the polarity of the frequency error is used.

[Action]

The present invention utilizes the fact that when the oscillation frequency reaches a desired value, the detected frequency error periodically fluctuates positively and negatively with zero as a boundary. That is, when the frequency control is not performed correctly, the frequency error has a positive or negative polarity for a long time. However, when the frequency error becomes smaller and the frequency control reaches a desired value, the delay time of the control circuit causes the frequency error to periodically fluctuate between positive and negative values in a small range. The polarity variation of the frequency error is counted for a predetermined time, and when the count value exceeds the predetermined value N, it is determined that the frequency synchronization state is established.

According to this method, the synchronization state detection circuit is simple,
It will not be detected by mistake. In particular, when a transmission signal or a reception signal is a burst signal in a communication device, it is erroneously determined that the control loop is in a synchronization state when the burst signal is interrupted and the automatic frequency control loop does not operate. Will disappear.

When the loop is in an asynchronous state, this synchronous detection output can be used to automatically force the oscillator frequency to sweep over a relatively wide range and control so that the correct oscillation frequency can be quickly captured. it can.

〔Example〕

FIG. 1 is a block diagram of the first embodiment apparatus of the present invention. This device is provided with a circuit for frequency-converting the signal (frequency ₁ ) arriving at the signal input terminal 11 by the first frequency conversion circuit 12 and sending it to the signal output terminal 21. The first frequency conversion circuit An automatic frequency control device according to an embodiment of the present invention is shown as a device that uses a voltage controlled oscillator 13 as an oscillator for supplying a local oscillation frequency ( ₂ ) to 12 and loop-controls the oscillation frequency of the voltage controlled oscillator 13. In this example, the frequency _{1 of} the signal a arriving at the signal input terminal 11
However, the output frequency ₂ of the voltage controlled oscillator 13 is tracked and controlled so as to absorb this fluctuation, and the signal output terminal
Reference numeral 21 shows an intermediate frequency signal (frequency ₃ ) whose fluctuation is absorbed and whose frequency is stabilized.

That is, this device inputs a voltage controlled oscillator 13, a first frequency conversion circuit 12 having an output frequency ( ₂ ) of this oscillator as a local oscillation frequency, and an output signal (frequency ₃ ) of this first frequency conversion circuit. And a second frequency conversion circuit 14 for obtaining an error frequency (Δ) with respect to the reference frequency ( ₄ ). This reference frequency ( ₄ ) is supplied from the fixed oscillator 15.

The second frequency conversion circuit is an output circuit that outputs the signal of the error frequency as two signals S and C in the base band whose phases are orthogonal to each other, and these two signals S and C output low-pass filters 16 and 17, respectively. It is given to the AD conversion circuits 18 and 19 via the respective signals and converted into digital signals DS and DC. This digital signal DS and D
A circuit for performing signal processing with C as an input and outputting a digital signal to be given to the DA conversion circuit 28 is constituted by a digital processing circuit.

The digital processing circuit includes a frequency error detection circuit 31 for detecting the polarity of the frequency error from the output signals DS and DC of the two AD conversion circuits 18 and 19, and a change in the polarity of the frequency error a predetermined number of times within a predetermined time. Frequency synchronization detection circuit for determining the frequency synchronization state when reaching N
35 and. Furthermore, this digital processing circuit has
A digital loop filter 33 through which the output signal of the frequency synchronization detection circuit 35 passes, a switching circuit 34 having the output of the filter 33 as an input, and an output signal of the switching circuit 34 as an input to the DA conversion circuit 28. A digital integrator 27 for supplying an input digital signal.

Here, the switching circuit 34 has two switching modes, a "steady mode" and a "sweep mode". Frequency synchronization detection circuit
According to the detection output of 35, when the detection output indicates the synchronous state, the output signal of the digital loop filter 33 is fed back to the digital integrator 27 as the frequency error information in the steady mode. When the detection output is in the asynchronous state, the voltage controlled oscillator is set to the sweep mode.
A control signal for sweeping the oscillation frequency of 13 is generated from the clock oscillator 25 and supplied to the digital integrator 27.

Next, the operation of the embodiment apparatus shown in FIG. 1 will be described in detail. The input signal a having a frequency deviation from the input terminal 11 is input to the first frequency conversion circuit 12, mixed with the output signal of the voltage controlled oscillator 13, and the input signal frequency ₁ and the output signal frequency _{2 of the} voltage controlled oscillator 13 are mixed. Obtain an output signal with a frequency of difference. This output signal is sent to terminal 21. Further, this output signal is branched and input to the second frequency conversion circuit 14, and mixed with the output signal of the fixed oscillator 15 which outputs the reference frequency. Further, two orthogonal output signals S and C are obtained with respect to the frequency difference between the output signal frequency _{3 of} the first frequency conversion circuit 12 and the reference frequency ₄ of the fixed oscillator 25. Output signal frequency of the first frequency converting circuit 12 ₃ = ₂ - _1, the second output signal frequency of the frequency converter 14 of delta = ₃ - _4, and the this frequency represents the difference between the reference frequency error Is. Two output signals S and C of the second frequency conversion circuit 14 which are orthogonal to each other are supplied to low-pass filters 16 and 17, respectively.
This eliminates unnecessary wave components such as harmonics and noise. The output signals S and C ′ of the low-pass filters 16 and 17 are S ′ = sin (2πΔ · t) C ′ = cos (2πΔ · t), where t represents time.

Becomes The two output signals S'and C'which are orthogonal to each other are input to AD conversion circuits 18 and 19, respectively, and
Digital signal of value DS = sgn [sin (2πΔ · t)] DC = sgn [cos (2πΔ · t)] where sgn [X] indicates 1 when X ≧ 0 and 0 when X <0.

To get Next, the output signals DS and DC of the two AD conversion circuits 18 and 19 are input to the frequency error detection circuit 31. The output signal SF is as follows: The following output signal SF is obtained according to the polarity of the frequency error Δ. That is, if Δ> 0, SF = 1 If Δ <0, SF = 0 If Δ = 0, the SF maintains the immediately previous state.

The frequency error detection circuit 31 also obtains a periodic output signal CF according to the magnitude of the frequency error Δ. That is, the output signal SF is a polarity signal with a frequency error Δ, and the output signal C
F is a clock signal of the AFC circuit according to the magnitude of the frequency error Δ.

The principle of detecting the output signals SF and CF will be described. The frequency error detection circuit 31 has two digital signals DS and DC.
One of them is used as a reference timing, and the level of the other digital signal is detected. The reference timing is the rise of DS,
4 of DS falling, DC rising, DC falling
If n pieces (n is an integer from 1 to 4) are selected as reference timings from among these, there are ₄ C _n combinations for selecting n pieces. In this operation description, the maximum value n of n
= 4 will be described.

2 and 3 are time charts for explaining the operation of the frequency error detection circuit 31 described above. This is the case when n = 4, and in the case of Δ> 0 in FIG.
In FIG. 3, the case of Δ <0 is shown as a separate diagram. 2 and 3, DS is an AD conversion circuit 18
, And DC is an output signal of the AD conversion circuit 19.
P1 is a rising edge detection pulse of DS, P2 is a falling edge detection pulse of DS, P3 is a rising edge detection pulse of DC, P4
Indicates a DC falling detection pulse. SF and CF are output signals of the frequency error detection circuit 31.

As can be seen from FIGS. 2 and 3, the rising edge of DS is detected to detect the detection pulse P1, the falling edge of DS is detected to detect the detection pulse P2, and the rising edge of DC is detected to detect the detection pulse P.
3. The detection pulse P4 is obtained by detecting the falling edge of DC. That is, the output signal CF of the frequency error detection circuit 31
Is obtained from the logical sum of P1, P2, P3 and P4 modulo 2. Further, the output signal SF of the frequency error detection circuit 31
Is obtained by detecting one of the two digital signals DS and DC as the reference timing and the level of the other digital signal. That is, the reference timing is the detection pulse P1.
Alternatively, in the case of P2, the level of the signal DC is detected, and in the case of the detection pulse P3 or P4, the level of the signal DS is detected and an output is obtained. Therefore, P1, P2, P shown in FIG.
3 and P4 are the reference timings, respectively, and 2 is the modulus, and P1.DC + P2. + P3. + P4.DS, where • is a logical product, + is a logical sum, and is the complement of X.

Then, this equation gives the frequency error Δ at the reference timing point.
Will show the polarity of. Therefore, the output signal SF
Is obtained by the operation of holding the level at the detected reference timing point until the next reference timing point. In this way, the frequency error detection circuit 31 detects the clock according to the polarity of the frequency error Δ and its magnitude. Since this output signal SF contains an error due to noise or the like,
This output signal SF is passed through a digital loop filter 23 to obtain a smoothed output signal SF '. Further, the signal CF 'passed through the digital loop filter 23 is AF
It is the clock of the C circuit, and the period of the signal CF 'is equal to CF.

The output signals SF ', C of the digital loop filter 23
F'is input to the switching circuit 34. In the switching circuit 34, the “steady mode” in which normal AFC operation is performed, and the voltage controlled oscillator 13
Switch to the "sweep mode" that sweeps the output signal frequency ₂ of. In the steady mode, the switching circuit 34 utilizes the input signals SF 'and CF'. In the sweep mode, the switching circuit 34 uses the sweep clock signal b and the sweep polarity signal d which are the output signals of the clock oscillator 25.
As the sweep polarity signal d, the output signal SF of the frequency error detection circuit 31 can be used as it is, and d = SF. The sweep mode and the steady mode are switched by the switching control signal e. This switching control signal e is given from the frequency synchronization detection circuit 35. Frequency synchronization detection circuit 35
When it detects that the frequencies are synchronized from the output signal SF of the frequency error detection circuit 31, it sets the level of the switching control signal e to "1" indicating the steady mode, and when it is not in the synchronized state, it indicates "0" indicating the sweep mode. To do. The output signals SF ″ and CF ″ of the switching circuit 34 are as follows: when e = 1, SF ″ = SF ′ CF ″ = CF ′ where e = 0, SF ″ = SF CF ″ = b.

In the steady mode, the output signals SF ″ and CF ″ of the switching circuit 34 are input to the digital integrator 27. The output of the digital integrator 27 is converted from a digital signal to an analog signal by the DA conversion circuit 28, and the voltage controlled oscillator 13
Is input as a control signal to control the frequency error Δ to a minimum. A feedback loop for controlling such this way with the output signal frequency ₄ of the fixed oscillator 15 and the output signal frequency ₃ of the first frequency converting circuit 12 coincide is constructed. The circuit of FIG. 1 is thus AFC
Operates as a circuit.

Next, in the sweep mode, the sweep polarity signal d
Is the output signal SF of the frequency error detection circuit 31, and the sweep direction is controlled by this. The sweep clock signal b is an output signal of the clock oscillator 25, which is a signal having a constant frequency. In the sweep mode, these two signals are output as output signals SF ″ and CF ″ from the switching circuit 34 and input to the digital integrator 27. The output signal of the digital integrator 27 is converted from a digital signal to an analog signal by the DA conversion circuit 28 and input to the voltage controlled oscillator 13 as a control signal.

FIG. 4 is a time chart for explaining the operation in the sweep mode. Δ indicates the above-mentioned frequency error. SF is an output signal of the frequency error detection circuit 31. In the sweep mode, since the sweep direction is controlled by the output signal SF of the frequency error detection circuit 31 and a feedback loop is formed, the frequency error Δ is large even when the initial frequency error is large as shown in FIG. The sweep clock signal b is an output signal of the clock oscillator and is a signal of a constant frequency, but Δ =
The sweep does not stop even when it reaches 0. Generally, the frequency error Δ
Since there is some delay in the detection of the polarity reversal, the vibration state is generated by raising or lowering the 0 level so that the frequency error Δ becomes small as shown in FIG.

As described above, the frequency error controlled so that Δ is small in the vicinity of Δ = 0 will be described.
The detection timing of is the output signal DS of the AD conversion circuit and DC rising and falling. If the input signal is a continuous signal, the voltage controlled oscillator
The output signal frequency of is changing at a constant rate. Assuming that the rate of change of this frequency is K, S ′ and C ′ are used instead of DS and DC for simplification of explanation, and Δ at t = 0.
= 0 and when Δ increases: S ′ = sin (2πKt · t + θ) C ′ = cos (2πKt · t + θ) where θ is the initial phase.

Becomes If the number of rising and falling is n,
Although there are many combinations as described above, here, the combination of retaining ponds is omitted as a practical example. When n = 1, one rise or fall is used, when n = 2, one rise and fall is used, and when n = 4, both rises and falls are used. Rise and fall are
This is the case when S ′ = 0 and C ′ = 0. The maximum value of the frequency error is the point at which S ', C'in () at the first rise or fall is the maximum. Therefore, the sine
In (sin), if the detection time is T _m , n = 1, rising 2πKT _m · T _m + θ = 2π (θ = 0) n = 1, falling 2πKT _m · T _m + θ = π (θ = −π The same applies to the cosine (cos), which is 2πKT _m · T _m = 2π / n (n = 1, 2, 4). Therefore, the average time T ₁ is set to 1 / the maximum value T _m .
If 2, That is, the polarity of the frequency error is detected after T ₁ time and the direction is reversed to reduce the frequency error. The frequency error Δ ₁ when the polarity is detected is KT ₁ , Becomes

Next, the case of a burst signal will be described. In the case of a burst signal, there is essentially no automatic loop control while the signal is interrupted. Therefore, the output frequency ₂ of the voltage controlled oscillator 13 becomes a fixed value while this signal is interrupted. Therefore, a fixed frequency error occurs when the burst signal is restarted. Assuming that this fixed frequency error is Δ ₂ , the average detection time interval for detecting the rising or falling may be 1/2 of the maximum value, which is 1 / (2n · Δ ₂ ). Further, in the case of a burst signal, rising and falling are detected only during the time when the burst signal exists, so the detection time interval becomes 1 / δ times when the ratio of the time when the burst signal exists is δ. That is, the detection time interval T ₂ is T ₂ = 1 / (2n · δ · Δ ₂ ). Therefore, the number of error frequency waves required for detection is Δ ₂ · T ₂ = 1 / (2n · δ).

In the sweep mode, since the frequency is actually changing, letting the detection time be T, Kt from t = 0 to T
Integrated value KT ^2/2 is the number of waves necessary for detection to. In other words, the ^{KT 2/2 = 1 / (} 2n · δ). Therefore, the detection time T and the frequency error Δ are Can be given.

As described above, the frequency error when the frequency is pulled in the vicinity of Δ = 0 in the sweep mode can be determined as Δ ₁ · Δ by the above equation.

Although the above is the continuous control, the sweep control can be performed stepwise instead of continuously. In this case, the frequency of the sweep clock signal frequency control amount per _c, 1 clock 'as, K to 1 / _c Time' K so changed, approximating the change rate K of the frequency K = K '· _c You can That is, the frequency error Δ
Can be made smaller than the required frequency error by selecting the frequency of the sweep clock signal as _c and the frequency control amount per clock as K '. Therefore, this can be achieved by selecting _c and K ′ so as to be smaller than the required frequency error. Further, when K ′ is fixed, Δ decreases as _c decreases.

Next, the switching operation from the sweep mode to the steady mode will be described. The output signal SF of the frequency error detection circuit 31 in the sweep mode has a constant level when the frequency error Δ is large as shown in FIG. 4, but Δ = 0.
, And the frequency error Δ becomes smaller, the level changes depending on the polarity of the frequency error, and 0 level and 1 level are repeated. This repetition continues until switching to the steady mode. Therefore, the frequency synchronization detection circuit 35 counts the level change of the output signal SF of the frequency error detection circuit 31 for a predetermined time, and when it reaches a predetermined N times, determines that the frequency error Δ is in the vicinity of Δ = 0. To do. This determination result becomes the output signal e of the frequency synchronization detection circuit 35, and switches between the sweep mode and the steady mode.

A specific circuit of the frequency synchronization detection circuit 35 can be configured by a counter having an input connected to a clock terminal, an overflow terminal connected to an output, and reset by a clock signal corresponding to a predetermined time. This circuit can be realized by a simple circuit. By increasing the number of times N, erroneous detection due to noise can be avoided, but the time until synchronization detection becomes long.

Further, in the sweep mode, the frequency of the clock oscillator 25 can be switched by the clock switching control signal g which is the output signal of the frequency synchronization detection circuit 35. As a result, the frequency error Δ is reduced stepwise. The frequency synchronization detection circuit 35 performs the detection operation N times a plurality of times, and the number of times N is N
₁ , N _i ... N _j times (N _i <N _{i + 1} ) and the output frequency of the clock oscillator 25 is set smaller as the number of times increases. This output frequency is switched by a clock switching control signal g which is an output signal of the frequency synchronization detection circuit 35 according to the number of times. By switching the clock frequency in this manner, stable operation against noise can be secured, and the switching time between the sweep mode and the steady mode can be shortened.
Here, when the number N of times is set to one value, the operation is the same as that of the fixed frequency clock oscillator.

Thus, according to the present invention, when the input signal is a burst signal which is intermittent in time, frequency error information obtained by orthogonal transform is detected only during the time when the burst signal exists, but when the frequency error is small. Occurs only when the frequency error is large and does not occur when the frequency error is large. Moreover, when the frequency error is small, the detection output changes between positive and negative when the frequency error is near zero, and this is repeated. Therefore, it is possible to count the number of times of this polarity change and detect the frequency synchronization determination.
As a result, the phenomenon of pseudo-frequency synchronization, which is mistakenly brought into the synchronized state, does not occur. If this determination detection result is used for switching between sweep mode and steady mode, switching of sweep speed, and switching of filter constants, erroneous switching will not occur. If the input signal is a continuous signal, the pseudo frequency synchronization is not similarly generated.

FIG. 5 shows a partial circuit diagram of a second embodiment device of the present invention.
Reference numeral 51 indicates a digital loop filter. SF ′
Is the output signal of the digital loop filter 51,
This signal has the same polarity as that described above. CF 'is an output signal of the same 51 and is a clock signal.

This embodiment differs from the first embodiment shown in FIG. 1 in that the time constant of the digital loop filter 51 is variable and can be switched by the output of the frequency synchronization detection circuit 53, and the frequency synchronization detection circuit The point is that the polarity signal SF ′ of the digital loop filter 51 is used for the input of 53.

The output signal SF 'of the digital loop filter 51 is a signal that has been smoothed and the error due to noise has been removed. The level change of the output signal SF 'is counted, and the frequency error Δ
Similarly, it is detected that is close to Δ = 0. That is, the level change of the output signal SF 'of the digital loop filter 51 as an input of the frequency synchronization detection circuit 35 is counted for a predetermined time, and when it reaches a predetermined N times, it is determined to be in the synchronization state. This determination is performed a plurality of times as in the previous example, and the determination result becomes the output signal of the frequency synchronization detection circuit 35, and becomes the switching control signal and the clock switching control signal of the switching circuit 34. In addition to this, in the second embodiment, the output signal of the frequency synchronization detection circuit 35 is used as the time constant switching control signal of the digital loop filter 51.

That is, the filter 51 narrows its bandwidth in the synchronous state to improve noise removal performance, and widens its bandwidth in the asynchronous state to facilitate synchronization pull-in.

FIG. 6 shows a partial circuit diagram of the third embodiment of the present invention. In the third embodiment, the sweep polarity signal d which is the input of the switching circuit 34 is further used as the digital loop filter 51.
It is characterized in that the polarity signal SF ′ of is used. The digital loop filter 51 of this embodiment shown in FIG.
The operation of the frequency synchronization detection circuit 35 and the frequency synchronization detection circuit 35 are the same as those explained in the operation of the first embodiment in FIG.

The output signal SF 'of the digital loop filter 51 is a signal from which errors due to noise have been removed. This output signal S
It is also possible to use F'as the sweep polarity signal. That is, the influence of noise can be further reduced by using it as the sweep polarity signal d which is the input of the switching circuit 34.

〔The invention's effect〕

As described above, according to the present invention, the fact that the frequency of the oscillator has reached the desired value is detected by the change in the polarity of the error frequency, and the number of changes exceeds the predetermined number for the predetermined time. The circuit is simplified, and its detection is error-free, so that what is not actually in the synchronization state is not determined to be the synchronization state. This is particularly advantageous when the signal to be handled is a burst signal.

Further, when the result of this determination is the asynchronous state, the control loop is automatically opened, the mode is switched to the sweep mode, and the control is performed, whereby a stable device that can quickly recover the asynchronous state can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of the apparatus of the first embodiment of the present invention. FIG. 2 is a signal waveform diagram for explaining the operation of the main part, showing a case where the polarity of the error frequency is positive. FIG. 3 is also a signal waveform diagram for explaining the operation of the main part, showing the case where the polarity of the error frequency is negative. FIG. 4 is a signal waveform diagram for explaining how the polarity of the error frequency periodically changes. FIG. 5 is a partial circuit configuration diagram of a second embodiment device of the present invention. FIG. 6 is a partial circuit configuration diagram of a third embodiment device of the present invention. FIG. 7 is a block diagram of a conventional circuit. 11 ... Signal input terminal, 12 ... First frequency conversion circuit, 13 ... Voltage controlled oscillator that outputs local oscillation frequency, 14 ... Second frequency conversion circuit, 15 ... Fixed oscillator that outputs reference frequency,
16, 17 ... Low-pass filter, 18, 19 ... AD conversion circuit, 21 ... Signal output terminal, 22 ... Frequency error detection circuit, 23 ... Digital
Loop filter, 24 ... Switching circuit, 25 ... Clock oscillator, 26 ... Control input terminal, 27 ... Digital integrator, 28 ... D
A conversion circuit, 31 ... Frequency error detection circuit, 33 ... Digital loop filter, 34 ... Switching circuit, 35 ... Frequency synchronization detection circuit, 51 ... Digital loop filter.

Front page continuation (72) Inventor Masahiro Umehira 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) References JP-A-63-224409 (JP, A) JP-A-62 -190958 (JP, A) JP-A-2-84847 (JP, A) JP-A 1-264042 (JP, A)

Claims (2)

[Claims] 1. An oscillator (13), frequency conversion means (12, 14) for obtaining an error frequency (Δ) with respect to a reference frequency ( ₄ ) by using the output of this oscillator as a local oscillation frequency ( ₂ ), and this error Circuit means for integrating frequency information and feedback-connecting to the oscillator as a control signal of an oscillation frequency, wherein the frequency conversion means includes two signals in a base band in which the signals of the error frequency are orthogonal to each other in phase ( S, C) output means (14), the feedback connection circuit means includes two signals (S, C).
An automatic frequency control device including two AD conversion circuits (18, 19) for respectively converting C) into digital signals and a digital processing circuit for digitally processing an output signal of the AD conversion circuit, wherein the digital processing circuit comprises: A frequency error detection circuit (31) that detects the polarity of the frequency error from the output signals of the two AD conversion circuits (18, 19), and the change in the polarity of the frequency error reaches a predetermined number (N) within a predetermined time. An automatic frequency control device, further comprising: a frequency synchronization detection circuit (35) for determining a frequency synchronization state. 2. The digital processing circuit feedback-connects frequency error information as a steady mode in the synchronous state according to the detection output of the frequency synchronization detecting circuit, and as a sweep mode in the asynchronous mode as the oscillator mode of the oscillator. An automatic frequency control device according to claim 1, including circuit means (34, 25) for generating a control signal for sweeping the oscillation frequency.