JP3028073B2 - Small-amplitude interface buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interface circuit for a semiconductor integrated circuit, and more particularly to an output buffer circuit operating at a high frequency.

[0002]

2. Description of the Related Art FIG. 3 shows an example of the configuration of a conventional output buffer circuit. Referring to FIG. 3, in this output buffer circuit, a first differential pair 101 and a second differential pair 102 are arranged between a power supply VDD and a ground GND, and the first differential pair 101 and the second differential pair 102 are arranged opposite to each other. The first differential pair 101 and the second differential pair 10 are first and second input terminals A + and A- for inputting complementary signals by cross-connecting the gate terminals of the two differential pairs 102 to each other.
The second connection point is configured as first and second output terminals B + and B−.

More specifically, the transistors constituting the first differential pair 101 and the drains of M11 and M12 are commonly connected, and the sources of the transistors M11 and M12 constitute the second differential pair 102, respectively. Transistor M
13 and the drain of M14. The sources of the transistors M13 and M14 are commonly connected. The common connection point of the drains of the transistors M11 and M12 is connected to the power supply VDD via the transistor M15, and the common connection point of the sources of the transistors M13 and M14 is connected to the ground GND via the transistor M16.

The gates of the transistors M11 and M14 are commonly connected and connected to a terminal A +.
2. The gates of M13 are commonly connected and connected to terminal A-. Complementary signals are input to these two terminals A + and A-.

The connection point between the source of the transistor M11 and the drain of the transistor M13 and the connection point between the source of the transistor M12 and the drain of the transistor M14 are output terminals B + and B-, which output complementary small amplitude signals. . These output terminals B + and B- are terminated by resistors.

[0006] The transistor is an N-channel MOS transistor or a P-channel MOS transistor.

The transistors M12 and M14 have the same potential threshold level, and the transistors M11 and M11 have the same potential level.
M12 has two threshold levels alternately depending on operating conditions.

When the potential at the connection point between the source of the transistor M11 and the drain of the transistor M13, which is the output terminal B +, is at a high level, the transistor M11 has a threshold level higher than that of the transistors M12, M13 and M14. When the output terminal B + on the side is at the low level, the transistor M11 has the same threshold level as the transistors M13 and M14.

Similarly, when the potential at the connection point between the source of the transistor M12, which is the output terminal B-, and the drain of the transistor M14 is at a high level, the transistor M12
Is at a threshold level having a higher potential than the transistors M11, M13 and M14, and when the output terminal B− of the transistor M12 is at the Low level, the transistor M1
2 has the same threshold level as the transistors M13 and M14.

In the above circuit, first and second input terminals A +,
When signals complementary to each other are input from A-, the input potential becomes
At two different times, the current passes through the threshold levels of the transistors M11 and M13.

The transistors M12 and M14
Also passes through the threshold level at different times.

FIG. 4 is a diagram showing input / output waveforms of the output buffer circuit shown in FIG.

When the input potential of the gate of the transistor M11 reaches the threshold level (below the threshold level in FIG. 4) at the time of switching of the waveform and the transistor M11 switches from ON to OFF, the complementary signal of this signal is gated. Transistor M12 to be input
Since the potential of the gate of the transistor M13 has not reached the threshold level, both the transistor M12 and the transistor M13 maintain the OFF state.

That is, at this time (time in FIG. 4), the transistors M11, M12 and M13 are simultaneously turned off.
The state becomes FF.

On the other hand, since the transistor M14 has not yet reached the threshold level, it remains on.

In this state, the current supply path is cut off,
Only the outflow path of the current is open, and the potentials of the two output terminals B + and B- rapidly decrease.

After a lapse of a predetermined time, the transistor M12,
The potential of the gate of M13 rises, and the transistor M12,
Since both M13 are switched from OFF to ON (time in FIG. 4), the current supply path is established, so that the output potential recovers, but the output potential temporarily drops, resulting in ringing.

The ringing causes a malfunction of the receiver and significantly lowers the reliability.

[0019]

As described above, in the conventional buffer circuit of the small-amplitude interface,
ON → OFF / OF of transistor whose output waveform is paired
There is a problem that ringing is generated due to a difference in the F → ON operation time, which causes a malfunction of the receiver and lowers reliability.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a conventional buffer circuit of a small-amplitude interface, in which a complementary signal is input, a conventional output buffer circuit is provided. It is an object of the present invention to provide an output buffer circuit that eliminates the occurrence of ringing generated in an output waveform due to a difference in operation time of a constituent transistor and improves the reliability of an interface.

[0021]

According to the present invention, in order to achieve the above object, the present invention is summarized as follows. A waveform shaping circuit is inserted in a stage preceding an output buffer to shape an input waveform, thereby forming an output buffer. Transistor ON → OFF at the same time
By turning ON / OFF → ON, occurrence of ringing is prevented.

More specifically, according to the present invention, first and second differential pairs each composed of a pair of MOS transistors are disposed so as to face a high potential side power supply and a low potential side power supply, Gate terminals of the differential pair are cross-connected to form first and second input terminals, and a connection point between the first differential pair and the second differential pair is defined as a first and a second.
And an output buffer circuit serving as an output terminal, and first and second waveform shaping circuits for inputting complementary signals input to input terminals, respectively, wherein outputs of the first and second waveform shaping circuits are output from the first and second waveform shaping circuits. The output buffer is connected to the first and second input terminals.

[0023]

Embodiments of the present invention will be described below. In a preferred embodiment of the output buffer circuit according to the present invention, referring to FIG. 1, which is a diagram for describing an embodiment described later, first and second differential pairs 101 and 102 each comprising a MOS transistor pair. Are arranged to face the higher power supply and the lower power supply, and the gate terminals of the first differential pair 101 and the second differential pair 102 are cross-connected to each other. For example, the gate of the transistor M11 of the first differential pair 101 is 2
And the gate of the transistor M12 of the first differential pair 101 is connected to the gate of the transistor M13 of the second differential pair 102, and the first and second inputs are connected. An output buffer circuit having terminals A + 'and A-' and a connection point between the first differential pair 101 and the second differential pair 102 having first and second output terminals B + and B-, and input terminals A + and A- And first and second waveform shaping circuits 103 and 104, respectively, for inputting the complementary signals input to the first and second input-output buffers, and outputs the outputs of the first and second waveform shaping circuits 103 and 104 to the first and second output buffers. It is connected to two input terminals A + 'and A-'.

In the embodiment of the present invention, the waveform shaping circuit is composed of two-stage cascaded CMOS inverters, and the preceding CMOS inverter adjusts the time for charging and discharging the input capacitance of the next-stage CMOS inverter. In this way, a desired waveform-shaped output signal waveform is obtained from the second CMOS inverter.

In the embodiment of the present invention, the above-mentioned problem can be solved by inserting a simple waveform shaping circuit in the preceding stage without changing the circuit configuration of the output buffer in the conventional configuration.

That is, in the embodiment of the present invention, the input waveform to the output buffer of the small-amplitude interface is passed through the waveform shaping circuits 103 and 104, and the L → H change time is earlier and the H → L change time is higher. Transistors forming the output buffer are simultaneously turned on by shaping the waveform into a slow, asymmetrical complementary waveform and using this as the input to the output buffer.
→ OFF / OFF → ON. As a result, it is possible to prevent the occurrence of ringing that has occurred at the time of switching the waveform.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; In the following, when the input to the output buffer is at the High level potential, the potential of the first power supply (VDD),
A description will be given of a so-called CMOS level in which the Low level is the potential (GND) of the second power supply.

FIG. 1 is a diagram showing a circuit configuration of one embodiment of the present invention. Referring to FIG. 1, in the present embodiment, the output buffer includes first and second differential pairs 101 and 102, and has the same configuration as the conventional output buffer shown in FIG. Further includes first and second waveform shaping circuits 103 and 104, and the first and second waveform shaping circuits 1 and 2
03, 104 to the two inputs A of the output buffer
+ 'And A-' are input.

First and second waveform shaping circuits 103 and 104
Is the same as the two-stage series connection of a normal CMOS inverter, but the P-channel MO of the first-stage CMOS inverter is
By making the L / W (W is the gate width, L is the gate length and the reciprocal of the W / L ratio) of the S transistor M1 smaller than the L / W of the N-channel MOS transistor M2,
The L → H waveform (rising waveform) of the output of the MOS inverter is blunted, and the H → L waveform (falling waveform) is sharpened.

Further, by inverting the logic of the output signal waveform of the first-stage CMOS inverter through the second-stage CMOS inverter, the L → H waveform is faster and the H → L
A slow waveform can be obtained.

The L / W value needs to consider the difference in electron mobility between the P-channel MOS transistor and the N-channel MOS transistor.

In FIG. 1, the capacitive element C connected to the output of the first-stage CMOS inverter is connected to the next-stage CM.
The gate input capacitance of the OS inverter may be used.

When the waveform thus shaped is input to the output buffer, in the circuit shown in FIG. 1, the paired transistors M11 and M12 are simultaneously turned ON → OFF / O.
FF → ON, and no temporary drop of output potential, that is, ringing does not occur.

FIG. 2 is a timing waveform showing the input and output waveforms of the embodiment shown in FIG. The operation of this embodiment will be described below with reference to FIGS.

As described above, the circuit configuration of the output buffer is the same as the conventional configuration shown in FIG. The transistors M12 and M14 of the output buffer have threshold levels of the same potential, and the transistors M11 and M12 alternately have two threshold levels depending on operating conditions.

In the output buffer, the waveform shaping circuits 103, 1
When the waveform shaped by 04 is input, the gate potential of the transistor M12 also passes through the threshold level at the time when the gate potential of the transistor M11 passes through the threshold level (FIG. 2).

The transistor M11 switches from ON to OFF, and the transistor M13 switches from OFF to ON.
At this time, the transistor M12 is also switched from OFF to ON, so that the current supply source is not cut off and the output potential does not drop sharply.

[0038]

As described above, according to the present invention,
Prevents ringing in the output waveform of the output buffer,
It has a remarkable effect of eliminating the cause of the malfunction.

The reason is that in the present invention, a simple waveform shaping circuit for shaping the input waveform to the output buffer is inserted in order to simultaneously operate the paired transistors of the output buffer circuit, thereby forming the output buffer. This is because the operation times of the paired transistors are the same.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a timing waveform chart showing input / output waveforms in one embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a conventional output buffer circuit.

FIG. 4 is a timing waveform chart showing an example of input / output waveforms of a conventional output buffer circuit.

[Explanation of symbols]

 Reference Signs List 101 first differential pair 102 second differential pair 103 first waveform shaping circuit 104 second waveform shaping circuit M1 to M8, M11 to M16 MOS transistors A +, A- Input terminal B +, B- Output terminal

Claims (4)

(57) [Claims] A first and a second differential pair comprising a MOS transistor pair are disposed opposite to each other between a high-potential power supply and a low-potential power supply, and gates of the first and second differential pairs are provided. An output buffer circuit in which terminals are cross-connected to form first and second input terminals, respectively, and a connection point between the first differential pair and the second differential pair is a first and second output terminal; And a first and a second waveform shaping circuit for respectively inputting a complementary signal input to an input terminal, wherein outputs of the first and second waveform shaping circuits are output from the first and second waveform shaping circuits of the output buffer. A small-amplitude interface buffer circuit connected to a second input terminal. 2. The next stage, wherein the waveform shaping circuit comprises a two-stage cascade-connected CMOS inverter, wherein the preceding stage CMOS inverter adjusts the time for charging and discharging the input capacitance of the next stage CMOS inverter. 2. A small-amplitude interface buffer circuit according to claim 1, wherein a signal having a desired waveform is obtained from the output of said CMOS inverter. 3. A first and a second MO having commonly connected sources.
A first differential pair composed of S transistors; a second differential pair composed of third and fourth MOS transistors having drains connected in common; a gate of the second MOS transistor and the third M transistor;
A first input terminal commonly connected to a gate of an OS transistor; a gate of the first MOS transistor;
A second input terminal commonly connected to a gate of the OS transistor; a first output terminal commonly connected to a drain of the first MOS transistor and a source of the third MOS transistor; An output buffer circuit comprising: a drain of a transistor and a second output terminal commonly connected to a source of the fourth MOS transistor. Complementary signals are input to the first and second input terminals. A small-amplitude interface buffer circuit to which the outputs of the first and second waveform shaping circuits are connected. 4. The first and second waveform shaping circuits are respectively constituted by cascading two stages of inverters each comprising a MOS transistor, and are provided at a connection point between an output of a preceding stage inverter and an input of a next stage inverter. 2. The small-amplitude interface buffer circuit according to claim 1, further comprising a capacitance element.