JPH0797119B2 - Voltage comparison circuit - Google Patents

Description

The present invention relates to a voltage comparison circuit, and more particularly to a voltage comparison circuit composed of a MOS-FET.

[Conventional technology]

Conventionally, various voltage comparison circuits have been devised. For example, the voltage comparison circuit described in Electronics / June2, 1982 P.144 Fig. 4 has been devised. As shown in FIG. 6, this voltage comparison circuit has first and second input terminals (IN and ▲ ▼) and an output terminal (OUT), and has a first power supply terminal (Vcc) and a second power supply terminal (Vcc). A second N-channel MOS-FET, which is composed of first and second N-channel MOS-FETs (Q _i1 and Q _i2 : i is an integer of 1 or more) connected in series between power supply terminals (GND).
A series circuit (series circuit i) having the gate of (Q _i2 ) as an input and the connection point () of the first and second N-channel MOS-FETs (Q _i1 and Q _i2 ) as an output has, for example, 6 stages, A first N configured by cascade connection (i is an integer of 1 to 6) and configuring an even-stage series circuit (series circuits 2, 4, 6).
The gate of the channel type MS-FET (Q ₂₁ , Q ₄₁ , Q ₆₁ ) is connected to the first input terminal (IN) and the odd-numbered series circuit (series circuit 1, 3,
5) The first N-channel MOS-FET (Q ₁₁ , Q ₃₁ , Q
The gate of ₅ ) is connected to the second input terminal (▲ ▼) to connect the input (gate of Q ₁₂ ) and the output () in the series circuit of the first stage (series circuit 1) and the series circuit of the final stage (series). Output () in circuit 6) is output terminal (OUT)
Configured to be connected to.

Next, the operation will be described with reference to FIG. First entry
The voltage applied to the input terminal (IN)_IN, The second input terminal
The voltage applied to (▲ ▼) is v_{▲ ▼},~of
Potential is V ~ V And N-channel MOS-FET (Q₁₁~ Q
₆₂) Β to (β_Q11~ Β_Q62), The threshold voltage is V_TTo
Then, the following equation is established in each series circuit.

If β _Q11 = β _Q21 = β _Q31 = β _Q41 = β _Q51 = β _Q61 and β _Q12 = β _Q22 = β _Q32 = β _Q42 = β _Q52 = β _Q62 , then β _Q12 = β _{From Q22} , the right side of equations 1 and 2 are equal, and the following equation holds.

Furthermore β_Q11= Β_Q21Than v Is given by

v = V + (V_IN-V_{▲ ▼}) …… Type 8 First, v_IN= V_{▲ ▼}In the case of = V Tona
It Furthermore v = V And β_Q12= Β_Q321 set and 3 sets
The right side ofHolds, and β_Q11= Β_Q31Than v = V Becomes
Similarly, v = V , v = V , v = V Becomes

Then v_{▲ ▼}Is a constant value v_INChanges when
explain. v_{▲ ▼}Is a constant value, so v_IN
Even if changes Is a constant value,
Is shown in. v Is given by equation 8 and is shown in FIG.
Has been done. v But v_IN> V_{▲ ▼}Next v
When is increased, v is satisfied in order to satisfy Equation 3. Goes down
Must be v_IN<V_{▲ ▼}Next v Is descending
In order to satisfy Equation 3, v Need to rise
It v Is shown in FIG. Similarly v_IN>
v_{▲ ▼}If v Rises, v Falls and v Rises
And output high from the output terminal (OUT), v_IN<V
_{▲ ▼}If v Is descending, v Rises and v Is descending
Output from the output terminal (OUT).

[Problems to be Solved by the Invention]

The above-mentioned conventional voltage comparison circuit has a drawback that the operation becomes unstable when a voltage is applied to the input of the voltage comparison circuit through a high impedance because the positive feedback is applied to the input. I will explain.

The MOS-FET that constitutes the voltage comparison circuit is shown in Fig. 8.
Close to the gate and drain and between the gate and source.
Raw capacity (C_GDAnd C_GS) Exists. Therefore, in FIG.
In addition, and the second input terminal (▲ ▼) is Q
₁₁, Q₃₁And Q₅₁C_GSAnd also and and the first input end
Child (IN) is Q_{twenty one}, Q₄₁And Q₆₁C_GSIs capacitively coupled with
C as shown in FIG._GSEquivalent to the impedance of
Or higher impedance (Z_OAnd Z ) Through
To the input (IN and ▲ ▼) of the voltage comparator circuit (v_OOver
And v See Fig. 10 for the operation when) is applied.
Explain. In Figure 10, t₀Then v_o<V And enter
Input terminal (IN and ▲ ▼) voltage (v_INas well as
v_{▲ ▼}) Also v_OAnd v Equal to
The potentials of ~ are determined and the output terminal (OUT) goes low.
Is being output. Then t₁At v_o, v Changes, v_o> V
And similarly v_IN, v_{▲ ▼}Also changes. v_IN, v
_{▲ ▼}And the potential of and decreases,
Also, the potentials of and start to rise. t₂And later v_Oas well as
v Is a constant value, but there is a delay, and
The potential continues to fall, and the potentials of and rise.
to continue. Where v_OIs high impedance (Z ) Through
Connected to the second input terminal (▲ ▼), and
Q₁₁, Q₁₃And Q₅₁C_GSAnd the second input terminal (▲ ▼)
Due to the capacitive coupling, the potential of
v_{▲ ▼}Is also lowered, v It becomes the following potential. same
Like v_OAlso high impedance (Z_O) Through the first input end
Connected to child (IN), and are Q_{twenty one}, Q₄₁And Q₆₁of
C_GSSince it is capacitively coupled with the first input terminal (IN),
, And v as the potential rises_INIs also raised, v
_OThe above potentials and the potentials of ~_INIs v_{▲ ▼}To
The corresponding potential is reached and high is output from the output terminal (OUT).
Be done. t₃And once the potential of ~ stabilizes, v_INIs v_OAnd so on
Descend as much as you can, v_{▲ ▼}′ Is v Is equal to
Rise as much as possible. Where the potential of is v_IN= V_OAnd v
_{▲ ▼}= V To the potential corresponding to
Potential rises slightly, and potentials rise slightly
To descend. Q at this time₁₁, Q₃₁And Q₅₁C_GSBy v
_{▲ ▼}Is raised and Q_{twenty one}, Q₄₁And Q₆₁C
_GSBy v_INHas been lowered, and
The potential rises further, and the potentials of and fall further
To do. Therefore, t_FourAt v_INIs v_OReduced to v
_{▲ ▼}Is v The output terminal (OU
The signal of (T) is inverted from high to low again. t_Fiveso
Once the potential of ~ stabilizes, v_INIs v_OIs equal to
Rise as much as possible, v_{▲ ▼}Is v As low as possible
Then v_INAnd v_{▲ ▼}Corresponding to
To do. t_FiveAfter that, the above-mentioned t₂~ T_FiveRepeat the operation and output
Takes a long time to stabilize, or the
However, there is a drawback that the output becomes unstable.

In other words, in the conventional voltage comparator circuit shown in FIG. 6 Q _11, Q
The C _{GS of 21} , Q ₃₁ , Q ₄₁ , Q ₅₁ and Q ₆₁ operate as a positive feedback capacitor, so the operation is very unstable.

[Differences from the Prior Art of the Invention]

The present invention is different from the above-described conventional voltage comparison circuit in that it operates stably even when a voltage is applied to the input through a high impedance.

[Means for Solving the Problems]

The voltage comparison circuit of the present invention comprises first and second MOS-FETs having first and second input terminals and an output terminal and connected in series between the first power supply terminal and the second power supply terminal, Second MO
It is configured by cascade-connecting a plurality of series circuits in which the gates of the S-FETs are input and the connection points of the first and second MOS-FETs are output, and a first series circuit that configures an even-numbered series circuit is formed. MO
The gate of the S-FET is connected to the first input terminal, the gate of the first MOS-FET forming the odd-numbered series circuit is connected to the second input terminal, and the input and output of the first-stage series circuit are connected. In addition, in the voltage comparison circuit in which the output of the series circuit of the final stage is connected to the output terminal, the output of the series circuit of the even stage and the second input terminal and the output of the series circuit of the odd stage and the first Has a capacitive element connected between the input terminals.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, which comprises first and second input terminals (IN and ▲ ▼) and an output terminal (OUT), and a first power supply terminal (Vcc ) And a second power supply terminal (GND) connected in series between the first and second N-channel MOS-FETs (Q _i1 and Q _i2 : i is an integer of 1 or more), and the second N-channel. Type MOS-FET (Q _i2 ) gate as input, the first and second N-channel type MOS-FET (Q _i1 and Q _i2 )
_i2 ) Series circuit with connection point () as output (series circuit i)
Are cascade-connected in six stages (i is an integer of 1 to 6)
The even-numbered series circuit (serial circuit 2,
The first N-channel MOS-FET (Q ₂₁ ,
The gates of Q ₄₁ and Q ₆₁ are connected to the first input terminal (IN) of the first N-channel type MOS-FET (Q ₁₁ , Q) which constitutes an odd-stage series circuit (series circuits 1, 3 and 5). Connect the gates of Q ₃₁ and Q ₅₁ ) to the second input terminal (▲ ▼) to connect the input (gate of Q ₁₂ ) and the output () in the series circuit of the first stage (series circuit 1), and the final stage. In the voltage comparison circuit in which the output () in the series circuit (series circuit 6) is connected to the output terminal (OUT), a series circuit (series circuits 2, 4,
6) between the output (and and) and the second input terminal (▲ ▼) and the odd-numbered series circuit (series circuit 1, 3,
The output (and) at 5) and the first input terminal (I
Capacitance elements (C ₁ , C ₂ , C ₃ , C ₄ , C ₅ and C ₆ ) are connected between N).

Next, the operation will be explained.
It is exactly the same as the case of the conventional embodiment (FIGS. 6 and 7).
Therefore, the explanation here is omitted, and as shown in FIG.
C_GSHigh impedance equal to or higher than the impedance of
Pedestal (Z_OAnd Z ) Input of the voltage comparison circuit via
(IN and ▲ ▼) voltage (v_OAnd v ) Is applied
The combined operation will be described with reference to FIG. t₀Then v_O<
v And the input terminal (IN and ▲ ▼) voltage (v_INOver
And v_{▲ ▼}) Also v_OAnd v Equals the above behavior
According to, the potentials of are determined according to the output terminal (OUT)
Row is output. Then t₁At v_O, v Is changing
v_O> V And v_IN, v_{▲ ▼}Also follows and changes. v
_IN, v_{▲ ▼}The potential of and decreases with the change of
, Or, and the potential starts rising. here
Capacitance element (C₁, C₂, C₃, C_Four, C_FiveAnd C₆) Value is Q₁₁, Q_{twenty one}, Q₃₁,
Q₄₁, Q₅₁And Q₆₁C_GSWhen set to the same value as
, And the potential drops, so Q₁₁, Q₃₁And Q₅₁C_GS
By v_{▲ ▼}Is lowered, but at the same time,
Since the potential of the₂, C_FourAnd C₆By v
_{▲ ▼}Is raised, so Q₁₁, Q₃₁And Q₅₁C_GS
By v_{▲ ▼}The fall of C₂, C_FourAnd C₆Cancel with
You can Exactly the same, and the potential of
Q because it rises_{twenty one}, Q₄₁And Q₆₁C_GSBy v_INIs raised
However, at the same time, and the potential of₁, C
₃And C_FiveBy v_INIs lowered, so Q_{twenty one}, Q₄₁And Q₆₁
C_GSBy v_INRise of C₁, C₃And C_FiveCancel with
Can t₂And the potential of ~ is determined and v_INas well as
v_{▲ ▼}Is v_OAnd v Output terminal
High is output stably from (OUT). That is, very
Power input (IN, ▲ ▼) via high impedance
Pressure (v_O, v ) Is applied, v_INAnd v_{▲ ▼}Is
Does not depend on changes in the potential of_OAnd v Determined only
Therefore, it operates very stably.

As described above, in the first embodiment of the present invention shown in FIG. 1, the voltage comparison circuit constituted by connecting the series circuits in six stages is cascaded. However, by connecting the series circuits in two stages or more, It is obvious that the same operation is performed in the configured voltage comparison circuit, and the description is omitted here.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. Instead of the capacitive elements (C ₁ , C ₂ , C ₃ , C ₄ , C ₅ and C ₆ ) shown in FIG. In the output (,,) of the series circuit (series circuits 2, 4, 6) of the second stage, the source is connected to the second input terminal (▲
N-channel MOS-FET (Q ₂₃ ,
Q ₄₃ , Q ₆₃ ) and N-channel type in which the source is connected to the output (,,) of the odd-numbered series circuit (series circuit 1, 3, 5) and the gate is connected to the first input terminal (IN). MOS-FET (Q
₁₃ , Q ₃₃ , Q ₅₃ ). In the second embodiment shown in FIG. ₃ , a series circuit is formed instead of the capacitive elements (C ₁ , C ₂ , C ₃ , C ₄ , C ₅ and C ₆ ) shown in FIG. First N-channel type MOS-FET (Q ₁₁ , Q ₂₁ , Q ₃₁ , Q
₄₁ , Q ₅₁ and Q ₆₁ ) N-channel type MOS-FET (Q ₁₃ , Q ₅₁ )
₂₃ , Q ₃₃ , Q ₄₃ , Q ₅₃ and Q ₆₃ ) are used, so positive feedback capacitance (C _{GS of} Q ₁₃ , Q ₂₃ , Q ₃₃ , Q ₄₃ , Q ₅₃ and Q ₆₃ )
There is also an advantage that the capacity equal to can be easily set. For example, N-channel type MOS-FET (Q ₁₃ , Q ₂₃ , Q ₃₃ , Q ₄₃ , Q ₅₃ and Q
₆₃ ) [Channel length (L) x Channel width (W)]
The 7th N-channel type MOS-FET (Q ₁₁ ,
_{Q 21, Q 31, Q 41} , Q 51 and Q ₆₁₎ of the [channel length (L) × channel width (W)] Positive feedback capacitor simply set to 1 / 2-2 / 3 of the [Q _13, Q _23, Q _33, Q _43, approximately equal Chi gate capacitance C _GS) of Q ₅₃ and Q ₆₃ can be set.

In FIG. 3, an N-channel MOS-FET (Q ₁₁ , Q ₂₃ , Q ₃₃ ,
Although the drains of Q ₄₃ , Q ₅₃ and Q ₆₃ ) are open, as in the i-th series circuit (series circuit i) shown in FIG. 4 (a), an N-channel MOS-FET (Q ₁₃ , Q ₂₃ , Q ₃₃ , Q
It is clear that the same efficiency can be obtained by connecting the drain and source of ( ₄₃ , Q ₅₃ and Q ₆₃ ).

Further, as in the i-th series circuit (series circuit i) shown in FIG. 4B, an N-channel MOS-FET (Q ₁₃ , Q ₂₃ , Q
It is also clear that ₃₃ , Q ₄₃ , Q _53, and Q ₆₃ ) have the same effect even if they have a structure without a drain as shown in FIG. 4 (c).

FIG. 5 is a circuit diagram showing a third embodiment of the present invention. In the first embodiment shown in FIG. 1, between the output () and the first input terminal (IN) of the series circuit 5 and in series. The capacitive element (C ₅ and C ₆ ) is connected only between the output () of the circuit 6 and the second input terminal (▲ ▼). In Fig. 5, the amplitude of the potential of and is larger than that of the potential, and the positive feedback amount by C _GS of Q ₅₁ and Q ₆₁ is also Q ₁₁ , Q ₂₁ , Q.
It is larger than the positive feedback amount by C _GS of ₃₁ and Q ₄₁ . Therefore, there is an advantage that even if the capacitive elements (C ₅ and C ₆ ) are connected to and, the element operates safely as described above and can be configured with a small number of capacitive elements.

〔The invention's effect〕

As described above, by connecting the feedback capacitor, the present invention operates stably even when a voltage is applied to the input via high impedance. Therefore, even if the power supply voltage is lowered and the output impedance of the circuit connected to the input of the voltage comparison circuit is increased, there is an effect that it is possible to operate very stably.

[Brief description of drawings]

1 and 2 are a circuit diagram showing a first embodiment of the present invention and a diagram for explaining the operation, FIG. 3, FIG. 4 (a),
(B) and FIG. 4 (c) are circuit diagrams showing a second embodiment of the present invention and diagrams showing the structure of a MOS-FET, and FIG. 5 is a circuit diagram showing a third embodiment of the present invention. FIG. 6, FIG. 7, and FIG. 10 are circuit diagrams showing a conventional example and diagrams for explaining the operation, and FIG.
FIG. 9 is a diagram showing the parasitic capacitance in the MOS-FET, and FIG. 9 is an equivalent circuit diagram of the circuit connected to the input of the voltage comparison circuit. IN, ▲ ▼ …… Input terminal, OUT …… Output terminal, Q ₁₁ , Q ₁₂ ,
Q ₁₃ , Q ₁₄ , Q ₁₅ , Q ₁₆ , Q ₂₁ , Q ₂₂ , Q ₂₃ , Q ₂₄ , Q ₂₅ , Q ₂₆ , Q ₃₁ , Q ₃₂ , Q
₃₃ , Q ₃₄ , Q ₃₅ , Q ₃₆ ... N-channel MOS-FET.

Claims (3)

[Claims] 1. A first and a second input terminal, an output terminal,
A plurality of series circuits, each of which has first and second MOS / FETs connected in series between a first power supply terminal and a second power supply terminal,
-Using the gate of the FET as an input, the first and second MOS-FETs
A plurality of series circuits having the connection point as an output, and connecting the plurality of series circuits in cascade so that the output of the series circuit of the previous stage becomes the input of the series circuit of the next stage, The gate of each of the first MOS-FETs of the series circuit is set to the first input terminal, and the gate of each of the first MOS-FETs of the series circuits of odd-numbered stages is set to the second input terminal. In each of the voltage comparison circuits, each of which is connected to the input and output of the series circuit of the first stage and the output of the series circuit of the final stage is connected to the output terminal, at least one output of the series circuit of the even stage And a second input terminal, and a capacitance element is connected between the output of the series circuit of at least one odd stage and the first input terminal, respectively. 2. The voltage comparison circuit according to claim 1, wherein the capacitance element is composed of a MOS-FET. 3. A capacitive element is connected between each of all the outputs of the even-numbered series circuits and the second input terminal,
Each of the outputs of the odd-numbered series circuits and the first circuit
The voltage comparison circuit according to claim 1 or 2, wherein a capacitance element is connected between the input terminals of.