JP3029307B2 - Program creation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program creating apparatus, and more particularly to a program creating apparatus comprising a combination of a plurality of processors (basic arithmetic units) controlled by a program. And a program for creating a signal processing circuit program capable of performing different digital data processing.

[0002]

2. Description of the Related Art As is well known, in recent years, with the development of semiconductor technology, digitization of signal processing of television images of the current system has been actively carried out. Digitizing signal processing enables stable signal processing such as modulation and demodulation and filtering, and also makes it possible to easily perform accurate time delay using a line memory or a frame memory. There are various advantages that the image quality can be improved by performing Y / C (luminance / color) signal separation or scanning line interpolation using a memory.

By the way, as signal processing becomes complicated and large-scale, developing dedicated hardware for each specific signal processing causes time and economic disadvantages. Therefore, conventionally, digital processing of a television signal has been considered to be performed using a basic arithmetic unit (hereinafter referred to as a processor) controlled by software by a program. That is, the hardware uses a standardized processor, and the processing content is to be specified by software. Therefore, when the processing content is changed, only the software needs to be changed, and the same hardware can be used for many different purposes.

In this case, since a video signal such as a television signal has a wide band, high-speed processing is required. For example, N
In the case of a TSC signal, since sampling is performed at 4 fsc (14.3 MHz), processing for each pixel must be performed within 70 ns. In other words, when a video signal processing circuit is configured using a processor, there are approximately 60 product-sum operation circuits required for Y / C signal separation and color signal processing.
60 × 14.3 = 858 MOPS (858 × 1 per second)
0 ⁶ times very fast process of operation) of is required.
For this reason, when performing video signal processing using a processor, it is important to speed up the processing using a plurality of processors.

As described above, as a method of configuring a circuit using a plurality of processors, a plurality of processors having the same structure are regularly arranged in a two-dimensional array, and data is exchanged between adjacent processors. There is a way. FIG. 12A shows a plurality of processors P
., P12,... Are arranged in a two-dimensional array. FIG. 12B shows a one-dimensional configuration portion extracted from the circuit shown in FIG. 12A for explanation. In FIG. 12, each square represents a processor, and a straight line connecting the processors is
A connection line for exchanging data between adjacent processors is shown.

In FIG. 12B, it is assumed that an input signal is input from a connection line L11. Then, after the input signal is processed by the processor P11, the connection line L1
2 to the processor P12 for further processing. Thus, each processor P11, P12,...
Repeats the operation of processing the data supplied via the connection lines L11, L12,... And outputting the data to the connection lines L12, L13,.
2,... Sequentially flow to obtain high processing performance as a whole. The two-dimensional configuration circuit shown in FIG. 12A operates in exactly the same manner as described above, but differs from the one-dimensional configuration because the processor P11 can output data to both the processors P12 and P21. Operation is complicated.

Here, the above-mentioned processor includes a control-driven type and a data-driven type. In a general control driving method, as shown in FIG. 13, execution of an instruction program is controlled by one control device 11. That is, program data is read from the program memory 12 based on the address indicated by the program counter 11a in the control device 11, and is decoded by an instruction decoder (not shown) in the control device 11.

Then, data specified by the operand section 12a in the program memory 12 is read from the data memory 13 or the I / O (input / output) port 14 under the control of the control device 11, and
The operation specified by the operation unit 12b in the
5 and the result is stored in the data memory 13 or I /
Stored in O port 14.

The next instruction to be executed is normally read from the address obtained by adding 1 to the program counter 11a, while the branch instruction is read from the address specified by the operand section 12a. As described above, in the control driving method, instructions are sequentially executed.

On the other hand, in the data driving method, the execution of an instruction program is not controlled by one control device as in the control driving method, and each instruction is executed when its operand data becomes complete. That is, as shown in FIG. 14, there is an access request and a response between the arithmetic unit 15 and the data memory 13. Then, the arithmetic unit 15 issues an access request to the data memory 13 or the I / O port 14 specified by the operand unit 12a, and the data memory 13 returns a response to the arithmetic unit 15 when the requested data is completed. After that, the calculation is executed and the program counter 11a is updated.

As described above, in the control driving method, since the program is sequentially executed under the control of the instruction specified by the program counter 11a, it is necessary to explicitly indicate the parallelism of the operation when creating the program. In contrast,
In the data driven method, an instruction is executed only when operand data is available, that is, instructions are executed one after another only according to the dependency of the operand data,
Since the parallelism inherent in the program can be extracted at the time of execution, it can be said that the program is suitable for parallel processing. The arithmetic unit 15 described above is generally composed of an ALU, an ACC (accumulator) or the like, but a detailed description is omitted.

Generally, data driven processors are connected by using a FIFO memory 16 as shown in FIG. That is, the data output from the processor 17 to the processor 18 is FI
It is stored in the FO memory 16. Therefore, the processor 1
If the timing at which the processor 8 reads data is later than the timing at which the processor 17 outputs data, the processor 18 reads the data stored in the FIFO memory 16, and conversely, the processor 18 reads the data at a timing higher than the processor 17. If the timing is earlier than the timing at which 17 outputs data, the processor 18 waits until data is input to the FIFO memory 16.

A plurality of data driven processors as described above are arranged in a two-dimensional array via a FIFO memory, and each processor is programmed to basically perform desired signal processing. Can be. Generally, development of a program to be provided to a processor is performed on a personal computer or a workstation, but programming of the processor is very complicated. In other words, the general programming language for processors is assembler, but it is necessary to be familiar with not only the grammar of the language itself but also the complex hardware architecture, and programming that is conscious of the arrangement of multiple processors is required. Therefore, it is a great burden for a signal processing engineer to program such a multiprocessor device to perform desired processing.

Here, conventional means for developing a program to be given to the processor will be described. FIG. 16 is a conceptual diagram showing a general configuration of a processor arranged on a two-dimensional array. However, this diagram shows only the most basic configuration for explanation, and actual hardware is more complicated. It is. That is, the input terminals 19, 20, 21, 22
Output data is supplied from the vertically and horizontally adjacent processors. Further, the selectors 23 and 24
One of input data from the input terminals 19, 20, 21, and 22, output data from the data memory 25, and a constant value output from the program memory 26 is selected and supplied to the ALU 27, respectively. .

The ALU 27 performs a predetermined operation on two input data. Then, the selectors 27, 29, 30,
31 selects one of the output data from the ALU 27 and the input data from the four input terminals 19, 20, 21, and 22, and outputs one of the output terminals 32, 33, 3 respectively.
Output to 4,35. These output terminals 32, 33, 34,
Reference numeral 35 is connected to each input terminal of the adjacent processor in the vertical and horizontal directions. The output data of the ALU 27 can also be written to the data memory 25. The addresses of the selectors 23, 24, 28, 29, 30, 31 and the data memory 25 are controlled according to the program contents of the program memory 26.

The program memory 26 outputs data at an address designated by a program counter (not shown), and the output data is decoded by an instruction decoder 36 to become a control signal. In actual hardware, several stages of latch circuits exist in the path from the input terminals 19 to 22 to the output terminals 32 to 35 in order to increase the speed, and the inside of the processor often performs a pipeline operation. However, they are omitted here for the sake of brevity.

Next, an assembler language for programming the processor shown in FIG. 16 will be described. First, the input terminals 19 to 22 and the output terminals 32 to 35
Will be called as follows.

Input terminals 19... Uin connected to the upper adjacent processor Input terminals 20... Din connected to the lower adjacent processor 21. Lin is connected to the adjacent processor on the output terminal 32 is connected to the adjacent processor below the output terminal 33 is connected to the adjacent processor below the output terminal 34 is connected to the right adjacent processor. rout An output terminal 35 connected to the processor adjacent to the left. lout The operation in the ALU 27 is specified as (operation) operand 1 operand 2 operand 3 (operation) operand 1 operand 2. Further, an input / output terminal name or an address of the data memory 25 is specified for each operand. For example, to add the input data from the upper and lower adjacent processors and output to the right processor, just write as add uin din rout and output the input data from the upper processor to the lower processor If so, describe as move uin dout.

Using the processor and the assembler shown in FIG. 16 described above, the transfer function H (z) = (1/4) z ^-1 + (1
FIG. 17 shows an example in which an FIR filter of (/ 2) + (1/4) z ^{+ 1} is configured. In this example, the filter is composed of 13 processors.
O memory is omitted. In this case, the program given to the processors 37, 38, and 39 in FIG. 17 is described as follows.

[0020] Here, m: 0 indicates the designation of the address 0 of the data memory 25. In this example, the operating frequency of the processor must be at least four times the input data rate from connection 40 because the program of the processor is looped with a maximum of four instructions. Further, although the loop cycle of each processor is different from that of 4, 3, 2 instructions, there is no particular problem as long as the processor is a data driven system as described above. In order to create such a program, not only the grammar of the assembler but also the address of the memory in the processor must be managed by the program creator. Programming the technician to cause the processor to perform the desired signal processing places a heavy burden on the technician.

[0021]

As described above, programming for signal processing by a processor requires not only to learn the programming language of the processor, but also to become familiar with the hardware architecture of the processor. However, since the arrangement of a plurality of processors must be taken into consideration, there is a problem that a heavy burden is imposed on a signal processing engineer.

Therefore, the present invention has been made in consideration of the above circumstances, and a signal processing engineer does not know a programming language or a hardware architecture of a processor.
Moreover, it is an object of the present invention to provide an extremely good program creating apparatus which can easily create a program for causing a processor to perform desired signal processing without being conscious of the arrangement of a plurality of processors.

[0023]

According to the present invention, there is provided a program creating apparatus in which a plurality of processors for performing a predetermined signal processing operation in accordance with a given program are arranged in a matrix, and a plurality of processors are preset in each processor. The present invention is directed to a signal processing system that performs a desired signal processing as a whole by providing and operating a program that has been provided, and that creates a program to be provided to each processor.

A storage means for storing a plurality of programs to be provided for causing the processor to perform various signal processing operations, and each signal processing executable by the processor by the plurality of programs stored in the storage means First display means for displaying a plurality of circuit graphics respectively corresponding to the contents; selection means for selecting a desired circuit graphic from the plurality of circuit graphics displayed on the first display means; A second display means for displaying the circuit graphic selected by the means in a desired area among a plurality of display areas which are set in a matrix in advance and each corresponding to the processor; and A program corresponding to each circuit graphic displayed in each display area is retrieved from the storage unit, and based on the rows and columns of the display area where each circuit graphic is displayed, It is obtained so as to include a programming means for providing to the processor corresponding to the display area.

[0025]

According to the above arrangement, a desired circuit graphic is selected from a plurality of circuit graphics displayed on the first display means and is displayed in a desired display area of the second display means. By simply creating a signal processing diagram, a program to be automatically given to each processor can be created, so that a signal processing engineer does not know the programming language or hardware architecture of the processor and is aware of the arrangement of multiple processors. Even without doing so, it is possible to easily create a program for causing the processor to perform desired signal processing.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. As described above, conventionally, a processor program is input using a keyboard using an editor on a personal computer or a workstation. In the embodiment described here, the editor is software for inputting characters. For example, Unix, which is a standard operating system of a workstation, includes an editor called vi. In this embodiment, a person who performs programming of the processor (hereinafter referred to as a user) does not need to input a program by keyboard according to the grammar of a programming language such as an assembler. By selecting, input is performed.

FIG. 2 shows the configuration of a general workstation. That is, the workstation body 4
1 includes a display device 42 made of a cathode ray tube (CRT) or liquid crystal, and a keyboard 4 as an input device.
3 and the mouse 44 are connected. Further, inside the workstation main body 41, an arithmetic unit 41a for performing an actual operation, a memory 41b for storing data necessary for the operation, a disk 41c, and its I / F (interface) 41
d etc. are provided. Of these, the memory 41b has a relatively small capacity as a temporary storage means, and the disk 41c has a large capacity. The editor is stored in the disk 41c, and is generally transferred to the memory 41b and executed when the editor is activated by operating the keyboard 43. In this embodiment, the user performs input using a signal processing component input program instead of the editor.

Hereinafter, a signal processing component input program as an input means will be described. In this description, it is assumed that the mouse 44 is used as an input device. FIG. 3 shows the entire screen configuration displayed on the display device 42.
Is a display area of a menu of the signal processing component, B is a display area for arranging a component selected from the menu, and C is a display area of a command menu for the display area B. Among them, a display example of the display area A is shown in FIG.
Is shown in In the menu of the signal processing component, a circuit diagram of twelve signal processing components and an arrow diagram for two page feeds are prepared. FIG. 4B shows a display example of the display area B. A plurality of grids each having the same size as a square surrounding each signal processing component shown in FIG. (Indicated by a broken line). FIG. 4C shows a display example of the display area C. In this example, a minimum of seven command menus are shown.

Next, the processing of the entire input program will be described with reference to the flowcharts shown in FIGS. Each menu is selected using the mouse 44. That is, when the mouse 44 is moved on the table, the pointer moves on the screen accordingly. Then, for example, the pointer moves to the display area C on the screen.
When the button of the mouse 44 is pressed when the user reaches a predetermined item, the command is selected and executed.

That is, when the command menu "save" is selected, a save process for saving the signal processing diagram created in the display area B on the disk 41c is performed, and when the command menu "load" is selected, the reverse is performed. Disk 41
The signal processing diagram stored in c is called on the screen. When the command menu "program creation" is selected, the program of the processor is created below the signal processing diagram displayed in the display area B, which will be described in detail later. In addition, the command menu "Rotate", "Move", "Delete"
Is selected, the individual signal processing components arranged in the display area B are rotated in grid units by the designation of the mouse 44,
This is the mode for moving and deleting. When the command menu “Add” is selected, a mode is set in which a new signal processing component specified by the mouse 44 is added to an empty grid in the display area B.

For example, if the button of the mouse 44 is pressed when the pointer is over the display area B on the screen, if the mode is the rotation mode, the graphic of the part indicated by the pointer is rotated by 90 degrees and rotated. Is added to the component. In this case, even if the same part is rotated twice or more, an attribute is added so that the number of times can be recognized. For example, attribute 0 is set when the rotation is 0 degree, attribute 1 is set when the rotation is 90 degrees, and attribute 2 is set when the rotation is 180 degrees. Further, in the moving mode, the moving is performed, and in the deleting mode, the deleting is performed.

When the button of the mouse 44 is pressed when the pointer is over the display area A on the screen, the pointer moves to 2
If any one of the two-page arrow diagrams is shown, the page of the component menu displayed in the display area A is sent. In the case of the addition mode, the component indicated by the pointer is added to the display area B. You.

Next, the addition processing and the program creation processing of the processing of the entire input program described above will be described in detail. First, FIG. 7 shows a flowchart relating to the additional processing. The user moves the pointer over a component to be added on the display area A, and presses a button of the mouse 44 at that position to select a component. Thereafter, the user moves the mouse 44 while keeping the button pressed, moves the pointer to a desired position on the display area B, and releases the button, whereby a component is added to the display area B.

In this case, the component is not accurately placed at the position of the pointer on the display area B, but is placed so as to fit in the grid including the pointer. At this time, if a component is already arranged in the grid including the pointer, it is set so that the component is not arranged in the grid.

By inputting the required components based on the above-described flowchart, the signal processing diagram input by the user is arranged neatly on the display area B in grid units. Will exactly match the arrangement of the processors arranged in a two-dimensional array. FIG. 1 shows a signal processing diagram on the display screen B when the FIR filter shown in FIG. 17 is input as described above. In addition, A to E and 1 to 4 in FIG. 1 indicate the positions of the grid, and may or may not be on the actual screen.

Next, the program creation processing will be described with reference to FIG. The flowchart shown in FIG.
A program for each processor is created based on the signal processing diagram input by the user as described above.
First, when the user selects "save" from the command menu shown in FIG. 4C, the input signal processing diagram is stored in the disk 41c. The file format of the disk 41c at this time is as follows, for example.

[0037] In the above file format, the first field indicates an attribute value indicating the number of rotations, the next two fields indicate the positions of parts corresponding to A to E and 1 to 4 in FIG. Indicates a part name. In the program creation process, this file is read, and the necessary processor program module is included by referring to the component name in the fourth field. As in the case of the program module of the processor, the one corresponding to each component name is prepared as a disk file as follows as in the case of the conventional example.

[0038] Then, the information of the signal processing diagram after the inclusion is as follows, and is in a form close to the program of the processor.

[0039] Next, the input / output port is changed according to the rotation attribute value of each module. That is, assuming that the attribute values correspond to 0 ° clockwise rotation 0 0 90 ° clockwise rotation 1 180 ° clockwise rotation 2 270 ° clockwise rotation 3 The output port is changed according to the following rules.

When the attribute value is 0: No change When the attribute value is 1: Change l to u ... Change u to r ... Change r to d ... Change d to l When the attribute value is 2 ... l Change to r… Change u to d… Change r to l… Change d to u When the attribute value is 3… Change l to d… Change u to l… Change r to u… d to r When the information is changed according to the above rules, the information of the signal processing diagram is changed as follows. At this point, the rotation attribute value is not shown because it is not necessary.

[0041] Then, these are further formatted and formed into an assembler program of the processor. If you write a multiprocessor program using the following format, By the format shaping, the following assembler program of the processor is output.

[0042] The case where the processing content of each processor is relatively small, such as a coefficient unit that performs only multiplication, has been described above. Next, the above-described program creation processing is applied to the processing of one processor. A case where the processing capacity is increased and the processing scale is further increased will be described. As the screen configuration of the signal processing component input program that is the input means,
3 and FIG. 4, and the flowchart of the component input program may be the same as FIG. 5 and FIG. The processing (addition processing) of arranging the signal processing components in the flowcharts shown in FIGS. 5 and 6 will be described with reference to FIG.

The flowchart shown in FIG.
Is similar to the flowchart shown in FIG. In the case of FIG. 7, if a component has already been arranged on the grid including the pointer at the time when the button of the mouse 44 is pressed, no new component is arranged. When the condition 1 is satisfied, a new component is superimposed on the already arranged component. The condition 1 is determined as follows. First, a constant 1 is assigned to each signal processing component of the menu in the display area A, and a variable 1 and a variable 2 are assigned to each grid in the display area B. The constant 1 indicates the number of programs for each component as follows.

Part name Constant 1 wire1... 4 delay1... 3 coef1... 2 Variable 1 of each grid has 0 as an initial value, and the value indicates how many parts are placed one upon another. Therefore, each time one component is placed, it is updated by the following equation.

Variable 1 (n + 1) = Variable 1 (n) +1 Equation (1) On the other hand, Variable 2 also has 0 as an initial value, and performs processing of all the parts placed on the grid. Shows the total number of instructions in the case of For this reason, each time one part is superimposed, it is updated by the following equation.

When variable 1 = 0 Variable 2 (n + 1) = constant 1 of newly placed component ... Equation (2.1) When variable 1 is other than 0 Variable 2 (n + 1) = variable 2 ( n) + Constant 1-1 of newly placed component ... Equation (2.2) Also, the maximum number of instructions is set according to the processing capability of the processor. This maximum number of instructions is the ratio of the operating frequency of the processor to the input signal rate to the processor. For example, if the input signal rate is 14.3 MHz obtained by sampling the NTSC signal at 4 fsc, and the processor operates at 10 times the same, the input signal rate is set to 10.

In the above case, it is determined whether or not a component is further placed on the grid on which the component is already arranged, under the following conditions.

Variable 2 (n) + Constant 1 of newly placed component
−1 ≦ maximum number of instructions If the above condition is satisfied, that is, if it can be determined that the processing of the processor can be performed in time even if components are newly placed, components are placed and variables 1 and
Update 2. If the condition is not satisfied, the user is notified that no more parts can be placed. By applying the above-described flowchart shown in FIG. 7 as shown in FIG. 9, it is possible to input a predetermined number of components in a superimposed manner.

FIG. 10 shows a display form of the display area A at this time. That is, the grids 2A to 2E in FIG.
5 parts on the grid 2A, 5 parts on the grids 3A to 3E on the grid 3A, and 5 parts on the grids 4A to 4E.
This shows a state in which three parts are arranged so as to be superimposed on the grid 4A. The numbers in the grids 2A, 3A, and 4A indicate the number of signal processing components overlapped.

Next, FIG. 11 shows a flowchart in the case where the overlapping arrangement of a plurality of parts is permitted in the program creation processing shown in FIG. It is possible to cope only by adding four processes as compared with FIG. In other words, one field is added to the file format of the signal processing diagram input by the user, indicating at what position the component is superimposed on the same grid.

[0051] As described above, when this file is read, the necessary program modules are included, and the input / output ports are changed according to the rotation attribute, the result is as follows.

[0052] These are rearranged in the order of earlier (smallest) arrangement of the matrices for the same program module, that is, for each component placed on the same grid (hereinafter referred to as a component in the same grid). However, in this example, there is no need because it is already lined up. Next, the memory used by the program modules in the same grid is reallocated. In this example,
Since four of the five parts of the grid 2A are programs that use the address 0 of the memory, different data is overwritten at the same address as it is. Therefore, the memory addresses are sequentially reassigned to 0 to 3 as follows.

[0053] Further, from the first program module to the last module in the same grid, inspection is performed, and for processors that are adjacent to each other and transmit / receive data using the input / output port, the input / output port is set to the next one. Allocate to memory according to rules.

The nth processor outputs to rout, and n + 1
The second processor is inputting from lin… Change each rout, lin to a memory at a common address.

The n-th processor outputs to lout, and n + 1
The second processor is inputting from rin… Change each lout, rin to the memory at the common address.

The n-th processor outputs to dout, and n + 1
The second processor is inputting from uin ... Change each dout, uin to the memory of the common address.

The n-th processor outputs to uout, and n + 1
The second processor is inputting from din… Change each uout, din to a common address memory.

When the input / output ports are reallocated to the memory according to the above rules, the following is obtained.

[0059] Furthermore, if you change the process from the first to the last in the same grid to be repeated in one loop, Becomes

Finally, if the format is shaped in the same manner as in the above-described example to form a processor program, Becomes

Therefore, according to the above embodiment, a signal processing system engineer can describe a desired signal processing program simply by arranging signal processing components using input means on a workstation. Since each component is in a square frame and can be arranged only in a grid unit of the square size, each signal processing component is arranged in an array on the screen without the input user being particularly conscious. Based on the position (row / column) of each signal processing component, the type of component, and the number of times the graphic has been rotated in the drawing arranged in this manner, the processor of the processor that performs the signal processing desired by the input user The program is automatically created, and even an unskilled signal processing system engineer can easily and quickly create a signal processing program by the processor without paying special attention to the processor, and can concentrate on the development of the signal processing algorithm. In addition, the effect that the signal processing content by the program can be visually grasped can be expected.

The present invention is not limited to the above embodiment, but can be implemented in various modifications without departing from the spirit and scope of the invention.

[0063]

As described in detail above, according to the present invention,
A signal processing engineer can easily create a program for causing a processor to perform desired signal processing without knowing the programming language or hardware architecture of the processor and without being aware of the arrangement of a plurality of processors. An extremely good program creation device can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a workstation to which the embodiment is applied;

FIG. 3 is a plan view showing a display screen of the embodiment.

FIG. 4 is a plan view showing details of the display screen.

FIG. 5 is a flowchart showing the overall operation of the embodiment.

FIG. 6 is a flowchart showing the overall operation of the embodiment.

FIG. 7 is a flowchart showing additional processing of the embodiment.

FIG. 8 is a flowchart showing a program creation process of the embodiment.

FIG. 9 is a flowchart showing another example of the additional processing.

FIG. 10 is a plan view showing a display screen in another example.

FIG. 11 is a flowchart showing another example of the program creating process.

FIG. 12 is a block diagram showing an arrangement of processors.

FIG. 13 is a block diagram showing the structure of a control-driven processor.

FIG. 14 is a block diagram showing the structure of a data-driven processor.

FIG. 15 is a block diagram showing the connection between processors of the same data drive system.

FIG. 16 is a block diagram showing a detailed structure of the data-driven processor.

FIG. 17 is a block diagram showing an FIR filter constituted by a processor.

[Explanation of symbols]

11: control device, 12: program memory, 13: data memory, 14: I / O port, 15: arithmetic device, 16
... FIFO memory, 17, 18 ... Processor, 19-2
2: Input terminal, 23, 24 ... Selector, 25: Data memory, 26: Program memory, 27: ALU, 28-
31 selector, 32-35 output terminal, 36 instruction decoder, 37-39 processor, 40 connection line, 41
... Workstation unit, 42. Display device, 43. Keyboard, 44. Mouse.

Continuation of front page (56) References JP-A-4-274518 (JP, A) Perez, "Graphical Development System for DSP Applications," Midcon '87 Conference Record (1987), P.S. 292-302, Proc. Of the 1990 IEICE Autumn National Convention, 1990-9. 6- 258-260 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/06

Claims (3)

(57) [Claims] 1. A plurality of processors that perform a predetermined signal processing operation according to a given program are arranged in a matrix, and a predetermined program is given to each processor to operate the processor. In a signal processing system for performing the above signal processing, in a program creating apparatus for creating a program to be given to each processor, a plurality of programs to be given to cause the processor to perform various signal processing operations are stored. Storage means; first display means for displaying a plurality of circuit graphics respectively corresponding to the respective signal processing contents executable by the processor by a plurality of programs stored in the storage means; and first display means. Selecting means for selecting a desired circuit graphic from the plurality of circuit graphics displayed in Second display means for displaying the circuit graphic selected by the selection means in a desired area among a plurality of display areas which are set in a matrix in advance and each correspond to the processor, and the second display means The program corresponding to each circuit graphic displayed in each display area of the means is retrieved from the storage means, and based on the row and column of the display area in which each circuit graphic is displayed, a program corresponding to each display area is sent to a processor corresponding to each display area. And a program creating means. 2. The method according to claim 1, wherein the second display unit includes a unit configured to rotate the circuit graphic displayed in the display area by a predetermined angle, and the program creating unit controls the rotation amount of the circuit graphic. 2. The program creating apparatus according to claim 1, further comprising means for rewriting a data input / output port of a program provided to the processor corresponding to the circuit graphic based on the circuit graphic. 3. The display device according to claim 2, wherein the second display unit superimposes the plurality of circuit figures on the display area,
2. The program creating means according to claim 1, further comprising means for rewriting a memory address of a program to be given to the processor corresponding to the circuit graphic based on an order in which the circuit graphics are superimposed. Program creation device.