JP3031186B2 - Random block display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random block display control device used in video equipment, game equipment, and the like when two screens are gradually changed from one to the other while the two screens are superimposed.

[0002]

2. Description of the Related Art Image processing called a random block is a kind of image dissolving function. A screen of one frame or one field is divided into a plurality of blocks.
The block in which the image signal is displayed and the block in which the second image signal is displayed are randomly assigned, and as the frame or field advances, the block in which the first image signal is displayed and the second image signal This is a method of controlling the synthesis of the first and second image signals so that the display screen is gradually switched from the first screen to the second screen by changing the ratio of the block in which the signal is displayed. .
Conventionally, this random block is a CPU (Central Proc
essing unit) is performed by randomly allocating the first image signal and the second image signal in block units and temporarily storing the synthesized image signal in a frame memory or the like.

[0003]

However, the above-described conventional random block display control device has a problem that the load on the CPU is large because the CPU sequentially executes processing necessary for synthesizing image signals according to a program. . Also, a large-capacity memory such as a frame memory is required. Furthermore, there is a problem that the method cannot be applied to a moving image that requires real-time properties.

The present invention has been made in view of the above problems, and provides a random block display control device capable of reducing the load on a CPU, realizing control in real time without requiring a large-capacity memory. The purpose is to do.

[0005]

Means for Solving the Problems A random according to the present invention
The block display control device divides one screen into a plurality of blocks.
A block in which the first image signal is displayed and a second image signal.
Randomly sort the image signal display block
Thereby, the first image signal and the second image signal
Block display control device that displays a composite image in one screen
Initialized by the applied horizontal synchronization signal
N-bit M-sequence pseudo-random numbers into each block in the horizontal direction
Random number generation means for generating the corresponding horizontal synchronization signal;
Signal corresponding to each block in the vertical direction based on the
And n-bits constituting the random number according to this signal.
Selection method for sequentially selecting m-bit data from data
And the m-bit data^mChange to bit data
And a decoder that converts ^mBit data
Gate control according to the gate control data, and
A gate means for outputting a selection signal of a second image signal;
The first image signal and the second image signal according to the selection signal of
Switching means for switching between image signals in real time
It is characterized by that.

[0006]

According to the present invention, based on the horizontal synchronizing signal,
An n-bit random number for eliminating horizontal regularity is generated from the random number generating means in correspondence with each block in the horizontal direction,
According to a signal corresponding to each block in the vertical direction, the selection means sequentially selects m-bit data from the n-bit data constituting the random number. As a result, m-bit data from which regularity in the horizontal and vertical directions is eliminated is allocated to each block constituting one screen. Converts the data of the m bits into 2 ^m-bit data, the 2 ^m
By performing gate control on the bit data in accordance with predetermined gate control data, a selection signal is output so as to select a block to which specific m-bit data is allocated. According to this selection signal, the first image signal and the second image signal are switched in real time. The display screen can be gradually switched from the first image to the second image by gradually increasing the number of m-bit data to be selected depending on how to provide the gate control data. According to the present invention, since the switching signal is generated by the dedicated circuit, the load on the CPU can be reduced. Also,
No large-capacity memory such as a frame memory is required. Further, since the screen can be controlled in real time, it can be applied to a moving image.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a random block display control device according to one embodiment of the present invention.

In this embodiment, 2 dots (horizontal) × 2 lines (vertical) will be described as one unit block. This means that if one screen is composed of, for example, 512 dots × 192 lines, one screen is 256 × 96 (=
24576) means to divide into blocks. Then, the screen displayed on the monitor is changed from the first screen (the first screen corresponds to the first image signal VA) to the second screen (the second screen corresponds to the second image signal VB). ), Each block is supplied with either the first image signal VA or the second image signal VB corresponding to the position of each block. At this time, to which block the first image signal VA or the second image signal VB is supplied is determined at random. Further, the ratio of the first screen / second screen to the entire screen is changed as time elapses. That is, at the beginning of screen switching, the first image signal VA is supplied to all blocks, and then the second image signal VB is supplied.
Is controlled so as to increase the proportion of blocks to which is supplied over time, for example, every time a frame / field is switched.

This random block display control device has four
Random counter 1 to generate in correspondence with the pseudo random number bit to each block in the horizontal direction, and ₄ C ₂ selector 2 for selecting the 2-bit data from the 4-bit pseudo-random number,
A decoder 3 for decoding the 2-bit data, a gate 4 for gating the output of the decoder 3, and ₄ C ₂ controller 5 and the gate controller 6 for controlling ₄ C ₂ selectors 2 and gate 4, respectively, from the gate 4 A switch 7 switches between the image signal VA and the image signal VB in real time according to the output selection signal Sel.

FIG. 2 is a circuit diagram showing a configuration of the random counter 1 in the same device, and FIG. 3 is a diagram showing pseudorandom numbers output from the random counter 1. As shown in FIG. 3, this random counter 1 has a 16-block period as one cycle and all bit patterns have the same probability while eliminating the horizontal regularity, corresponding to each block position in the horizontal direction. This is an M-sequence (Max-Length) counter that generates a 4-bit pseudo random number that appears once (in the example).
Although not shown, each flip-flop 11a, 15a
To 15d, a block clock (clock indicating block division) obtained by dividing the dot clock by １ ／ is given. When the horizontal synchronization signal Hsync is input,
D flip-flop 11 in synchronization with the block clock
a, a horizontal synchronizing signal detecting section 11 composed of an inverter 11b and an AND gate 11c detects a rising edge of Hsync, and outputs D flip-flops 15a-1 through an OR gate 12, an inverter 13 and AND gates 14a-14c.
"1000" is preset in 5d. Thereafter, according to the block clock, the D flip-flops 15a to 15d
Are sequentially shifted, and the inverters 16,
Data circulates through OR gates 17, 18, NOR gate 19, AND gate 20, and OR gate 12, and 4-bit pseudo random number data A0 to A3 as shown in FIG.
Are generated for one horizontal period corresponding to each block in the horizontal direction so as to eliminate the regularity in the horizontal direction. Although only the first to sixteenth blocks are shown in FIG. 3, the same pseudo-random number data A0 to A3 as the first to sixteenth blocks are repeatedly output from the seventeenth block to the sixteenth block as one cycle. Is done. Hereinafter, similarly, the same pseudo-random number data A0 to A3 are repeatedly output after being initialized by the applied horizontal synchronization signal Hsync.

FIG. 4 shows a ₄ C ₂ selector 2 in the device.
And FIG. 5 is a truth table thereof. ₄ C
_Second selector 2 in accordance with the selector control signals S2~S0 from ₄ C ₂ controller 5 described later, 4-bit pseudo-random number data output from the random counter 1 A0～A
This is a circuit for selecting 2-bit data from among 3 as data B0 and B1, and has the following configuration, for example.

That is, among the data A0 to A3 input from the random counter 1, A0 and A1 are the switches 21a
A2 and the output of the switch 21a are input to the switch 21b, and the output of the switch 21b is input to the data B0.
Is output as A1 and A2 are switches 21c.
A3 and the output of the switch 21c are input to the switch 21d, and the output of the switch 21d is input to the data B1.
Is output as Switches 21a to 21d are switched according to selector control signals S2 to S0. FIG.
As shown in the figure, the selector control signals S2 to S0 are "00".
"Repeated a value up to, ₄ C ₂ selector 2 in response to this, the input data" 1 "from" 110 A1, A0 '~
“A3, A2” is repeatedly selected as 2-bit output data B0, B1. That is, the selector control signals S2 to S2
While S0 changes from "001" to "110", all combinations for selecting two from the input data A0 to A3 are generated as output data B0 and B1. Note that AN
The D gate 22 outputs the signal B0 when S1 and S2 are "11".
A2 is unconditionally selected as an AND gate 23 and O
The R gate 24 outputs the output B when S1 and S2 are "00".
It is provided to select A0 unconditionally as 0.

FIG. 6 is a circuit diagram showing the configuration of the ₄ C ₂ controller 5 in the same device. ₄ C ₂ controller 5
Are the outputs S2 to S0 at the rise of the vertical synchronization signal Vsync.
Is preset to “001”, and the outputs S2 to S0 are changed to the next values at two risings of Hsync (vertical width of one block). That is, first, the vertical synchronization signal Vsync
Is input, the detecting section 31 detects the rise,
“001” is set in the counter unit 33 including the counters 33 a to 33 c via the R gate 32.

Next, when the horizontal synchronizing signal Hsync is inputted, its rising is detected by the detecting section 34 and the counter 35 is counted up. When the counter 35 counts the rising detection pulse signal of the horizontal synchronization signal Hsync twice, the counter 35 outputs “1”. This output is provided to the counter unit 33 via the AND gate 36. The counter unit 33 counts these and selects the selector control signals S2 to S
Change 0. The counter unit 33 includes a counter 33b,
When the data of 33c becomes 1 and the AND gate 37 becomes active, the AND gate 38 and the OR gate 32
Is initialized via

Therefore, the selector control signals S0 in the upper and lower columns in FIG. Hereinafter, similarly, selector control signals S2 to S0 corresponding to each block in the vertical direction are generated based on the applied horizontal synchronization signal. The clock to the counter unit 33 is output for each block in the vertical direction, and is also output to the gate controller 6 as a shift signal Shift.

FIG. 7 is a circuit diagram showing the configuration of the decoder 3, gate 4, and gate controller 6 in the same device. As shown in the truth table of FIG.
₄ C _2-bit data B0 input from the selector 2,
B1 is a circuit that decodes B1 into 4-bit data C0 to C3 in which the position indicated by B0 and B1 is “1”. For example, an inverter 42 that inverts data B0 and B1
a, 42b and B1, B0 are "11", "10", "0".
A, which outputs "1" when "1" and "00" respectively
It is composed of ND gates 41a to 41d.

The gate 4 receives a signal from the decoder 3
This is a circuit that gate-controls bit data C0 to C3 according to gate control data D0 to D3 and a shift signal Shift input to a gate controller 6 described later, and outputs a selection signal Sel of image signals VA and VB. 4 AND gates 51a-51 for outputting the logical product of the outputs C0-C3 of the third gate and the output of the gate controller 6
and an OR gate 52 for outputting the logical sum of these outputs
It is composed of

The gate controller 6 outputs a load signal Lo.
ad, the gate control data D0 to D3 are ANDed.
The gates 61a to 61c, the OR gate 61d, and the D flip-flop 61e are read into the gate unit 61 and the gate units 62 to 64 having the same configuration, respectively.
The data held in the gate units 61 to 64 is shifted according to the shift signal Shift.

FIGS. 9 to 12 are diagrams showing random blocks generated by the random block display control device configured as described above. Here, (horizontal) × (vertical) is shown as 16 × 12, but in practice, this is repeated in the horizontal and vertical directions using this as a reference unit.
FIG. 9 shows the gate control data “D3, D2,
D1, D0 "is" 0001 ". In the first block row including the first line and the second line, D0
Only passes through the gate 4 when the decoder output C0 corresponding to "1" becomes "1", and Sel becomes "1". In the first block row, since ₄ C ₂ selector 2 selects the data B1, B0 as A1, A0, A1, A0 is "00"
(C0), that is, “0100” (4
H), "1100" (CH), "1000" (8H),
3,14,1 from left where "0000" (0H) occurs
Only the 5th and 16th hatched blocks display the image signal VB.

Next, in the second block row composed of the third and fourth lines, the output of the gate controller 6 is shifted to "0010" by the shift signal Shift, so that the decoder output C1 becomes "1". Only when this happens, Sel becomes "1". In the second block column, ₄ C
_{(2) Since the} selector ₂ selects A2 and A0 as the data B1 and B0, pseudo random numbers in which A2 and A0 are "01" (C1), that is, "0001" (1H) and "1001"
(9H), “0011” (3H), “1011” (B
Only the first, fourth, fifth and tenth hatched blocks from the left where H) occurs display the image signal VB.

As described above, 2-bit data B0 and B1 randomized in the horizontal and vertical directions are allocated to each block constituting one screen, and which data B0 and B1 is assigned to each block in the vertical direction. Since the selection is switched, it is possible to generate a random block uniformed over one entire screen. That is, if only fixed specific m-bit data is selected in one screen, the selected block may be biased in one screen. However, based on a signal corresponding to each block in the vertical direction, If the gate control data is shifted, m-bit data selected for each block in the vertical direction is switched, and a block in which the first image signal is displayed and a block in which the second image signal is displayed are displayed. Are uniformed within one screen, and selection bias can be reduced. Similarly, FIGS. 10 to 12 respectively show the gate control data “D3, D
2, D1, D0 "are" 0010 "," 0100 "," 1 ".
000 ".

Since all the bit patterns appear as the pseudo-random numbers A0 to A3, when these four screens are overlapped, all the blocks are always selected once. Therefore, the gate control data “D3, D2, D1,
D0 ”to“ 0001 ”,“ 0011 ”,“ 0111 ”,
When given as “1111”, the screen can be gradually switched from the image signal VA to the image signal VB. In addition, by giving the gate control data as shown in FIGS. 9 to 12, the effect of flashing the screen can be obtained.

The gate control data D0 to D3 and the load signal Load can be set as write signals from the CPU to increase the degree of freedom in setting, but may be supplied from hardware such as a counter. .
Further, by increasing or decreasing the load timing of the gate control data D0 to D3, it is possible to increase or decrease the screen switching timing. Furthermore, if the output switching timing of the random counter 1 can be adjusted, the horizontal block width can be varied. Similarly, the shift signal Shi of the ₄ C ₂ controller 5
If the output timing of ft can be adjusted, the vertical block height can be varied.

[0024]

As described above, according to the present invention,
Initialized by the horizontal sync signal to eliminate horizontal regularity
The n-bit M-sequence pseudo-random number to be divided
And generate the random numbers.
Select m-bit data from n-bit data
And eliminating vertical regularity,
M-bit data is randomly distributed to each block,
This m-bit data is 2 ^mDecode to bit data
After that, gate control according to the specified gate control data
Thus, the first and second image signals are real-timed.
CPU load is reduced by selecting
Large-capacity memories such as frame memories
It is not necessary and can be applied to moving images.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a random block display control device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a random counter in the device.

FIG. 3 is a diagram showing pseudo random numbers generated by the counter.

4 is a circuit diagram showing a configuration of ₄ C ₂ selector in the apparatus.

FIG. 5 is a diagram showing a truth table of the selector.

6 is a circuit diagram showing a ₄ C ₂ controller configuration in the apparatus.

FIG. 7 is a circuit diagram showing a configuration of a decoder, a gate, and a gate controller in the device.

FIG. 8 is a diagram showing a truth table of the decoder.

FIG. 9 is a diagram for explaining generation of a random block signal in the embodiment.

FIG. 10 is a diagram for explaining generation of a random block signal in the embodiment.

FIG. 11 is a diagram for explaining generation of a random block signal in the embodiment.

FIG. 12 is a diagram for explaining generation of a random block signal in the embodiment.

[Explanation of symbols]

1 random counter, 2 ... ₄ C ₂ selectors, 3 ... decoder, 4 ... gate, 5 ... ₄ C ₂ controller, 6 ... Gate Controller, 7,21A～21d ... switch, 11,
31, 34... Detecting sections, 11a, 15a to 15d, 61e
... D flip-flops, 11b, 13, 16, 42a,
42b... Inverter, 11c, 14a to 14c, 20,
22, 23, 36 to 38, 41a to 41d, 51a to 5
1d, 61a to 61c: AND gate, 12, 17, 1
8, 24, 32, 52, 61d OR gate, 19, 6
5: NOR gate, 33: counter unit, 33a to 33
c, 35: counter, 61 to 64: gate unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G09G 5/00 530 A63F 13/00 H04N 5/262 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A screen is divided into a plurality of blocks, and a first
A random block for combining and displaying the first image signal and the second image signal in one screen by randomly assigning a block in which the image signal is displayed and a block in which the second image signal is displayed In the display control device, a random number generating means for generating an n-bit M-sequence pseudo-random number initialized by a given horizontal synchronization signal in correspondence with each block in the horizontal direction; Selecting means for generating a signal corresponding to the block and sequentially selecting m-bit data from the n-bit data constituting the random number in accordance with the signal; and converting the ^m- bit data into 2 ^m- bit data a decoder, and gate the data of the 2 ^m bits according to a predetermined gating data, said first and second image signals of the selection signal A gate means for outputting a random block display control device characterized by comprising a switching means for switching between said second image signal and the first image signal in real time according to the selection signal.