JP3034348B2 - Semiconductor device and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an electrode wiring in the manufacturing process.

[0002]

2. Description of the Related Art Self-aligned silicide (SALICID)
E) A method for manufacturing an electrode wiring using a technique is described in, for example, "Solid State Technology", April 1987, 155-1.
It is well known as shown on page 62 and is described with reference to FIG. In FIG. 3, the silicon substrate 11
Active area 1 separated by field oxide film 12
3, a silicon diffusion layer 14 and a gate oxide film 15
And conductive polysilicon 16 and sidewall 1
A substrate having a gate electrode 17 consisting of 6 'is made (FIG. 3a).

[0003] Titanium 1 is deposited on the wafer by sputtering.
8 is deposited to a thickness of about 100 nm (FIG. 3b) and heat-treated in nitrogen at about 600 ° C. for 30 seconds to form titanium monosilicide 1 on the surface of silicon diffusion layer 14 and conductive polysilicon.
9 (FIG. 3c).

Next, unreacted titanium 18 is converted into NH ₄ OH + H ₂
Removed with a mixture of O ₂ + H ₂ O and
Heat treatment at 30 ° C. for 30 seconds to form titanium monosilicide 19
Into a low resistance and stable disilicide 20 (FIG. 3).
d).

Subsequently, an insulating film 21 is deposited, and a contact hole 22 is formed by using a photolithography technique (FIG. 3E).

[0006] Finally, an Al-based alloy 23 is deposited by a sputtering method, and an electrode wiring is formed using photolithography technology to complete it (FIG. 3F). In this case, the wiring has an Al-based alloy single layer structure.

[0007]

However, the above-mentioned method requires two heat treatments for silicidation to obtain a desired silicide, and it is necessary to remove unreacted substances, which complicates the process. . Further, the silicide layer of the silicon diffusion layer tends to be formed thick by two heat treatments, but in this case, a shallow junction may be broken. Further, since the wiring has an Al alloy single-layer structure, there is a problem related to reliability as the wiring becomes finer, for example, disconnection due to current stress (electromigration).
And a problem of resistance increase (stress migration) due to defects due to film stress. This problem has a possibility of deteriorating the reliability of each semiconductor element.

According to the present invention, a shallow junction is destroyed by a simple process in order to eliminate the problems of the above-mentioned complicated processes, the destruction of the junction due to the increase in the thickness of the silicide layer, and the deterioration of the reliability of the single-layer Al alloy wiring. It is an object of the present invention to provide a method for forming a highly reliable wiring without obtaining a highly reliable semiconductor device.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A wiring layer comprising a first refractory metal layer having a tensile stress formed in a lower layer and a second refractory metal layer having a lower resistance than the first refractory metal formed in an upper layer. . According to the method for manufacturing a semiconductor device of the present invention, a thin high-melting-point metal film having a tensile stress having a tendency to suppress silicidation is formed by sputtering in order to suppress the thickness of silicide, and then a low-resistance metal film having a lower resistance is formed. After forming the refractory metal film by sputtering, a shallow silicide layer is formed between the refractory metal film and the thin refractory metal film by heat treatment. An electrode is provided on a low-resistance film.

[0010]

In the semiconductor device and the method of manufacturing the semiconductor device according to the present invention, the tendency of the refractory metal film for forming silicide to be silicidated is controlled by optimizing the sputtering conditions to control the film stress, thereby increasing the tensile stress at which silicidation is difficult to occur. A laminated structure of a melting point metal film and a high melting point metal film having a neutral stress lower in resistance than this film is obtained, and good electrical connection between the electrode and the silicon diffusion layer is obtained as a whole.

[0011]

FIG. 1 is a process diagram showing one embodiment of the present invention. A field oxide film 202 is formed on a silicon substrate 201.
Then, an active region 203 is formed, and a silicon diffusion layer 204, a gate oxide film 205, and a gate electrode 207 made of conductive polysilicon 206 are formed thereon to form a substrate (FIG. 2A).

On this substrate, non-doped silicate glass (NSG) and borophosphosilicate glass (BPSG) are deposited as insulating films 208 to a thickness of 150 nm and 500 nm, respectively, by CVD, and contact holes 209 are formed by photolithography. (Fig. 1
b).

Next, by using a sputtering method and changing the conditions, two tungsten layers having different stresses are formed. First, DC power 1kW, argon pressure 17.5m
The tungsten film 210 having a tensile stress of about 1
Deposit 00 nm (FIG. 1c). By making the tungsten film 210 have a tensile stress, a silicidation reaction with the underlying diffusion layer 204 is less likely to occur.

Subsequently, DC power of 2 kW and argon pressure of 17.
Under the condition of 5 mTorr, the tungsten film 2 having a tensile stress is used.
Neutral stress tungsten film 2 having a resistance lower than 10
11 is deposited to a thickness of about 200 nm (FIG. 1d).

Next, after the electrode wiring 212 is formed by using the photolithography technique, a heat treatment is performed in nitrogen at 800 ° C. for 30 seconds to thinly silicide (230) the surfaces of the silicon 204 and 206 to complete the process.

FIG. 2 shows the relationship between the stress of the tungsten film and the specific resistance.

In the above, the film 210 using tungsten is used.
211, but other refractory metals such as vanadium, chromium, manganese, iron, cobalt, nickel,
Copper, zirconium, molybdenum, palladium, silver, hafnium, platinum, and gold may be used. Further, the formation of such a high melting point metal film can be easily controlled by using sputtering, but not limited thereto, and for example, vacuum deposition, vapor phase growth, or the like can be used.

[0018]

As described above, the semiconductor device of the present invention has a laminated structure of a high melting point metal film having a tensile stress which is unlikely to be silicided and a high melting point metal film having a neutral stress having a lower resistance than this film. As a result, a good electrical connection between the electrode thereon and the silicon diffusion layer can be obtained. Further, according to the method for manufacturing a semiconductor device of the present invention, a tungsten film having a tensile stress that is unlikely to be silicided and a tungsten film having a neutral stress having a lower resistance than that are formed as a laminated structure by changing the sputtering conditions. In a simple process, only the silicon contact portion can be thinly silicided by self-alignment, and low-resistance contact characteristics can be realized without breaking even at a shallow junction. Further, the present invention can be applied to word lines and wirings as they are, and high reliability and low resistance wirings can be formed.

[Brief description of the drawings]

FIG. 1 is a process chart showing one embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between tungsten stress and specific resistance.

FIG. 3 is a process diagram showing an example of a conventional self-aligned silicide technique.

[Explanation of symbols]

 Reference Signs List 201 silicon substrate 202 field oxide film 203 active region 204 silicon diffusion layer 205 gate oxide film 207 gate electrode 208 insulating film 209 contact hole 210 tensile stress refractory metal film 211 neutral stress refractory metal film 211

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-109651 (JP, A) JP-A-4-280627 (JP, A) JP-A-4-56214 (JP, A) JP-A-3-56 293766 (JP, A) JP-A-2-22832 (JP, A) JP-A-2-205666 (JP, A) JP-A-2-228034 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/28 H01L 21/336 H01L 21/768 H01L 29/78

Claims (3)

(57) [Claims] In a semiconductor device, a first refractory metal layer having a tensile stress formed in a lower layer, and a second refractory metal layer formed in an upper layer and having a lower resistance than the first refractory metal. A semiconductor element having a wiring layer comprising: 2. The semiconductor device according to claim 1, further comprising a silicide layer below said first refractory metal layer. 3. A method of manufacturing a semiconductor device, comprising: forming a gate electrode on a semiconductor substrate; forming an insulating film on the semiconductor substrate; forming a contact hole in the insulating film; Depositing a first refractory metal film having a stress; depositing a second refractory metal film having a lower resistance than the first refractory metal film on the first refractory metal film; Patterning the first and second refractory metal films.