JP3036115B2 - Digital to analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having a built-in linearity evaluation circuit.

[0002]

2. Description of the Related Art Conventionally, such a digital-analog converter has a digital section on the input side and an analog section on the output side, and is used for linearity measurement and the like.

FIG. 6 is a diagram of a linearity measuring system using a digital-to-analog converter for explaining an example of the prior art. As shown in FIG. 6, in the conventional linearity measurement system of the digital-to-analog converter 1A, an external digital signal source 33 is used for setting a digital value on the input side. Recently, systemization of signal processing circuits and LSI
The digital-to-analog converter 1A has become a component of a system LSI and a signal processing LSI.
It often happens to be built in. A composite LSI incorporating such a digital-to-analog converter 1A
In the evaluation or selection of, the accuracy of the analog section is more important than the digital section. That is, the quality of the entire composite LSI may be determined to some extent depending on the accuracy of the analog unit. Here, the digital signal source 33
Digital data input from the clock signal generator 30
Is input to the digital / analog converter 1A, and the converted analog output OUT is measured by an analog output voltage measuring device 35 such as a digital voltmeter. As a result, the controller 34 is controlled to control the digital signal source 33. Therefore, when the digital-to-analog converter 1A including an analog circuit and serving as a junction between the digital unit and the analog unit is built in as a component of the composite LSI, an important part of the evaluation and selection of this LSI is considered. Becomes

On the other hand, the most basic evaluation of the digital-to-analog converter 1A is its linearity evaluation. In a composite LSI incorporating the digital-to-analog converter 1A,
Unnecessary external input pins must be provided despite only the linearity evaluation of the digital-to-analog converter 1A. Further, when digital data is serially input, the parallel output of the digital signal source 33 may need to be converted to a serial mode, which makes the external connection circuit of the measurement system more complicated.

[0005]

The above-mentioned conventional digital-to-analog converter has a disadvantage that the number of pins is unnecessarily increased when measuring the linearity of the built-in LSI. In addition, since a digital input signal is input from the outside, a circuit for generating digital data and a signal line for data input are required, and there are drawbacks such as a complicated connection of a measurement system.

It is an object of the present invention to provide such a built-in LSI.
It is an object of the present invention to provide a digital-to-analog converter which suppresses an increase in the number of pins and an increase in signal lines when measuring the linearity of a digital signal, thereby facilitating a measurement system.

[0007]

SUMMARY OF THE INVENTION A digital-to-analog converter according to the present invention comprises a buffer circuit provided with a digital input.
And connected to the output side of the buffer circuit,
The bus is controlled by an externally supplied linearity measurement control signal.
Buffer circuit output or counter signal.
First and second switch means for selecting, and the buffer
Latch the output of the circuit or use the counter signal
A plurality of flip-flops for counting the
AND gates that take the AND logic of the signal and the count result
Counter / latch circuit provided with
Reset pulse is applied to the counter and latch when a signal is input
Reset supplying the plurality of flip-flops of a circuit
A pulse generation circuit, the linearity measurement control signal and the
NA that takes NAND logic of output of counter / latch circuit
An ND circuit, an output of the NAND circuit and an external
An AND circuit which takes an AND logic of the supplied clock;
An output of the AND circuit, and the counter / latch circuit
A pulse generating circuit that outputs the counter signal to the
The output of the counter / latch circuit is converted to an analog signal.
And a conversion processing unit .

[0008]

Next, a related art and an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a digital diagram showing the related art of the present invention.
It is a block circuit diagram of an analog converter. As shown in FIG. 1, the related technology assumes that the number of bits is 5 bits. First, a control signal for setting the normal digital / analog conversion mode or the linearity measurement mode is input to the linearity measurement control signal input terminal. This control signal is fixed at a low or high level when the digital-to-analog converter 1 is operating, so that the influence of noise or the like on the circuit can be ignored. Here, it is assumed that a low level is input to the measurement control signal in the case of a normal digital-to-analog conversion operation. When this low level signal is input,
The control signal is input to the reset pulse generation circuit 2, the buffer 3, and the inverter 4. Since the output of the inverter 4 goes high and the output of the buffer 3 goes low,
The first switch 5 is turned on, and the second switch 6 is turned off. Therefore, the 5-bit data of the digital input terminals D0 to D4 is processed by the buffer circuit 12, the latch circuit 13, and the conversion processing unit 14, and the analog output terminal OU
A normal digital-to-analog converted analog value is output to T.

On the other hand, when a high level is inputted to the linearity measurement control signal input terminal, the first switch 5 is turned off and the second switch 5 is turned off.
Switch 6 is turned on. As a result, the 5-bit synchronization counter 11 is driven by the reset pulse generation circuit 2 and supplies its outputs A to E to the buffer circuit 12 via the second switch 6. Therefore, the analog output terminal OU
As T, a value obtained by converting the digital data of the counter 11 into an analog value by the latch circuit 13 and the conversion processing 14 is output. The reset pulse generating circuit 2 inputs one pulse to the counter 11 when the measurement control signal input changes from low level to high level, and sets the content of the counter 11 to an initial value. The outputs of the inverter 4 and the buffer 3 are for delaying the change from when the reset pulse is output until the counter 11 returns to the initial value, and includes an internal delay circuit.

Next, the counter 11 and its peripheral circuits and their operation will be described. First, the input digital signal I when measuring the linearity of the analog / digital converter 1 is measured.
The change in N is usually “00000” → “00001” →
“00010” → “00011” → “00100” ...
The steps are performed in the order of “11111”. Therefore,
An analog output voltage OUT at each digital input value IN is measured to measure linearity. Since the change in the digital value is the same as the operation of the counter 11, the output of the counter 11 can be used as a digital input. The count signal input to the counter 11 is an external clock signal C
LK is frequency-divided by the pulse generation circuit 10 and its output is input as a count signal. The input to the pulse generation circuit 10 is not directly clocked, but the output of the counter 11 becomes the maximum level "11111". In this case, the clock input to the pulse generation circuit 10 is interrupted when the That is, the third switch 7 and the AND circuit 8
After passing through a gate circuit including a NAND circuit 9 and a pulse generation circuit 10, the signal is input to a pulse generation circuit 10. Since the third switch 7 is controlled at the same timing as the second switch 6, it operates when the measurement control signal goes high. In short, it is turned on only when the linearity measurement mode is set, and the clock signal is led to the AND circuit 8.
The AND circuit 8 outputs a waveform similar to the clock signal CLK when the output of the NAND circuit 9 is high. In addition, since the output of the AND circuit 8 is obtained by shaping the clock waveform, a clear low and high waveform is formed, so that the counter 11 can be easily operated accurately. On the other hand, the NAND circuit 9 outputs a signal for selecting the passage of the clock in the AND circuit 8. This is to output a low-level signal when all the inputs of the NAND circuit 9 are at a high level, that is, when the outputs A to E of the counter 11 become maximum, so that the clock signal does not pass through the AND circuit 8. As a result, the counter 11 loses its count input signal, and its output is fixed at the maximum count. If the outputs A to E of the counter 11 are not the maximum values,
The output of the ND circuit 9 becomes high level, and the clock operates the counter 11 through the pulse generation circuit 10. The output of the pulse generation circuit 10 is output to the outside not only as a count signal of the counter 11 but also as a controller control same signal CONT via a buffer circuit 15. This is because the linearity measurement of the digital-to-analog converter 1 needs to be performed in synchronization with a change in the analog voltage output. Further, the above-mentioned 5-bit synchronization counter 11
Receives the count signal from the pulse generation circuit 10 and the reset pulse from the reset pulse generation circuit 2 and sends out 5 bits as a count output. The data output method of the counter 11 is that the output is digital for analog-to-digital conversion. Since it is also used as an input, a synchronous counter is used for the purpose of suppressing a malfunction of digital-to-analog conversion due to a delay in change of each input data.

[0012] Digital Figure 2 showing a Kazumi施例of the present invention
It is a block circuit diagram of an analog converter. As shown in FIG. 2, the present embodiment employs a digital-to-digital converter in which the 5-bit synchronous counter 11 and the latch circuit 13 in the related art described above are used.
It is an example of an analog converter. First, an accurate control signal S is obtained by using the buffer 16 to control the linearity measurement control signal.
2, the reset pulse generating circuit 2, the counter / latch circuit 20, the NAND gate circuit 21, the switch 7,
Supply to 18. Further, similarly to the related art described above, it has a normal digital data input terminal D0 to D4 for supplying a digital input IN, and a clock input terminal CLK for receiving a clock signal. The inputted clock signal is divided into a signal inputted to the counter / latch circuit 20 as the signal S3 via the switch 18 and a signal inputted as the signal S4 via the switch 7, the AND circuit 8 and the pulse generating circuit 10. The process of introducing a clock to the pulse generating circuit 10 is as follows. First, when the measurement control signal is in the linearity measurement mode, that is, when the measurement control signal is at a high level, the switch 7 is driven via the buffer 3 and
It leads to the D gate circuit 8. This AND gate circuit 8 has an NA
The clock signal CLK to the pulse generation circuit 10 is selected by the output of the ND gate circuit 21. The output of the NAND gate circuit 21 outputs a low level only when the output of the counter / latch circuit 20 in the linearity measurement mode is maximized, and cuts off the input of the clock signal CLK to the pulse generation circuit 10. Here, the inverter 19 is shifted leading edge timing of the counter signal S4 and the clock CLK during linearity measurements, Ru Oh used for inputting a clock signal S3 for accurate counting and latches. The inverter 17 is provided for alternately and accurately switching the switch 18 and the switch 7.

FIG. 3 is a block diagram of the counter / latch circuit shown in FIG. As shown in FIG. 3, the counter / latch circuit 20 has inverters 23 and 24 for 5 bits.
And five JK flip-flops 22A to 22E
, Switch circuits 25 and 26, and AND gate circuit 27
To 29. Outputs of these JK flip-flops 22A to 22E are input clocks S3 and S4.
Is determined by the data set at the input terminals J and K. In the normal conversion mode, the input of the linearity measurement control signal becomes low level, so that the switch 25 is turned on and the switch 26 is turned off via the inverter 23. Thereby, each digital data from the input terminals D0A to D4A is divided into five JK flip-flops 2.
2A to 22E. In this case, there are two patterns of the input data of these JK flip-flops 22A to 22E: J = 1, K = 0, J = 0, and K = 1. Such J, K flip-flops 22A to 22
The operation of E is such that when J = 1 and K = 0, the output Q is 1 and J =
It is determined that the output Q is 0 when 0, K = 1, the output Q is inverted when J = 1, K = 1, and the output Q is maintained when J = 0, Q = 0. Therefore, the output in the normal conversion mode depends on the state of the input J, and as a result, the input data can be latched. on the other hand,
When the linearity measurement control signal is at a high level, switch 2
Since 5 is off and the switch 26 is on, the JK flip-flops 22A to 22E perform the same operation as the 5-bit synchronous counter. Hereinafter, this counting operation will be described.

FIG. 4 is a timing chart for explaining the operation of the JK flip-flop shown in FIG. As shown in FIG. 4, JK flip-flops 22A to 22E
Is changed at the rising edge of the inverted clock, and it is assumed that the pulse generation circuit (counter signal S4) 10 performs a divide-by-2 operation. First, when the measurement control signal input in the D / A conversion circuit 1 of FIG. 2 is switched from low to high to switch to the linearity measurement mode, the reset pulse S1 is generated by the reset pulse generation circuit 2, so that J- All the K flip-flops 22A to 22E are in the initial state, and the output terminals D4B to
D0B is a digital output of "00000". on the other hand,
In the case of the measurement mode, the clock input to the counter / latch circuit 20 is input after changing the clock to the opposite phase because the JK flip-flops 22A to 22E assume a rising operation. Therefore, when the counter signal S4 rises after being input to the reset pulse S1, the inputs of the JK flip-flops 22A to 22E are J = 1 and K = 1, considering the least significant data. In this state, when the inverted clock signal rises, the JK flip-flop (hereinafter, J-flip-flop) is activated.
The Q output of the (KF / F) 22E is inverted and changes from 0 to 1.
The states of the other J-KF / Fs 22D to 22A are four A because the output Q of the flip-flop from the previous stage is "0".
The output of the ND circuit 28 also becomes "0", and each F / F does not change while maintaining the previous state. At this time, the digital signal has changed from 000000 to 00001. When the next counter signal S4 is output and the inverted clock signal is input, the J-KF / F22E is inverted and changes from 1 to 0. At this moment, the output Q of the J-KF / F22E has been "1" until then.
The K input is also 1, 1, and the output Q of the J-KF / F22D is inverted at the same time as the inverted clock is input, and changes from 0 to 1. The output digital data at this time is “0000”.
From "1" to "00010", that is, the output of the AND circuits 28 and 29 is the output Q of the J-KF / F lower than the J-KF / F to which the output of the AND circuit is supplied.
Are all "1" and the counter signal 4 is high, "1" is output. Thereafter, when the inverted clock signal rises, the outputs of these AND circuits are changed to J-KF / F.
, The output Q can be inverted. In other states, since the output of the AND circuit is "0", this J-KF / F holds the previous state even when the clock rises. Therefore, during linearity measurement, the latch circuit operates as a counter.

[0015] Finally, the circuit will be described that constitute the linear measuring system using a digital-to-analog converter shown in the above-described Kazumi施例.

FIG. 5 is a diagram of a linearity measuring system showing an application example of the present invention. As shown in FIG. 5, when measuring the linearity of the digital-to-analog converter 1 of the present embodiment, the input by the signal line connected to the outside is only the measurement control signal and the clock signal from the clock signal generator 30. The output is an analog output to a voltmeter 31 using a voltmeter and a controller control synchronization signal for operating the controller 32 to read the value of the voltmeter 31, and the total is four. However, in the measurement system shown in FIG. 6 described above, when measuring a 5-bit digital-to-analog converter, a total of seven input digital data of five parallel input, one analog output and one clock signal input are used. A signal line is required for measurement. Therefore, the digital
Analog converters can reduce the number of signal lines, which is more effective as the number of bits increases.

[0017]

As described above, the digital-to-analog converter of the present invention does not need to externally input a digital input signal in the linearity measurement, so that the number of pins is increased and the number of signal lines is reduced. There is an effect that can be. In particular, in a composite LSI with a built-in digital-to-analog converter, there is no need for a data input line only for evaluation and selection of the digital-to-analog converter.
Even in the inspection as a check on the wafer, since no data input line is required, the complexity of connection of the measurement system is reduced, and the inspection can be performed more reliably.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a digital-to-analog converter showing a related technique of the present invention.

2 is a block circuit diagram of a digital-to-analog converter showing the Kazumi施例of the present invention.

FIG. 3 is a configuration diagram of a counter / latch circuit shown in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of the JK flip-flop shown in FIG. 3;

FIG. 5 is a linearity measurement system diagram showing an application example of the present invention.

FIG. 6 is a diagram of a linearity measurement system using a digital-to-analog converter for explaining an example of the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 D / A converter 2 Reset pulse generation circuit 3,15,16 Buffer 4,17,19,23,24 Inverter 5-7,18,25,26 Switch 8,27-29 AND circuit 9,21 NAND circuit 10 Pulse generation circuit 11 5-bit synchronization counter 12 Buffer circuit 13 Latch circuit 14 Conversion processing unit 20 Counter / latch circuit 22A to 22E JK flip-flop (JK
F / F) 30 Clock signal generator 31 Voltmeter 32 Controller IN Digital input OUT Analog output A to E Counter output

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 G01R 31/00 G01R 31/28 H03K 23/50

Claims (1)

(57) [Claims] 1. A buffer circuit supplied with a digital input.
And connected to the output side of the buffer circuit,
The bus is controlled by an externally supplied linearity measurement control signal.
Buffer circuit output or counter signal.
First and second switch means for selecting, and the buffer
Latch the output of the circuit or use the counter signal
A plurality of flip-flops for counting the
AND gates that take the AND logic of the signal and the count result
Counter / latch circuit provided with
Reset pulse is applied to the counter and latch when a signal is input
Reset supplying the plurality of flip-flops of a circuit
A pulse generation circuit, the linearity measurement control signal and the
NA that takes NAND logic of output of counter / latch circuit
An ND circuit, an output of the NAND circuit and an external
An AND circuit which takes an AND logic of the supplied clock;
An output of the AND circuit, and the counter / latch circuit
A pulse generating circuit that outputs the counter signal to the
The output of the counter / latch circuit is converted to an analog signal.
And a conversion processing unit .