JPH0692990B2 - Digital cycle measuring circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital speed measuring circuit, and more particularly to a digital cycle measuring circuit which is suitable for high speed and high accuracy measurement and has good cost performance and low power consumption.

[Background of the Invention]

A conventional digital period measuring device was composed of a simple speed comparison counter and a latch circuit as described in National Technical Report VoL.28 No3, 6, 1982. This is detailed below. FIG. 8 is a diagram illustrating a conventional technique. In FIG. 8, 1 is a decoder, 2 is a preset value generation circuit, 3 is a pulse generation circuit, 4 is a preset circuit, 5 is an AND gate, 6 is a speed comparison counter, 7 is a maximum count value detection gate, and 8 is a trapezoidal wave output. A gate, 9 is a speed error gate circuit, and 10 is a latch circuit. Further, 21 to 25 are electric signals, and specifically, 21: clock pulse, 22: FG signal, 23: mode designation input, 24: preset pulse, 25: latch pulse.

In order to explain the operation of this conventional example, FIG. 9 of the supplementary diagram will be used below. The horizontal axis in FIG. 9 is time, 30 is the value of the speed comparison counter (FIG. 9), 31 is the value of the speed error gate circuit (FIG. 8), and 32 to 34 are FG signals 22. There is.
First, the pulse generation circuit in this system (Fig. 8 3)
Receives the FG signal 22 and creates a latch pulse 25 and a preset pulse 24 from the clock pulse 21. These two pulses are continuous without overlapping in time, and latch pulse 25
Latches the output of the speed error gate circuit 9 in the latch circuit 10, and the preset pulse 24 determines the timing for presetting the speed comparison counter 6. That is, first, the speed comparison counter 6 is preset to NP by the preset pulse 24. After that, the speed comparison counter 6 counts the clock pulses 21. The pattern of this count value is as shown in Fig. 30, but
When the count value reaches NF = 2n ^-1 , the output of the maximum count value detection gate 7 changes to low, the AND gate 5 is closed and the clock pulse 21 is not applied to the speed comparison counter 6 and is held at the count value NF. It The trapezoidal wave output gate 8 outputs the lower n bits through the speed error gate circuit 9 only when the count value of the speed comparison counter 6 is within a certain range, thereby providing a digital output like 31 which changes into a trapezoidal wave. If this trapezoidal wave output (output of 9) is latched by the latch pulse 25 generated by the next FG signal, the output of the latch circuit 10 changes in proportion to the FG cycle (trapezoidal waveform). For example, when the FG cycle is relatively long, such as 32 in FIG. 9, the latched value is a large value such as 37, the standard time is a value such as 36, and the short value is a small value such as 35. In this example, the decoder 1 reads the preset value for each designated mode from the preset value generation circuit 2 (specifically, ROM) by the mode designation signal input 23.

In this way, the cycle information of the FG signal 22 can be converted into a digital amount as the output of the latch circuit 10. However, the roughness of the measurement of the FG cycle to be converted here is determined by the cycle of the clock signal 21, and in order to perform accurate measurement, it is necessary to operate a high-speed operation element at a high voltage or a large current. Therefore, even if it is a high frequency clock to some extent, it is 6 dB
However, in order to improve the accuracy, a large cost increase and power loss were required.

[Object of the Invention]

An object of the present invention is to provide a digital speed comparison circuit whose accuracy can be easily improved (good cost performance).

[Outline of Invention]

The main points of the present invention are: 1) The least significant bit information is determined based on the sampling value of the clock signal by the CG signal.

2) Determine the clock application and stop timing for the speed comparison counter in synchronization with the FG signal and clock signal.

To do.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 50 is a pulse generation circuit, 51 is LSB (lowest)
It is a latch circuit. Of these, 50 is a little complicated, unlike the conventional example. A concrete configuration of the pulse generating circuit 50 is shown in FIG. 2, and a description will be added below with reference to a waveform diagram of a main part in FIG. In FIG. 1, 80 to 83 are electronic signals, and these are output signals of the pulse generating circuit 50. 80: Latch pulse 81: LSB (least significant bit) information, 82: shaped clock pulse, 83: preset pulse, respectively.

Before explaining the detailed operation of this embodiment, the principle of high precision measurement will be described with reference to FIG. FIG. 4 shows patterns (a) to (d) of the FG signal 22 having the same nT cycle, where the uppermost stage is the original clock signal 21 and the cycle is T. These are measured as the same period of nT by a counter that counts up at the rising edge of the clock 21, but if these are measured in finer T / 2 units, they are (a): nT (b) nT, ( c) nT-T / 2,
(D) nT + T / 2. To determine these four cases, 1) LSB (T / 2 step) information is obtained from the relationship between the sampling values H and L of the clock 21 at two consecutive FG edges.

2) Higher information is obtained by counting the shaped clock pulses 82.

Do the operation. Of these, the following means is one example of obtaining the shaped clock pulse 82. That is, 1) After detecting the FG edge, the clock is stopped at an appropriate timing T ₁ .

2) After that, clock start at an appropriate timing T ₂ .

Is.

Hereinafter, an example of obtaining the timings of T ₁ and T ₂ will be described.

An FG edge is detected and this FG edge (hereinafter, this FG edge
Edge) and the immediately preceding FG edge, the relationship between the sampling value of the clock 21 is determined.
For example, T ₁ is the timing at which the clock is stopped 0 or 1 clocks after the clock 21 after the FG edge is detected, depending on the relationship of the determined sampling values, and T ₂ is the determined timing. 4 after the current FG edge is detected, regardless of the relationship between the sampling values of
The clock starts from the 21st clock 21. Specifically, the current FG edge and the previous FG
There are four types of sampling values of the clock 21 at the edges, H ・ H, L ・ L, L ・ H, H ・ L, but in the case of H ・ H, L ・ L, H ・ L, Indicates that T ₁ is the timing to stop the clock one clock 21 after the FG edge is detected, and in the case of LH, T ₁ is the clock stop 0 clock 21 after the FG edge is detected. It is time to do it.

In this way, each time an FG edge is detected, the FG edge
21 is removed from the period from T ₁ to T ₂ to generate the shaped clock 82.

The preset value m when the timings T ₁ and T ₂ are set as described above is 2, and the FG shown in FIGS.
A shaping clock 82 for a signal is shown in FIGS. 4 (a) to (dd). This will be described below.

For the sake of explanation, the edge shown on the right side of each FG signal shown in FIGS. 4A to 4D is the current FG edge, and the left edge is the immediately preceding FG edge. When preceding FG edge is supplied, the clock 21 from the timing T ₁ to T ₂ is removed from the timing T _2, as shown in FIG. 4 (aa) ~ (dd), 4 (a The shaping clock 82 for the FG signal shown in FIGS. When the current FG edge is detected, the current
The relationship between the sampling value of the clock 21 at the FG edge and the FG edge immediately before the FG edge is H / H in the FG signal shown in FIG. 4 (a), and in the FG signal shown in FIG. 4 (b). , L • L With the FG signal shown in FIG. 4 (c), L • H is judged as H • L with the FG signal shown in FIG. 4 (d).

Therefore, the timing T ₁ after the current FG edge is detected is shown in FIGS. 4 (a), (b),
For the FG signal shown in (d), the timing is to stop the clock one clock 21 after the detection of the current FG edge. For the FG signal shown in FIG. 4 (c), the current FG edge is set. It is the timing to stop the clock 0 clocks after the clock 21 is detected. Therefore, the shaping clocks 82 for the FG signal shown in FIGS. 4 (a), (b), and (d) are respectively shown in FIGS. 4 (aa), (bb), and (dd).
In contrast to FIG. 4 (c), the shaping clock 82 for the FG signal shown in FIG. 4 (c) is reduced by one as shown in FIG. 4 (cc). That is, the number of shaping clocks 82 from the timing T ₂ with reference to the immediately preceding FG edge to the timing T ₁ with reference to the current FG edge is as shown in FIGS. 4 (aa), (bb), and (dd). In the shown shaping clock 82 (n-
m), the shaping clock 82 shown in FIG. 4 (cc) has (n−m−1) pieces.

Here, the count number of the shaping clock 82 from the timing T ₂ to the next timing T ₁ is set as information higher than the LSB information. When the preset value is m, the shaping clock 82 from the timing T ₂ to the next timing T ₁ is (m
Counting starts from the value of +1). As a result, the count number of the shaping clock 82 from the current FG edge to the timing T _{1 in} units of period T is shown in FIGS. 4 (a), (b), (c)
For the FG signal shown in (d), nT, nT, (n-1) T, nT respectively.
Becomes

Next, a method for obtaining the above LSB information will be described.

The exclusive OR of two sampling values of the original clock 21 at two consecutive FG edges for the same FG signal is shown in FIGS. 4 (a), (b), (c) and (d).
It becomes L, L, H, H respectively for the FG signal, and when such exclusive OR is L, the LSB information (T / 2 step) is 0 × (T /
2) and when the exclusive OR is H, the LSB information (T / 2
Set the step size to 1 × (T / 2). As a result, the period of the FG signal in FIG. 4 (a) = nT + 0 × (T / 2) = nT. The period of the FG signal in FIG. 4 (b) = nT + 0 × (T / 2) = nT. ) FG signal cycle = (n-1) T + 1 × (T /
2) = nT−T / 2 FG signal cycle in FIG. 4 (d) = nT + 1 × (T / 2) = nT + T
It is measured as / 2, and it becomes possible to measure in T / 2 increments.

Next, FIG. 2 showing an embodiment for realizing the above operation will be described. Second
In the figure, 60, 61, 62 and 63 are flip-flops (FF),
The former three are D-FF and the last are RS-FF. Further, 64 is a counter, 65 to 70 are logic gates (specifically, 65 is described as an AND gate), 71 is an add gate, and 72 is an exclusive logic talk (exclusive OR) gate. Again 80-87
Is an electrical signal.

In the initial state in the figure, the flip-flop 60 is reset to be high, the reset signal 87 of the counter 64 is to be high, and each bit output of the counter (for example, Q ₁ , Q ₂ ... from the least significant) is all low. This is because the logic gate 65 always returns the product of an appropriate counter output (for example, Q ₂ and Q ₃ ) to the reset of the flip-flop 60, so that the flip-flop 60 is always reset and its Q output becomes high and stable. It is because The input to be ANDed by the logic gate 65 is arbitrary as long as it is longer than the clock stop period (in the example, 2 clocks or 3 clocks) (for example, if Q ₂ and Q ₃ are selected, it is reset at 2 + 4 = 6).
Next, at the rising edge of the FG signal 22, the flip-flop 60 takes in the D input (data input) high, the Q output high,
Invert to output low. Then, since the signal 87 is low, the counter 64 advances the counting operation according to the clock 21.
The flip-flop 63 is operated by the count information, the clock 21, and the sampling value of the clock with the continuous FG signal described above.

The flip-flops 61 and 62 detect the sampling value of the clock 21 at two consecutive rising edges of the FG signal 22, and determine whether the rising edge is in the first half of the cycle of the clock 21 or in the second half of the cycle. The Q output of the flip-flop 62 is the sampling value at the immediately preceding rising edge, and the Q output of the flip-flop 61 is the next rising edge (that is, the current FG edge above).
The sampling values at are shown respectively. Therefore, the combination of the Q outputs of these flip-flops 61 and 62 is H · H, L·L, L · H, H.
・ It will be either L, but this is shown in Fig. 4 (a),
(B), (c), (d) or Fig. 4 (aa), (b
It corresponds to b), (cc), and (dd).

Further, the logic gate 70 is for determining the relationship between the sampling values of the clock 21 in two consecutive rising edges of the FG signal 22, and the Q of the flip-flops 61 and 62.
When the combination of outputs is H ・ H, L ・ L, H ・ L, and when L ・ H
Is determined.

The logic gate 67 determines the timing T ₂ described with reference to FIG.
When is high, a high signal 85 (FIG. 3) is output (specifically, Q3 of the counter 64 and the clock 21 are ANDed).

The logic gate 66 determines the timing T ₁ described with reference to FIG. 4, and according to the output of the logic gate 70, the counter 64
The signal 84 or 84 'shown in FIG. 3 which is high during the low period of the clock 21 when the value is 1 or 0 is output.

The output 84 or 84 'of the logic gate 66 is a flip-flop.
63 is set and the output 85 of the logic gate 67 resets the flip-flop 63. This makes the flip-flop 63
Output, 'as indicated, T ₁ through T ₂ period or T _1' signal 86 or 86 in FIG. 3 becomes through T ₂ period wax. AND gate this signal 86 or 86 'with the original clock 21.
The signal 82 or 82 'in FIG.
As shown below, the shaping clock 82 is obtained by removing the clock 21 during the T _{1 to} T ₂ period or the T ₁ ′ to T ₂ period. That is,
The shaping clock 82 as shown in FIGS. 4 (aa), (bb), (cc), and (dd) is obtained.

As described above, the flip-flops 60, 63, the counter 64,
The logic gates 65 to 67, 70 and the AND gate 71 constitute means for generating and outputting the shaping clock 82 using the judgment results of the flip-flops 61, 62.

The exclusive OR gate 72 is a flip-flop 61, 62.
Is supplied to generate the LSB information 81 described above.

In addition, the logic gates 68 and 69 respectively calculate from the value of the counter 64
The output of the flip-flop 63 generates the latch pulse 80 and the preset pulse 83 in FIG. 1 during the low period.

Next, the operation of this embodiment shown in FIG. 1 will be described.

When the pulse forming circuit 50 detects the rising edge of the FG signal, the pulse forming circuit 50 outputs the shaping clock 82 so far and supplies it to the speed comparison counter 6 via the AND gate 5. The relationship between the rising edge and the sampling value of the clock 21 at the immediately preceding rising edge is determined, the LSB information 81 corresponding to this determination is generated and output, and the above timing T ₁ is set. The output of the shaping clock 82 that has been output in the cycle of the FG signal is stopped. Assuming that the preset value of the speed comparison counter 6 by the preset circuit 4 is m, the number of the shaping clocks 82 supplied in the cycle of the FG signal so far is (nm) or ((m-m)) as described with reference to FIG. n-m-1),
The count value n or (n-1) obtained by adding m to this is supplied to the latch circuit 10 via the speed error gate circuit 9.

The pulse forming circuit 50 stops the output of the shaping clock 82 during the period between the timing T ₁ set above and the timing T ₂ described above.
Is generated to latch the count value n or (n-1) through the speed error gate circuit 9 in the latch circuit 10, and LSB.
The LSB information 81 is latched in the latch circuit 51. This gives F
The digital value of one cycle of the G signal is obtained by the latch circuit 10 and the LSB latch path 51.

Thereafter, the pulse generation circuit 50 generates a preset pulse 83, presets the value m of the preset circuit 4 in the speed comparison counter 6, and then, at the timing T ₂ , outputs the shaping clock 82 and the speed comparison counter 6 outputs. The counting is started from (m + 1).

In this way, by interrupting the shaping clock 82 for the period of T _{1 to} T ₂ , the latch between the latch circuit 10 and the LSB latch circuit 51 and the presetting of the speed comparison counter 6 can be performed, and the speed comparison counter 6 can be preset. 6 can count the period of the FG signal 22. Such a latch circuit 10 and LSB
Since the latching with the latch circuit 51 and the presetting of the speed comparison counter 6 can be performed in at least two cycles of the clock 21, the preset value m of the speed comparison counter 6 may be 2 or more.

Finally, the specific structure of the logic gates 70, 66, 67 is shown in FIG. 5, and the description of one embodiment is completed. In FIG. 5, 100 to 106 are inverters, 107 to 109 are NAND gates, 110 and 111 are AND gates, and 120 to 122 are electric signal lines. Here, the signal 120 becomes high only when the Q output of the flip-flops 62 and 61 is LH, that is, in the case of FIG.
Open 7, otherwise go low to open gate 108. Therefore, the signals 121 and 122 become reverse polarity signals of 84'84 in FIG. 3 and the above-described operation becomes possible.

Now, another embodiment of the present invention will be described with reference to FIG.

In FIG. 6, 150 to 155 are flip-flops,
Reference numeral 150 is a T-flip-flop, 151 to 154 are D-flip-flops, and 155 is an RS-flip-flop. 156-16
2 is a NAND gate, 163-164 are inverters, 165-167 are AND gates, 168 is an exclusive OR gate, and 180-186 are electric signals. Now, description will be added below with reference to the waveform chart of the main part of FIG. 6 in FIG. First, consider a case where the relationship between the original clock signal 21 and the FG signal 22 is as shown in FIGS. 7 (e) and 7 (f). That is, two consecutive FGs
The sampling value of clock 21 at the rising edge of
HH, LL, and the sampling value before (not shown) is H. First, in the case of (e), the sampling value of the clock 21 at the edge of FG continues to be H.
Therefore, the Q output signal 180 of the flip-flop 152 is also H
Is. Therefore, because NAND gate 159 is open and the output of NAND gate 160 is high, signal 181 is clocked.
It has the same polarity as 21. Next, because of the inverter 163, the flip-flops 150 and 151 are reset during the low period of the FG signal 22. Therefore, the output of the NAND gate 156 is high, and the signal 182 is output to the NAND gate 157. After the FG signal 22 rises, the flip-flop 15
The reset of 0, 151 is released, and the counting operation is started by these 2 bits. Although the trigger input is input to 152 during counting, the data signal 180 remains H. Further, the counting flip-flop 155 has a signal 183 (Q output of the flip-flop 150) and a signal 184 (Q of the flip-flop 151).
Output) is H · L, and the reset input is applied when H · H, the output of the flip-flop 155 becomes like the signal 185, and the AND output 186 of this and the signal 181 is the signal 21. Input with the same polarity as shown in the figure. On the other hand, in the case of (f), the sampling value of the clock at the FG signal edge that precedes the one shown in the figure is H, but (to the part shown in the figure) continues to L. Change. As a result, the signal 180 is inverted from H to L as shown in the figure, and at this time, the NAND gate 160 opens to allow the clock of the opposite polarity to pass.
Is as shown in FIG. In this way, the period of the signal 185 is shortened by a half cycle of the clock, and the polarity of the output signal 186 is inverted.
Thus, the temporal relationship between the FG signal 22 and the output clock 186 matches. In other words, this operation is performed by inverting the polarity of the clock, which is the on / off timing of the output clock that was performed in the previous embodiment. Although not mentioned in this embodiment, the operations of the flip-flops 153 and 154 and the exclusive OR gate 168 are the same as those in the previous embodiment. If the gate delay amount is taken into consideration, the value obtained by sampling the output clock (for example, signal 168) with FG signal 22 is used as LSB information (for example, exclusive OR gate 1).
The output of 68) is also possible.

〔The invention's effect〕

According to the present invention, conventionally, there is no choice but to raise the clock for period measurement that requires accuracy, and even if the accuracy is improved by 6 dB, it is necessary to operate all the elements that form the counter array at high speed, resulting in a large power consumption. Although the LSI chip area was increased due to the use of expensive high-speed elements and the difficulty of element layout, the above-mentioned consideration is not required, and the power and cost are reduced by 30 to 50%. .

[Brief description of drawings]

1 and 2 are block diagrams showing an embodiment of the present invention,
3 and 4 are waveform diagrams of main parts, FIG. 5 is an example of a block configuration diagram of one embodiment, FIG. 6 is a block diagram of another embodiment of the present invention, and FIG. 7 is of FIG. FIG. 8 is a waveform diagram showing waveforms of essential parts, FIG. 8 is a block diagram of a conventional technique, and FIG. 9 is an operation explanatory diagram of the conventional technique. 51 …… Latch circuit 50 …… Pulse creation circuit 66,67 …… Logic gate 61,62,63,150 to 155 …… Flip-flop 64 …… Counter 72,168 …… Exclusive OR gate

Claims (1)

[Claims] 1. A predetermined value m every time the period of a signal under measurement starts.
By using the counting means preset for counting the shaping clock and the latch means for fetching the count value of the counting means immediately before the preset time point, the period of the measured signal is measured and the measurement result is digitally measured. A digital period measuring circuit that obtains a value, and a determining unit that determines whether the start time point of the sequential measurement period of the signal under measurement is in the first half of the period of the original clock or in the second half of the remaining period. According to the determination result of the determination means, the sequential 2
When the start time of one measurement cycle is in the first half of the cycle of the original clock or the latter half of the cycle, the "0" bit which is the least significant bit in the digital value is generated and the measured signal is sequentially output. The least significant bit that generates the "1" bit, which is the least significant bit, when one of the two measurement cycle start points of is in the first half of the period of the original clock and the other is in the remaining second half. Depending on the generation means and the determination result of the determination means, the sequential measurement of the measured signal is performed.
When one of the two measurement cycle start times is in the first half or the remaining second half of the cycle of the original clock, or when the preceding measurement cycle start time of the two successive measurement cycle start times of the measured signal is When the subsequent measurement cycle start time point in the first half of the period of the original clock and the subsequent measurement cycle start time in the remaining second half of the period of the original clock, after the subsequent counting cycle start time point is detected, The original clock is removed by m to form the shaped clock, and the preceding measurement cycle start time of the two successive measurement cycle start times of the measured signal is in the remaining second half of the cycle of the original clock. When the next measurement cycle start time is in the substantially first half of the cycle of the original clock, one original clock is generated after the subsequent counting cycle start time is detected. Before Counting clock output means for supplying the shaping clocks to the counting means respectively except (m + 1) are provided, and the latch timing of the latch means and the preset timing of the counting means are m original clocks or (m + 1). A digital cycle measuring circuit, wherein the measurement result is obtained by setting a period excluding the number and adding the least significant bit obtained by the least significant bit generating means to the digital value latched by the latch means.