JP3036768B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit whose process is simplified and integration density is greatly improved.

(B) Conventional technology As semiconductor integrated circuits become more sophisticated and sophisticated,
High integration is a very important point.

For example, the structure and manufacturing method of a bipolar transistor are described in detail in "Latest LSI Process Technology" Industrial Research Committee (issued on April 25, 1984).

This bipolar transistor (1) is as shown in FIG.
An N-type epitaxial layer (3) is stacked on a P-type semiconductor substrate (2), and an N ⁺ type buried layer (4) is provided between the semiconductor substrate (2) and the epitaxial layer (3). Is formed.

In addition, around the buried layer (4), the semiconductor substrate (2) was reached from the surface of the epitaxial layer (3).
There is a P ⁺ type isolation region (5). This separation area (5)
It may be diffused at once from the surface of the epitaxial layer, or may be dispersed by a vertical separation method as shown in FIG.

The isolation region (5) forms an island (6) comprising the epitaxial layer (3), and the island (6) becomes an N-type collector region. Further, a P-type base region (7) formed in the island (6), an N ⁺ -type emitter region (8) formed in the base region (7), and an epitaxial layer serving as the collector are formed. There is a collector contact region (9) formed in an exposed region, and there are respective electrodes formed through contact holes of a SiO ₂ film formed on the epitaxial layer (3).

Next, a method for manufacturing the bipolar transistor (1) will be described. First, on a P-type semiconductor substrate (2), SiO ₂
There is a first step of forming a film, forming a diffusion hole of the buried layer (4) in the SiO ₂ film, and diffusing antimony into the semiconductor substrate (2) through the diffusion hole.

Here, in the case of FIG. 2, since the separation region (5) is achieved by vertical separation, boron is diffused into the semiconductor substrate (2) through a diffusion hole, and a P ⁺ type lower diffusion layer is formed. (10) is also formed.

Next, an epitaxial layer (3) is laminated on the surface of the semiconductor substrate (2), and an SiO ₂ film is formed on the epitaxial layer (3). In the SiO ₂ film, diffusion holes in the upper diffusion region (11) of the separation region (5) are formed by application of a photoresist film, mask alignment, exposure, etching, and the like, and boron is diffused through the diffusion holes. There is a second step in which the isolation region (5) is formed.

Then, again apply the photoresist film, align the mask,
There is a third step of forming a diffusion hole of the base region (7) in the SiO ₂ film by exposure and etching, and diffusing boron through the diffusion hole to form the base region (7).

Further, diffusion holes of the emitter region (8) and the collector contact region (9) are formed in the SiO ₂ film by applying a photoresist film again, aligning a mask, exposing, etching and the like, and arsenic is diffused through the diffusion holes. Then, there is a fourth step of forming the emitter region (8) and the collector contact region (9).

Finally, apply the photoresist film again, align the mask,
Contact holes for the emitter region (8), the base region (7), and the collector contact region (9) are formed in the SiO ₂ film by exposure and etching.
There is a fifth step of forming each electrode by vapor deposition.

(C) Problems to be Solved by the Invention The bipolar transistor (1) is achieved by the above-described first to fifth steps. However, the positions where the diffusion holes are formed in the second step, the third step, and the fourth step are deviated from the design values due to mask alignment and etching.

In FIG. 2, the upper diffusion region (1
The diffusion depth of 1) and the diffusion depth of the base region (7) are
If they are 4 μm and 1 μm, respectively, they spread to the same extent in the horizontal direction.

The base region (7) may be shifted to the left as shown by the broken line in FIG. 2 by mask alignment or etching. Of course, the same can be said for a shift in the right direction and in the direction perpendicular to the page. In consideration of this, a margin of the width (about 2 μm) indicated by the arrow is actually provided to prevent contact with each diffusion region. Therefore, a margin of 4 μm on both sides is set for each of the transistors to be integrated, which is an obstacle to the improvement of the degree of integration.

In addition, since the base and emitter regions have steps of mask alignment, etching and diffusion, respectively, the number of steps is long and the yield is reduced.

Although the above description refers to a vertical NPN transistor, similar problems to this transistor also occur for lateral transistors that are integrated together. In other words, according to FIG. 1N of the present invention, after forming the upper diffusion region (32) of the upper and lower isolation region (31) surrounding the lateral transistor (25), the lateral transistor (25) is formed. Since the diffusion holes of the P-type emitter (47) and the collector region (48) to be formed are formed through mask alignment and an etching process, a deviation from a design value occurs.

As described above, the present application relates to a lateral transistor (25)
The deviation from the design value that occurs in the above is prevented, and the lateral transistor (25) and the vertical transistor (2
1) prevents deviation from the design value which occurs when integrated together.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and is directed to a method of manufacturing a semiconductor integrated circuit having a lateral transistor (25) having an emitter region (47) of at least one conductivity type. Forming an insulating film (61) on a semiconductor layer (28) of the opposite conductivity type having a buried layer (29) of the opposite conductivity type; Forming an impurity introduction hole (62) in the insulating film (61) corresponding to the one conductivity type expected collector region (48) surrounding the 47) and the one conductivity type expected isolation region (31); Through the introduction hole (62), the predetermined separation region (3
1), a step of introducing impurities into the predetermined emitter region (47) and the predetermined collector region (48).

Also, a method for manufacturing a semiconductor integrated circuit having a lateral transistor (25) having an emitter region (47) of at least one conductivity type and a vertical transistor (21) having an emitter region (39) of the opposite conductivity type. A semiconductor layer (2) having a reverse conductivity type buried layer (29) provided in the predetermined lateral transistor (25) region and the predetermined vertical transistor (21) region;
8) a step of forming an insulating film (61) thereon; and the emitter region (47) to be formed in the planned lateral transistor (25); and the emitter region (47).
Corresponding to a predetermined collector region (48) of one conductivity type, a base region (38) of one conductivity type to be formed in the predetermined vertical transistor (21), and a separation region (31) of one conductivity type, respectively. Forming an impurity introduction hole (62) in the insulating film (61), and introducing the impurity into the introduction hole (62) to form the predetermined isolation region (31) and the predetermined emitter region (47). And a step of diffusing the predetermined collector region (48) and the base region (38).

(E) Action In the lateral transistor (25), the impurity introduction hole (6) is formed in the insulating film (61) corresponding to the isolation region (31), the emitter region (47) and the collector region (48).
Since the holes 2) are formed at one time, the formation positions of the respective diffusion regions can be determined, and the shift of the formation positions conventionally provided can be eliminated. In addition, a margin due to the displacement can be omitted.

On the other hand, when the vertical transistor (21) and the lateral transistor (25) are integrated on a semiconductor substrate, an isolation region (31) formed in the lateral transistor region and an emitter region ( 47) and the insulating film (61) corresponding to the collector region (48) and the insulating film (61) corresponding to the isolation region (31) and the base region (38) formed in the vertical transistor region. Inlet (6
Since the holes 2) are formed at one time, the formation positions of the respective diffusion regions can be determined, and the shift of the formation positions conventionally provided can be eliminated. In addition, a margin due to the displacement can be omitted.

(F) Embodiment Hereinafter, a method of manufacturing a semiconductor integrated circuit according to an embodiment of the present invention will be described.
Transistor (21), lateral type second of the PNP transistor (22) and the vertical third NPN-type transistor (23) configured I ² L (24), a lateral type PNP type An integrated structure of the fourth transistor (25) and the vertical PNP fifth transistor (26) will be described.

First, the overall configuration will be described with reference to FIG. As shown in the figure, there is a P-type silicon substrate (27).
Above there is an N-type semiconductor layer (28) (hereinafter described as an epitaxial layer). Between the epitaxial layer (28) and the substrate (27), regions of the first transistor (21), I ² L (24), fourth transistor (25), and fifth transistor (26) An N ⁺ -type buried layer (29) is formed in correspondence with the above. Further, on the N ⁺ type buried layer (29) corresponding to the fifth transistor (26),
Further, a P ⁺ type buried layer (30) is formed.

The epitaxial layer (28) surrounding the buried layer (29)
There is a P ⁺ -type upper and lower separation region (31) penetrating through. The upper and lower isolation regions (31) are composed of an upper diffusion region (32) and a lower diffusion region (33), and the upper diffusion region (32) is diffused downward from the surface of the epitaxial layer (28). The side diffusion region (33) is achieved by being diffused upward from the surface of the substrate (27). Further, here, in order to achieve high integration of the present integrated circuit, the lower diffusion region (33) is substantially diffused upward to near the surface of the epitaxial layer (28).

Therefore, the first to fourth islands (34), (35), (36),
(37) is formed.

The first island (34) is provided in the P-type base region (38), the N ⁺ -type emitter region (39) and the base region (38) using the epitaxial layer (28) as a collector. First transistor (vertical NPN transistor) comprising P ⁺ type base contact region (40) (2
1) There is.

The second island (35) incorporates at least one I ² L (24) by a lateral PNP-type second transistor (22) and a vertical NPN-type third transistor (23). ing. The second transistor (22) includes the N transistor
-Type epitaxial layer (28) based, become by a P ⁺ -type emitter region and (41) P ⁺ -type collector region (base contact region of the third transistor (23)) (42), said emitter region (41) is the injector region of I ² L (24). On the other hand, the third transistor (23) uses the P ⁺ -type well region (43) as a base region and the epitaxial layer (28) as an emitter region. The collector C ₁ to N ⁺ -type diffusion region (44), and the collector C _2. Further, the P ⁺ type base region is diffused over the entire surface except for two places in the well region (43). This is because two collector regions (44) were made, and this number can vary depending on the purpose. On the other side of the P ⁺ type injector region (41), there are an N ⁺ type emitter extraction region (45) and an N ⁺ type emitter contact region (46).

The third island (36) incorporates a lateral PNP-type fourth transistor (25), which is based on the epitaxial layer (28). ^{There is a +} type emitter region (47) and a P ⁺ type collector region (48) around the emitter region (47). Further, there is an N ⁺ type diffusion region (49), which functions as a base contact region.

The fourth island (37) incorporates a vertical PNP fifth transistor (26). As mentioned above,
This island (37) has an N ⁺ type buried layer (29)
And a P ⁺ type buried layer (30) are provided, and this P ⁺ type buried layer (30) becomes a collector region. In order to extract the collector region, the epitaxial layer (28)
P ⁺ -type collector contact region reaching from the surface the P ⁺ -type buried layer to (30) (50) is provided. In the region surrounded by the collector extraction region (50), an N ⁺ -type well region (51) is superimposed and diffused, and a P ⁺ -type well region (51) is provided in the base well region (51). An emitter region (52) and an N ⁺ type base contact region (53) are formed. Although the N ⁺ -type well region (51) is overlapped here, it may be simply an N-type epitaxial layer (28).

Further, an insulating film (54) made of a silicon oxide film or the like is formed on the surface of the epitaxial layer (28), and an electrode is formed through a contact hole.

Explaining in order from the left side of the figure, a collector hole, a base hole and an emitter hole are formed in the first island (34), and a collector electrode, a base electrode and an emitter electrode are formed through these holes. The second island (35) has injector holes, base holes, collector holes,
And an emitter hole are formed, and an injector electrode, a base electrode, a collector electrode, and an emitter electrode are formed. An emitter hole, a collector hole, and a base hole are formed in the third island (36), and an emitter electrode, a collector electrode, and a base electrode are formed. A collector hole, an emitter hole, and a base hole are formed in the fourth island (37), and a collector electrode, an emitter electrode, and a base electrode are formed.

Although this configuration has been achieved by a single layer of electrodes,
Some circuits may be composed of two or more layers of electrodes. Although a diode and a resistor are also incorporated, they are omitted here.

 Next, the manufacturing method of the present invention will be described.

First, as shown in FIG. 1A, after a thermal oxide film is formed on the surface of a P-type silicon semiconductor substrate (27) having an impurity concentration of about 10 ¹⁵ atom / cm ³ , an N ⁺ -type buried layer (29) is formed. After etching the intended region, N-type impurities such as antimony and arsenic are doped through the opening.

Subsequently, as shown in FIG. 1B, the lower diffusion region (33) of the P ⁺ type upper and lower isolation region (31) and the fifth transistor (26)
An opening is formed in the thermal oxide film on the region where the P ⁺ -type buried layer (30) is to be formed, and boron, which is a P-type impurity, is doped through this opening. Here, this may be achieved by ion implantation. In other words, the thermal oxide film generated in the previous process is removed, and
A 0 ° thermal oxide film is formed, a resist serving as a positive mask is applied and patterned, and boron ions are implanted.
Thereafter, the resist is removed, and heat treatment is applied to diffuse the resist.

Next, as shown in FIG. 1C, the thermal oxide film on the semiconductor substrate (27) is completely removed, and then the N.sub. A mold type epitaxial layer (28) is formed with a thickness of 2 to 8 μm.
At this time, the previously doped impurity is slightly diffused up and down.

Next, as shown in FIG. 1D, a heat treatment is performed in an oxygen atmosphere to form a thermal oxide film (6
0) is formed. Subsequently, a negative resist film is applied on the entire surface and patterned, and the N ^{+ of} the fifth transistor (26) is
Layer (2) corresponding to the well region (51) of the mold
8) Inject phosphorus ions into the surface.

Next, as shown in FIG. 1E, after removing the resist film,
A negative resist film is applied again on the entire surface and patterned, and boron ions are applied to the surface of the epitaxial layer (28) corresponding to the P ⁺ type well region (43) to be formed in the second island (35). inject.

Next, as shown in FIG. 1F, a thermal oxide film is formed on the surface of the epitaxial layer (28) by thermal oxidation at a temperature of about 1000 ° C. for several hours. Is re-diffused.

Accordingly, the lower diffusion region (33) is diffused upward to about half or more (substantially near the surface of the epitaxial layer (28)) of the epitaxial layer (28). Further, by this step, the thermal oxide film (61) on the surface of the epitaxial layer (28) grows to a thickness of several thousand 、, and this thermal oxide film (61) exhibits the same function as a mask described later. However, the thermal oxide film may be entirely removed, and a silicon nitride film or the like may be used as a diffusion mask, or a silicon oxide film may be formed by a CVD method.

Further, when the thickness of the epitaxial layer is reduced to about half or less as compared with the conventional case, the lower diffusion region (33) is correspondingly shallowed. Therefore, the lateral spread can be reduced.

Subsequently, as shown in FIG. 1F, the second island (3
The insulating film (61) corresponding to the emitter extraction region (45) of the third transistor (23) in 5) is etched, and Pocl _{3 serving} as a diffusion source is applied on the entire surface. Thereafter, heat treatment is performed to diffuse phosphorus into the epitaxial layer (28). Thereafter, Pocl ₃ is removed, and heat treatment is performed again so as to have a predetermined depth.

Subsequently, as shown in FIG. 1G, a predetermined upper and lower separation area (31)
Upper diffusion region (32) of the first transistor (2
In the base region (38) of 1) and the planned I ² L (24), an injector region (41) serving as an emitter region of the second transistor (22) and a base contact region (42) of the third transistor (23) ), Corresponding to the emitter region (47) and collector region (48) of the planned fourth transistor (25), and the emitter region (52) and collector extraction region (50) of the planned fifth transistor (26). An impurity introduction hole (62) is formed in the silicon oxide film (61).

Here, it is formed by dry etching using a positive resist film as a mask. Thereafter, the exposed region of the epitaxial layer (28) is subjected to dummy oxidation to form a dummy oxide film. This dummy oxide film is used to reduce damage to the epitaxial layer (28) due to the subsequent ion implantation step, and also to disperse ions randomly and to implant ions uniformly.

Subsequently, as shown in FIG. 1H, the base region (38) of the predetermined first transistor (21), the emitter region (41) of the second transistor (22) of the predetermined I ² L (24) and The base contact region (4) of the third transistor (23)
2) the emitter region (47) and the collector region (48) of the planned fourth transistor (25);
A mask (63) is provided in the introduction hole (62) corresponding to the emitter region (52) of the transistor (26), and boron as an impurity is ion-implanted. Therefore, boron is implanted into the predetermined upper diffusion region (32) and the predetermined collector extraction region (50) of the fifth transistor (26).

Here, a resist film that can block implanted ions,
After covering the entire surface with a so-called mask (63), the mask (63) corresponding to the upper diffusion region (32) is removed, and boron, which is a P-type impurity, is implanted under predetermined conditions.

In this step, even if the opening of the mask (63) is formed larger than the introduction hole (62) of the silicon oxide film (61) as shown in the figure,
Since the silicon oxide film (61) functions as a mask, it indicates that the formation position of the introduction hole (62) and the predetermined upper diffusion region (32) match.

Subsequently, as shown in FIG. 1, the resist (63) serving as the mask is removed, and heat treatment is performed under predetermined conditions.

Therefore, the upper diffusion region (32) reaches the lower diffusion region (33). As described above, the lower diffusion region (3
Since (3) is diffused upward to the vicinity of the surface of the epitaxial layer (28), the diffusion of the upper diffusion region (32) is reduced. Therefore, the lateral diffusion of the upper diffusion region (32) can be prevented. The collector extraction region (50) reaches the P ⁺ type buried layer (30).

Subsequently, as shown in FIG. 1J, impurities are ion-implanted into all the introduction holes (62).

Here, no mask is formed in the introduction hole (62),
Base region (38) of first transistor (21), emitter region (41) of second transistor (22), base contact region (42) of third transistor (23), fourth transistor (25) The boron is ion-implanted into the emitter region (47) and the collector region (48) of the fifth transistor (26), and boron is implanted into the upper diffusion region (32) and the fifth transistor (26). The collector extraction region (50) is ion-implanted again.

Subsequently, as shown in FIG. 1K, a resist film serving as a mask is formed so that a base contact region (40) to be formed is at least opened in a base region (38) of the planned first transistor (21). Form (64). Then, boron is ion-implanted.

Here, the base region (38) excluding the base contact region (40) covers at least the resist film (64), and all the introduction holes (62) shown in the figure are opened.
However, a part of the introduction hole (62) may be covered with a resist film in consideration of the respective impurity concentrations.

The feature of the present invention lies in the steps described with reference to FIGS. 1G to 1K.

As shown in FIG. 1G, the base region (38) of the first transistor (21), the emitter region (41) of the second transistor (22), the base contact region (42) of the third transistor (23), The emitter region (47) and collector region (48) of the fourth transistor (25), the emitter region (52) and the collector extraction region (50) of the fifth transistor (26), and all upper diffusion regions (32) Since the corresponding introduction holes (62) are formed at one time and the formation positions are determined by the introduction holes (62), it is possible to omit a margin due to a deviation from a conventionally provided design value.

In particular, in the first transistor (21), the upper diffusion region (32) and the base region (38), and the second transistor (22)
The upper diffusion region (32) and the emitter region (41) in the fourth transistor (25), the upper diffusion region (32) and the collector region (48) in the fourth transistor (25), and the collector extraction region (50) in the fifth transistor (26). There is no need for allowance between the emitter regions (52), and the allowance can be eliminated in the vertical and horizontal directions in plan view.
Each cell size is reduced, and eventually the chip size can be reduced. Further, since the cell size can be reduced, the degree of integration can be improved in width.

On the other hand, in the case of a vertical PNP transistor, which is the fifth transistor (26), the left and right collector extraction regions (5
Since the distance between 0) can be shortened, the collector resistance can be reduced and the saturation voltage of V _CE can be reduced.

In the step of FIG. 1J, the diffusion is performed without forming a mask. However, in the present application, a mask may be provided in the introduction hole on the isolation region (31) or the like.

As described with reference to FIG. 1H, the diffusion region (38) can be accurately determined simply by making the opening of the mask slightly larger than the introduction hole (62). Further, here, it is possible to prevent excessive impurities from being injected into the isolation region (31) by the mask.

Subsequently, as shown in FIG. 1L, the photoresist film (64) is removed, and the entire silicon oxide film (61) on the epitaxial layer (28) is etched. Thereafter, a non-doped silicon oxide film and a phosphorus-doped silicon oxide film are laminated on the entire surface in the thickness of several thousands of layers, respectively, so that there is no difference in the overall film thickness. This is because the silicon oxide film (6
In the case of 1), the silicon oxide film (61) on the emitter region (39) of the intended first transistor (21) is thinner than the silicon oxide film on the collector region. This is because the epitaxial layer serving as the emitter region (39) is etched or the corresponding silicon oxide film (61) is side-etched before opening. Therefore, as described above, the difference in film thickness is eliminated and the amount of etching of the epitaxial layer corresponding to the emitter region (39) or the amount of side etching of the silicon oxide film on the epitaxial layer is reduced.

Further, as shown in FIG. 1M, a photoresist film is formed, and a contact hole is formed in the silicon oxide film (66) by anisotropic etching.

Specifically, the emitter hole (67), the base hole (68) and the collector hole (69) of the first transistor (21),
The emitter hole (70) of the transistor (22), the emitter hole (71), the base hole (72) and the collector hole (73) of the third transistor (23), and the emitter hole (74) of the fourth transistor (25). ), Base hole (75) and collector hole (7
6), an emitter hole (77) of the fifth transistor (26),
A base hole (78) and a collector hole (77) are formed.

After removing the photoresist film, the base hole (68) of the first transistor (21), the emitter hole (70) of the second transistor (22), and the base hole (70) of the third transistor (23) are again formed. 72), fourth transistor (25)
The resist film (80) covers the emitter hole (74) and the collector hole (76) of the fifth transistor (26) and the emitter hole (77) and the collector hole (79) of the fifth transistor (26). Thereafter, arsenic is ion-implanted using the resist film (80) as a mask to form an emitter region (39) in the first transistor (21) and an emitter contact region (46) in the third transistor (23).
And the collector region (44) with the fourth transistor (2
In 5), the base region (49) is connected to the fifth transistor (2
In 6), it is formed simultaneously with the base contact region (53). Here, an N ⁺ type diffusion region is formed for ion implantation of arsenic.

Finally, the resist film (80) is removed, heat treatment is performed to diffuse the N ⁺ type diffusion region downward, and then light etching is performed to remove a silicon oxide film formed on the surface of the hole.
As shown in FIG. 1N, the electrodes of the first to fifth transistors are formed by vapor deposition of aluminum.

(G) Effects of the Invention As is clear from the above description, in the lateral transistor, impurity introduction holes are formed in the insulating film corresponding to the predetermined emitter region, the predetermined collector region, and the predetermined isolation region. Therefore, the formation positions of these regions are determined in advance. Therefore, it is possible to omit the margin provided as a measure against the deviation from the design position which has been conventionally provided. Further, the area occupied by the lateral transistor can be reduced.

On the other hand, when the lateral transistor and the vertical transistor are integrated together, the introduction hole provided in the lateral transistor and simultaneously with the planned base region and the planned separation region of the vertical transistor region. Since an impurity introduction hole is provided in the corresponding insulating film, the occupied area can be reduced for the same reason as described above.

[Brief description of the drawings]

1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor integrated circuit.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yoshiaki Sano 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-59-90957 (JP, A) JP-A Sho 50-92686 (JP, A) JP-A-62-216356 (JP, A) JP-A-54-38775 (JP, A) JP-A-63-257261 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 27/06 H01L 27/08

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor integrated circuit having a lateral transistor having at least one conductivity type emitter region, wherein impurities of a buried layer of the opposite conductivity type are introduced into a semiconductor substrate of one conductivity type. Introducing an impurity of the lower diffusion region into a lower diffusion region below the upper and lower separation regions of one conductivity type surrounding the buried layer of the opposite conductivity type; A step of forming an epitaxial layer; a step of diffusing impurities in the lower diffusion region; and a step of growing a silicon oxide film formed on the epitaxial layer in the diffusion step; and a predetermined emitter of the lateral transistor. region,
Forming an impurity introduction hole in the silicon oxide film corresponding to the one conductivity type expected collector region of the lateral transistor and the upper isolation region of the one conductivity type intended upper and lower isolation region; Introducing an impurity into the upper diffusion region of the predetermined upper and lower isolation regions, the predetermined emitter region, and the predetermined collector region through the semiconductor integrated circuit. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein said lower diffusion region is upwardly diffused to a vicinity of a surface of said epitaxial layer. 3. A method for manufacturing a semiconductor integrated circuit having a lateral transistor having at least one conductivity type emitter region and a vertical transistor having an opposite conductivity type emitter region, wherein the predetermined lateral type transistor is provided. Introducing an impurity of a buried layer of the opposite conductivity type into the semiconductor substrate of the one conductivity type corresponding to the transistor and the vertical transistor of the planned vertical transistor; and Introducing an impurity in the lower diffusion region into the lower diffusion region; forming an opposite conductivity type epitaxial layer on the semiconductor substrate; and diffusing the lower diffusion region upward to near the surface of the epitaxial layer. Growing the silicon oxide film formed on the epitaxial layer in this diffusion step; and forming the silicon oxide film on the predetermined lateral transistor. The emitter region, the collector region of one conductivity type to be formed in the planned lateral transistor, the base region of one conductivity type to be formed in the planned vertical transistor, and the upper separation region of the upper and lower separation regions. A step of forming an impurity introduction hole in the corresponding silicon oxide film; and introducing an impurity into the introduction hole, the emitter region of the planned lateral transistor, and one conductivity type of the planned lateral transistor. Introducing a dopant into a planned collector region, a planned base region of the planned vertical transistor, and an upper diffusion region of the planned upper isolation region of the one conductivity type. Production method. 4. A method of manufacturing a semiconductor integrated circuit having a lateral transistor having an emitter region of at least one conductivity type and a vertical transistor of an NPN type, comprising: the predetermined lateral transistor; Forming a buried layer of the opposite conductivity type on the semiconductor substrate of the one conductivity type corresponding to the vertical transistor; and forming a lower diffusion region below the upper and lower isolation regions of the one conductivity type surrounding the buried layer. Forming a semiconductor layer of the opposite conductivity type on the semiconductor substrate; and forming an insulating film on the surface of the semiconductor layer by diffusing the lower diffusion region upward to near the surface of the semiconductor layer. The emitter region to be formed in the planned lateral transistor, a collector region of one conductivity type surrounding the emitter region, and a planned vertical transistor to be formed in the planned vertical transistor. Forming impurity introduction holes in the insulating film corresponding to the conductivity type base region and the one conductivity type isolation region; and introducing the impurity into the predetermined emitter region, the predetermined collector region, and the predetermined base region. Providing a mask in the hole and introducing an impurity into the isolation region; and, after removing the mask, introducing an impurity into all the introduction holes to form the planned separation region, the planned emitter region, and the planned A step of diffusing a collector region, providing a mask on a part of the base region of the planned lateral transistor, and adding a predetermined base contact region in the base region to the impurity, an emitter region of the planned lateral transistor, and Introducing the semiconductor device into the planned collector region.