JPH06101541B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit with greatly improved integration density.

(B) Conventional Technology As semiconductor integrated circuits have advanced in performance and functionality, high integration has become a very important point.

For example, the structure and manufacturing method of the bipolar transistor are described in detail in "Latest LSI Process Technology" Industrial Research Group (issued April 25, 1984).

As shown in FIG. 2, this bipolar transistor ( 1 ) has an N-type epitaxial layer (3) laminated on a P-type semiconductor substrate (2), and is provided between the semiconductor substrate (2) and the epitaxial layer (3). A buried layer (4) of N ⁺ type is formed in.

Further, the periphery of the buried layer (4) reaches the semiconductor substrate (2) from the surface of the epitaxial layer (3).
There is a P ⁺ -type isolation region ( 5 ). This separation area ( 5 ) is
It may be diffused all at once from the surface of the epitaxial layer, or may be diffused by the vertical separation method as shown in FIG.

Further, the isolation region ( 5 ) forms a plurality of islands formed of the epitaxial layer (3), and the island (6) therein is an N-type collector region.
Also, the P type base region (7) formed in the island (6) and the N ⁺ formed in the base region (7)
Type emitter region (8) and a collector contact region formed in a region where the epitaxial layer serving as the collector is exposed, and a SiO ₂ film contact hole formed on the epitaxial layer (3) There is a respective electrode formed through.

Next, a method of manufacturing this bipolar transistor ( 1 ) will be described. First, a SiO ₂ film is formed on a P-type semiconductor substrate (2), a diffusion hole of an embedding layer (4) is formed in this SiO ₂ film, and antimony is added to the semiconductor substrate (2) through the diffusion hole. There is a first step to diffuse into.

Here, in the case of FIG. 2, since the separation region ( 5 ) is achieved by upper and lower separation, boron is diffused into the semiconductor substrate (2) through a diffusion hole, and the P ⁺ -type lower diffusion layer is formed. (1
0) is also formed.

Next, an epitaxial layer (3) is laminated on the surface of the semiconductor substrate (2), and a SiO ₂ film is formed on this epitaxial layer (3). In this SiO ₂ film, a diffusion hole in the upper diffusion region (11), which is to be the separation region ( 5 ), is formed by applying a photoresist film, mask alignment, exposure, etching, etc., and boron is diffused through this diffusion hole. There is a second step of forming the isolation region ( 5 ).

Then, a diffusion hole of the base region (7) is formed in the SiO ₂ film again by applying a photoresist film, mask alignment, exposure, etching, etc., and boron is diffused through the diffusion hole to form a base region (7). There is a third step of forming 7).

Further, diffusion holes of the emitter region (8) and the collector contact region (9) are formed in the SiO ₂ film by applying a photoresist film again, mask alignment, exposure, etching, etc., and arsenic is diffused through the diffusion holes. Then, there is a fourth step of forming the emitter region (8) and the collector contact region (9).

Finally, contact holes of the emitter region (8), the base region (7) and the collector contact region (9) are formed in the SiO ₂ film again by applying a photoresist film, aligning the mask, exposing and etching. There is a fifth step in which Al is vapor-deposited to form each electrode to form an integrated circuit.

(C) Problem to be Solved by the Invention The bipolar transistor ( 1 ) is achieved by the above-described first to fifth steps. However, the formation positions of the diffusion holes in the second process, the third process, and the fourth process deviate from the designed values due to mask alignment and etching.

In FIG. 2, the upper diffusion region (11) of the upper and lower separation regions ( 5 )
When the diffusion depths of 1 and 4 μm and the diffusion depth of the base region (7) are 4 μm and 1 μm, respectively, they spread to the same extent in the lateral direction. Further, the base region (7) and the collector contact region (9) may be shifted to the left as shown by the broken line in FIG. 2 due to mask alignment and etching. Of course, the same can be said for the right direction and the direction perpendicular to the paper surface. In consideration of this, the width (about 2 μm) that is a margin to the original design value width
Is provided and has a width shown by an arrow to prevent contact with each diffusion region. Therefore, a margin of 4 μm is set on each side of each of the integrated transistors, which is an obstacle to the improvement of the integration degree.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and includes a planned base region (34) of a semiconductor layer (23), a planned collector contact region (36), and an isolation region ( 25 ). Introducing holes (54), (5) for impurities in the insulating film (51) on the semiconductor layer (23) corresponding to
3) and (52) are formed, and a mask (56) is provided in the introduction holes (54) and (53) on the planned base region (34) and the planned collector contact region (36). A step of diffusing impurities to form the isolation region (27), and after removing the mask (56), a mask (5) is formed in the introduction hole (53) on the planned collector contact region (36).
7) is provided and then impurities are diffused to form the base region (3
The problem is solved by including the step of forming 4).

(E) Operation By forming the introduction holes (52), (53) and (54) at the same time, the formation positions of the isolation region (27), the base region (34) and the collector contact region (36) can be determined. Therefore, it is possible to omit the margin that is conventionally provided due to the deviation of the forming position.

(F) Embodiments Embodiments of the present invention will be described below. First, for convenience of description, the structure of the semiconductor integrated circuit ( 21 ) will be described with reference to FIG. 1J.

As shown in FIG. 1J, N is formed on the P-type semiconductor substrate (22).
A type epitaxial layer (23) is provided, and an N ⁺ type buried layer (24) is provided between the epitaxial layer (23) and the semiconductor substrate (22).

Around the buried layer (24), there is an isolation separation region ( 26 ) that reaches the semiconductor substrate (22) from the surface of the epitaxial layer (23), and as shown in the figure, the lower diffusion region (26) and the upper diffusion region are formed. It consists of (27).

A plurality of islands are formed by this isolation region ( 25 ). The first island (28) has a transistor ( 29 ), the second island (30) has a MOS capacitor element (31) and a third island.
The island (32) has a diffusion resistance element ( 33 ).

The transistor ( 29 ) includes a collector region (28) formed of the epitaxial layer, a P-type base region (34) formed in the island (28), and an N-type formed in the base region (34). Of the emitter region (35), and a collector contact region (36) and a base contact region (37) are formed in the collector region (28) and the base region (34), respectively.

The MOS capacitor element ( 31 ) is a dielectric composed of an N ⁺ -type lower layer electrode region (38) formed in the island (30) and a silicon nitride film formed on the lower layer electrode region (38). (39), an upper layer electrode (40) formed on the dielectric (39), a contact region (41) formed in the lower layer electrode region (38), and an ohmic contact region (41). The lower electrode (42) in contact therewith.

Further, the diffusion resistance element ( 33 ) is formed on the island (32).
It is composed of a P type diffusion resistance region (43) formed inside and a P ⁺ type contact region (44) formed at both ends of the diffusion resistance element (43).

Next, a method of manufacturing the semiconductor integrated circuit ( 21 ) of the present invention will be described in detail.

First, as shown in FIG. 1A, a thermal oxide film is formed on the surface of a P-type silicon semiconductor substrate (22) with an impurity concentration of about 10 ¹⁵ atom / cm ³ , and then an N ⁺ -type buried layer (24) is to be formed. After etching the region, N-type impurities such as antimony and arsenic are doped through this opening.

Then, as shown in FIG. 1B, a thermal oxide film is formed on the region where the lower diffusion region (26) of the P ⁺ -type upper and lower isolation regions ( 25 ) is to be formed, and the P-type impurity is introduced through this opening. Is doped with boron.

Next, as shown in FIG. 1C, the thermal oxide film on the semiconductor substrate (22) is completely removed, and then N of the specific resistance of 0.1 to 5 Ω · cm is formed on the semiconductor substrate (22) by a known vapor phase growth method. An epitaxial layer (23) of the mold is formed with a thickness of 2 to 8 μm. At this time, the previously doped impurities are normally diffused.

Next, after forming a thermal oxide film on the surface of the epitaxial layer (23) by thermal oxidation at a temperature of about 1000 ° C. for several hours,
The entire semiconductor substrate is heat-treated again to re-diffuse the previously doped impurities.

Therefore, the lower diffusion region (26) is upwardly diffused to about half of the epitaxial layer (23). Further, in this step, the thermal oxide film on the surface of the epitaxial layer (23) grows to a thickness of several thousand liters, and this thermal oxide film (51) exhibits a function similar to that of a mask described later. However, the thermal oxide film may be entirely removed, and a silicon nitride film or the like may be used as a diffusion mask, or a silicon oxide film may be formed by a CVD method.

Further, if the thickness of the epitaxial layer is reduced to about half that of the conventional one, the lower diffusion region (26) is shallowed correspondingly. Therefore, the lateral spread can be reduced.

Subsequently, as shown in FIG. 1D, the silicon oxide film (51) on the lower electrode region (38) of the predetermined MOS capacitor element ( 31 ) is removed, and a ring lath, for example, is formed on the entire surface. Then, heat treatment is performed at a predetermined temperature for a predetermined time to diffuse phosphorus into the epitaxial layer (23). Then, the ring lath is removed with a predetermined etching solution, and heat treatment is performed again so as to reach a predetermined depth.

Subsequently, as shown in FIG. 1E, the upper diffusion region (27) of the planned upper and lower isolation regions ( 25 ), the planned collector contact region (36), the planned base region (34) and the planned diffusion resistance region (43). ) Corresponding to the above), there is a step of forming impurity introduction holes (52), (53), (54) and (55) in the silicon oxide film (51).

Here, the positive resist film is used as a mask and is formed by dry etching. After this, the epitaxial layer (2
Dummy oxidation is performed on the exposed region of 3) to form a dummy oxide film. This dummy oxide film reduces damage to the epitaxial layer (23) due to the subsequent ion implantation step,
It is also used to randomly disperse and uniformly implant ions.

Subsequently, as shown in FIG. 1F, the planned collector contact region (36), the planned base region (34), and the introduction holes (53), (54), (55) on the diffusion resistance region (43). A mask (56) is provided to diffuse the impurities to form the upper diffusion region (27).

Here, after covering the entire surface with a resist film capable of blocking implanted ions, a so-called mask (56), the mask (56) corresponding to the upper diffusion region (27) is removed, and boron, which is a P-type impurity, is removed. Implantation is performed under predetermined conditions to form the upper diffusion region (27).

In this step, even if the opening of the mask (56) is formed larger than the introduction hole (52) of the silicon oxide film (51) as shown in the figure, since the silicon oxide film (51) acts as a mask, the introduction hole ( 52) and the upper diffusion region (27) are formed at the same position.

After that, the mask (56) is removed and a predetermined heat treatment is performed so that the upper diffusion region (27) reaches the lower diffusion region (26) as shown in FIG. 1G.

Subsequently, as shown in FIG. 1G, a mask (57) is formed in the introduction hole (53) on the predetermined collector contact region (36), and impurities are diffused from the introduction holes (52), (54) and (55). Then, there is a step of forming the base region (34).

Here, since the mask (56) is completely removed in the previous step and the mask (57) is formed in the introduction hole (53), the upper diffusion region (27), the base region (34) and the resistance diffusion region (4) are formed.
The introduction holes (52), (54), (55) of 3) are exposed. In this state, boron (B) is ion-implanted.

Therefore, the base region (34) is formed, and at the same time, the resistance diffusion region (43) is formed. At the same time, the upper diffusion area (2
Impurities are diffused again into 7).

The feature of the present invention resides in FIGS. 1E to 1G described above.

Traditionally the formation of isolation regions ( 25 ) and the base region (34)
Although a margin was provided so that contact between both regions would not occur even when a deviation from the design value occurs at the time of forming, the present application preliminarily introduces the introduction holes (52), (53), (54), ( 55) forming
Since the formation position is determined by this introduction hole, it is not necessary to provide the above margin.

That is, as shown in FIG. 1F, the formation position of the isolation region ( 25 ) can be determined by simply providing a mask in the introduction holes (54) and (53) of the base region (34) and the collector contact region (36). It can be determined by the introduction hole (52) of ( 25 ). The base region (34) is determined by the introduction hole (54) of the base region (34) formed in advance. Therefore, there is no need to worry about the misalignment of the mask and the misalignment of the introduction hole in the base region, which are shown in the conventional example. As shown in FIG. 1E, once the introduction holes (52), (54), (55) are formed with high accuracy, the formation positions of the diffusion regions (27), (34), (43) are formed with this accuracy. Can be realized.

Moreover, since the ion diffusion is performed by ion implantation, the diffusion depth of each diffusion region can be made smaller than that of thermal diffusion, so that the lateral spread can be minimized. Also, the base area (3
By making the diffusion depth of 4) shallower than that of the conventional one, it is possible to prevent further spreading in the lateral direction.

For these reasons, a margin is not required around the base region (34) and is unnecessary in the vertical and horizontal directions in a plan view, so that the margin can be significantly reduced and the cell size can be reduced.
Therefore, in a highly integrated chip, the chip size can be significantly reduced.

In the step of FIG. 1G, a mask was formed on the introduction hole (53) to diffuse the impurity. However, in the present application, a mask is provided on the introduction hole (52) on the isolation region (27) and then impurities are diffused. The base region (34) may be diffused.

As described with reference to FIG. 1F, the base region (34) can be accurately determined only by making the opening of the mask (57) corresponding to the base region (34) slightly larger than the introduction hole (54). . Here, the mask can prevent excess impurities from being implanted into the isolation region (27).

Then, the collector contact region (36) shown in FIG. 1H.
Is formed through the introduction hole (53). As in the previous step, a mask is provided, and here the introduction holes (52), (5
It is provided on 4) and (55). Then, arsenic, which is an N-type impurity, is ion-implanted.

Also in this step, an opening of the mask is formed larger than the introduction hole (53), and the formation position of the front introduction hole (53) determines the formation position of the collector contact region (36).

Further, the collector contact region (36) in this step is diffused through the introduction holes (52), (53), (54) and (55),
At the very end, it diffuses through the introduction hole (53). This is to prevent lateral spread of the collector contact region (36).

The introduction holes (52) (5) formed in advance by the above steps
The position of each diffusion region can be determined by 3), (54), and (55), and the cell size can be reduced without providing a margin as described above.

Then, as shown in FIG. 1H, on the region corresponding to the base contact region (37) to be formed in the base region (34) and on the contact region (44) of the isolation region (27) and the diffusion resistance region (43). There is a step of forming a photoresist film (58) serving as a mask so that the holes are opened.

Then, there is a step of implanting boron (B) ions.

Then, the photoresist film (58) is removed, and a phosphorus-doped silicon oxide film is formed on the entire surface.

Further, as shown in FIG. 1I, the negative type photoresist film is used to remove the silicon oxide film (51) on which the intended dielectric thin film (39) of the MOS capacitor element (31) is formed. There is a step of forming (39).

Here, the silicon oxide film (51) is opened by wet etching, and a silicon nitride film (39) of several hundred liters is formed on the entire surface. Then, chemical dry etching is performed as shown in the figure.

Finally, by anisotropic etching using the host resist film as a mask, the planned emitter region (35), base contact region (37), collector contact region (36),
The silicon oxide film (51) on the contact region (41) of the lower electrode (42) and the contact region (44) of the diffusion resistance region (43) is removed. Then, after removing the photoresist film, the planned emitter region (35), the planned collector contact region (36), and the epitaxial layer corresponding to the contact region (41) of the lower electrode (42) are exposed again, Form a photoresist film.

Then, using this host resist film as a mask, arsenic (A
(s) is ion-implanted to form the emitter region (35) and the contact region (41) of the lower layer electrode (42).

Then, the resist film is removed, heat treatment is performed to diffuse the emitter region (35) downward, and then light etching is performed to form an aluminum electrode as shown in FIG. 1J.

As described above, in order to form the introduction holes (52), (53), (54) at one time, the planned emitter region (35), collector contact region (36) and base contact region (37) are formed.
The upper silicon oxide film (51) has the same thickness. Therefore, the opening of the transistor ( 29 ) can be etched at the same time, and the etching of the epitaxial layer of the emitter region (35) can be prevented.

(G) Effect of the Invention As is clear from the above description, the introduction holes of the impurities are accurately formed in the insulating film corresponding to the planned base region, the planned collector contact region, and the planned isolation region of the semiconductor layer. Then, a mask is provided in the introduction holes on the planned base region and the planned collector contact region to form an isolation region, the mask is removed, a mask is provided on the planned collector contact region, and impurities are introduced to form the base. By forming the region and forming the collector contact region through the planned introduction hole of the collector contact region, the formation positions of the base region and the collector contact region can be determined by the introduction hole formed with high precision in advance. Therefore, the shift due to the base region and the collector contact region can be greatly reduced, and the margin due to the shift that has been conventionally provided can be greatly reduced.

Therefore, since this margin can be reduced around the base region and collector contact region, the cell size can be reduced, and in the case of an integrated circuit, this reduction area can be reduced by the number of cells, resulting in a large chip size. Can be reduced.

Since the base region and the isolation region have the same conductivity type, they can be formed without forming a mask. Therefore, the host resist process can be omitted, and the yield can be improved accordingly.

Then, after the step of forming the isolation region, the mask is removed, and the mask is provided again on the isolation region to form the base region and the collector contact region. By making the area and the collector contact area larger than the introduction holes, the positioning can be performed with the accuracy of the introduction holes formed in advance. Therefore, accurate positioning can be performed without injecting extra impurities into the isolation region, and the cell size can be greatly reduced as described above.

On the other hand, since the introduction holes of the base region and the collector contact region are formed at one time, the film thickness of the silicon oxide film on this region is almost the same. Therefore, diffusion holes in the emitter region,
The contact hole in the base contact region and the contact hole in the collector contact region end at almost the same time even if they are etched at once. Therefore, since the etching of the emitter region can be prevented, the yield of the transistor can be improved, and the number of steps can be reduced because separate etching is not required.

[Brief description of drawings]

1A to 1J are sectional views showing a method for manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor integrated circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 29/73 (72) Inventor Nobuyuki Sekikawa 2-18 Keiyo Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. Company (72) Inventor Tadayoshi Takada 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Inventor Yasuhiro Tamada 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72 ) Yoshiaki Sano 2-18, Keihan Hondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) Reference JP-A-55-67141 (JP, A) JP-A-55-105344 (JP, A) JP JP-A-57-50424 (JP, A) JP-A-60-111466 (JP, A) JP-A-1-89359 (JP, A)

Claims (3)

[Claims] 1. An opposite conductivity type epitaxial layer is laminated on the entire surface of the one conductivity type semiconductor substrate, and the semiconductor substrate is heat-treated to separate one conductivity type upper and lower layers provided between the semiconductor substrate and the epitaxial layer. A step of diffusing impurities in the lower diffusion layer of the region so as to bury it up to more than half of the epitaxial layer, and a mask for ion implantation of a silicon oxide film or a silicon nitride film on the epitaxial layer 1
Forming a layer insulating film, and corresponding to a predetermined base region, a predetermined collector contact region and a predetermined upper diffusion layer of the upper and lower isolation regions in the one-layer insulating film formed on the epitaxial layer. A step of simultaneously forming an impurity introduction hole in the one-layer insulating film; and an introduction hole of the upper diffusion layer by covering the introduction holes on the predetermined base region and the predetermined collector contact region with an ion implantation mask. Impurities are ion-implanted through
Forming an upper diffusion layer of the upper and lower isolation regions, removing the mask, providing an ion implantation mask in the introduction hole of the predetermined collector contact region, and ion implantation of impurities through the introduction hole of the base. Implanting and forming the base region, and after removing the mask, a mask for ion implantation is provided in the upper diffusion layer of the upper and lower isolation regions and the introduction hole of the base region, and the predetermined collector contact region is formed. And a step of forming the collector contact through an introduction hole. 2. In the step of forming the base region, after removing the mask for ion implantation, impurities are simultaneously ion-implanted through the introduction holes of the upper diffusion layer of the predetermined base region and the upper and lower isolation regions. By injecting
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein impurities are reintroduced into the upper diffusion layer at the same time when the base region is formed. 3. In the step of forming the base region, after removing the mask for ion implantation, ion implantation is performed in the introduction hole on the upper diffusion layer of the predetermined collector contact region and the upper and lower isolation regions. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the base region is formed by covering the mask and ion-implanting impurities through the planned introduction holes of the base region.