JP3039393B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a gate array type semiconductor integrated circuit device comprising CMOS basic cells.

[0002]

2. Description of the Related Art In recent years, this type of gate array type semiconductor integrated circuit device has been developed by computer-aided design and manufacturing (CA).
(D, CAM) technology can be designed and manufactured at a short delivery time and at low cost, so that it is widely used as a semiconductor integrated circuit device of various kinds and small-quantity production used for personal computers, communication devices, home electric appliances and the like. ing.

FIG. 7 is a layout plan view showing one of a plurality of CMOS basic cells formed side by side in an internal region on a semiconductor chip of a general first semiconductor integrated circuit device of this kind. For reference, the CMOS basic cell of the first conventional semiconductor integrated circuit device includes N-type diffusion regions (N-type regions) 1 and 4 and P-type diffusion regions (P-type regions) 2 and 2.
And two P-channel type MOs formed in the P-type diffusion region (P-type region) 2 and having the same channel width and channel length.
Similarly to the S transistors P1 and P2, the N type diffusion region (N
(Channel region) 4 and two N-channel MOS transistors N1 and N2 having the same channel width and channel length.

Source / drain (transistor) of P-channel type MOS transistors P1 and P2 in P-type region 2
Including regions 5 to 7 and N-channel type MOS in N-type region 4
Includes transistor regions 8 to 10 of transistors N1 and N2.

P and N channel type MOS transistors P
A set of N1, N1 and a set of P2, N2 each have a common gate electrode (polysilicide) G made of polysilicon.
1 and G2. The gate electrode G1 includes an upper terminal region U1 arranged at the upper end of the transistor P1, a central terminal region T1 at the center of the transistors P1 and N1, and a lower terminal region S1 arranged at the lower end of the transistor N1. The gate terminal GT1 is disposed in the upper terminal region U1, the gate terminals GT2 and GT5 are disposed in the central terminal region T1, and the gate terminal GT6 is disposed in the lower terminal region S1. The gate electrode G2 includes an upper terminal region U2 disposed at the upper end of the transistor P2, a central terminal region T2 at the center of the transistors P2 and N2, and a lower terminal region S2 disposed at the lower end of the transistor N2. Upper terminal area U2
, A gate terminal GT3, a gate terminal GT4 and GT7 in the central terminal region T2, and a gate terminal GT8 in the lower terminal region S2.

The layout plan view also shows horizontal grids K1 to K12 and vertical grids KA to KD for designating the position coordinates of each part of the basic cell for design support. As is well known, in this type of semiconductor integrated circuit device, all wirings are arranged along these lattices.

Referring to FIG. 7 again, the gate terminal GT
2, GT4 is a gate terminal GT on the central grid K6.
5, GT7 is arranged on the lattice K7. However, the gate terminal is not disposed at the intersection of the lattice KC and the lattices K6 and K7, and is unused.

Next, FIG. 8 shows an equivalent circuit of a buffer circuit composed of the basic cells of FIG. 7 and a layout diagram thereof.
Referring to (A) and (B), this circuit includes a two-stage CMOS inverter including transistors PM1 and NM1 and transistors PM2 and NM2, respectively. Here, for convenience of explanation, the transistor of the equivalent circuit is hereinafter referred to as P
M1 and NM1, etc., and the transistors in the layout diagram are indicated as P1, N1, etc., the transistor P
M1, PM2, NM1, and NM2 correspond to the transistors P2, P1, N2, and N1, respectively.

Referring again to FIG. 8B, output signals from transistors P2 and N2 corresponding to transistors PM1 and NM1 of the first inverter to transistors P1 and N1 corresponding to transistors PM2 and NM2 of the second inverter. When the wiring and the gate input wiring of these transistors P1 and N1 are provided, the gates of the transistors P2 and N2
The position of the G terminal must be one of the two terminals GT4 or GT7 in the central terminal area T2. Here, the position of the gate terminals of the transistors P2 and N2 is GT4,
An example in which the input terminal H01 is connected to the terminal GT4 is shown.

The output signal wiring W1 of the transistors P2 and N2 corresponding to the transistors PM1 and NM1 is disposed on a lattice KC which is on a straight line between the P-type transistor region 6 and the N-type transistor region 9, and is disposed on the central terminal region T2. Are connected to the gate terminal GT5 on the central terminal region T1 (lattice KB-K7) corresponding to the input gate terminal positions of the transistors P1 and N1 while avoiding the input gate terminals GT4 of the transistors P2 and N2. Further, since the input gate terminal positions of the transistors P1 and N1 are located at GT5 on the central terminal region T1, the transistors P1 and N1 corresponding to the transistors PM2 and NM2 are provided.
The wiring W2 to the output terminal N01 is a wiring using the outer grid of the central terminal area T1.

Next, referring to FIGS. 9A and 9B which show an equivalent circuit of a three-input AND circuit constituted by using two basic cells of FIG. 1 and a layout diagram thereof, respectively, A NOR circuit including transistors PM1 to PM3 and transistors NM1 to NM3 formed in a range of two cells of symmetrically arranged basic cells C1 and C2 and a CMOS inverter including transistors PM4 and NM4 are provided.

Referring to FIG. 9B, the transistor regions 15 to 17 and 18 to 20 of the basic cell C1 and the basic cell C
Two transistor regions 25 to 27 and 28 to 30 are arranged in line symmetry, and P-channel type MOS transistors P11 and P
12, P21, P22 and N-channel MOS transistors N11, N12, N21, N22. Equivalent circuit transistors PM1, PM2, PM3
Each of PM4, NM1, NM2, NM3 and NM4 is a transistor P11, P12, P22, P21, N11,
They correspond to N12, N22, and N21, respectively.

The transistors PM1, PM2, PM2 of the equivalent circuit
Transistors P11, P12, P corresponding to PM3 and NM1
The output signal wiring W3 commonly connected to the drains of the drains 22 and N11 is connected to the input gate terminal GT22 of the transistors P21 and N21 corresponding to the transistors PM4 and NM4. In this case, the transistors P1 1, N1 1 for connecting to the input terminal H01 gate - DOO terminals are arranged in the gate terminal GT 1 5 on the central terminal region T11 ie lattice KB1-K7. Therefore the output signal line W3 of the transistor P1 1, N1 1 is a wiring using outer lattice of the central terminal region T11. Further, the transistors PM4 and NM4
Since the input gate terminal positions of the corresponding transistors P21 and N21 are on the lattice KB2-K6, that is, in the central terminal region T21, the wiring W4 to the output terminal N01 is a wiring using the outer lattice of the central terminal region T21.

As described above, in the first conventional semiconductor integrated circuit device, for example, the contact CT can be arranged as an input terminal necessary for forming the transistors PM1 and NM1 of the first-stage inverter of the buffer circuit. The gate terminal positions are defined by the lattices KD-K6 and KD-K on the central terminal region T2.
7 only. Since the output wiring W1 of the transistors PM1 and NM1 is wired avoiding the input terminal H01, it has to be wired on a straight grid KC of the transistor regions 6 and 9. Also, the input terminals of the transistors P2 and N2 of the second-stage inverter have to be arranged at the terminal GT5 or GT2 on the limited lattice KB on the central terminal region T1, and furthermore, the wiring W2 to the output terminal N01. Also, wiring must be performed on the grid outside the transistor regions 5 and 8 in order to avoid the input terminals. In this conventional basic cell configuration, the degree of freedom in wiring is small and the length of wiring is long, and problems such as an increase in transmission delay time due to wiring resistance, wiring load capacitance, and the like have arisen. In addition, since the wiring protrudes outside the transistor region, the utilization efficiency of the chip area is reduced.

[0015] To solve the above problems, Japanese Patent Laid-Open Publication No.
The second conventional semiconductor integrated circuit device described in Japanese Patent No. 30972 has a structure in which a part of each of the P-type and N-type transistor regions is protruded, and these protruding portions are connected to a power supply line to provide a wiring. The grid is being reduced.

Further, the third conventional semiconductor integrated circuit device described in Japanese Patent Application Laid-Open No. 3-123076 has a wiring structure provided with a wiring layer independent of a normal connection wiring layer for wiring between function blocks. Improving efficiency.

[0017]

In the first conventional semiconductor integrated circuit device described above, the gate terminal position at which the input terminal and the output terminal can be arranged is the gate terminal at the boundary between the P and N channel transistor regions at the center of the cell. Since it is limited to two places in the region, one of the input / output wirings connected to each of the input terminal and the output terminal is forced to pass outside the transistor region of the cell, so that the degree of freedom of wiring is small, and There is a drawback that the length becomes longer and the transmission delay time increases due to wiring resistance, wiring load capacitance, and the like. In addition, since the wiring protrudes outside the transistor region, there is a disadvantage that the efficiency of using the chip area is reduced.

In the second conventional semiconductor integrated circuit device which improves the efficiency of using the chip area among the above-mentioned disadvantages, the diffusion region other than the transistor region is directly connected to the power supply and the ground due to the deformation of the transistor region. However, there is a drawback in that the influence of such an element on the transistor characteristics, such as diffusion resistance and current, makes it difficult to achieve desired characteristics.

Further, in the third conventional semiconductor integrated circuit device in which the wiring area is made more efficient by providing an independent connection wiring layer that is not normally used for the connection between the function blocks, a new wiring layer is provided. Therefore, there is a drawback that the cost for one layer is increased and the wiring resistance is increased.

[0020]

A semiconductor integrated circuit device according to the present invention is constituted by arranging a plurality of CMOS type basic cells and forming a horizontal horizontal grid and a vertical vertical grid respectively set at a predetermined pitch. based in the semiconductor integrated circuit device of the gate Toarei scheme setting the position coordinates of the internal this CMOS type basic cell, the CMOS-type basic cell, the first conductivity type diffusion region including the 3 duty at least the longitudinal grid A first transistor region that is a source region or a drain region formed along a central second vertical lattice and shares a first transistor region on the left and a third vertical lattice on the right of the second vertical lattice, respectively; And first and second transistors of the first conductivity type respectively formed along the first and second horizontal lattices, which are two lattices of the horizontal lattice in the vertical direction from the first transistor region. Width including The second and third transistor regions, which are source regions or drain regions formed along the second vertical lattice, of the second conductivity type diffusion region arranged via the central portion share the first and third regions, respectively. Of the second conductivity type formed along each of the vertical lattices of
And a first central terminal region disposed between the first vertical lattice and the second vertical lattice, occupying the left side of the central portion, and arranging a gate wiring terminal. And a first gate electrode common to the third transistor and a third gate arranged between the second vertical grid and the third vertical grid, occupying the right side of the central portion and arranging a gate wiring terminal. The second transistor and the fourth transistor, the second transistor and the fourth transistor having a common second gate electrode, and the first to second transistors included over the first and second central terminal regions. No. 3 terminal arrangement candidate points for arranging the gate wiring terminals which can be arranged only at each of the intersections of the vertical lattice and the first and second horizontal lattices.
And a total of at least six central terminal regions.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1, which shows a first embodiment of the present invention in a layout plan view using common characters / numerals for components common to those in FIG. The CMOS basic cell of the semiconductor integrated circuit device of the present embodiment shown in FIG. 1 has N-type diffusion regions (N-type regions)
P-type MOS formed in P-type diffusion region (P-type region) 2 including P-type diffusion region (P-type region) 2 and 3
Similarly to the transistors P1 and P2 , the N-type diffusion region (N
N-type MOS transistors N1 and N2 formed in the (type region) 4.

P and N channel type MOS transistors P
A set of N1, N1 and a set of P2, N2 each have a common gate electrode (polysilicide) G made of polysilicon.
1 and G 2 .

The gate electrode G 1 is conventionally an addition to a common upper terminal region U1 and the lower terminal region S1, the transistors P1, 3 pieces of the gate terminal in central N1 GT2, GT
5, a central terminal area T1A for arranging the input / output terminals of the unit circuit block having the GT10. The gate electrode G 2 is, in common with the conventional in addition to the upper terminal region U2 and the lower terminal region S2, the unit circuit blocks having a gate terminal GT4, GT7, GT9 three in a central portion of the transistor P2, N2 Central terminal area T2 for arrangement of input / output terminals
A. Thereby, the conventionally unused KC-K6, KC-K6
7 can effectively be used.

Next, referring to FIG. 2, which shows a layout diagram of a buffer circuit common to the conventional one constituted by the basic cells of FIG. 1 using common characters / numerals for common components to FIG. 8, FIG. As described above, the central terminal region T
The gratings KC-K6 and KC-K7 of 2A and T1A can be used as gate terminals GT9 and GT10, respectively. Thereby, the transistor P of the first-stage inverter
The output signal lines from the transistors P2 and N2 corresponding to M1 and NM1 to the transistors P1 and N1 corresponding to the transistors PM2 and NM2 of the second inverter and the wiring W1A of the gate input signal lines of these transistors P1 and N1 are connected to the transistor P2. The connection terminals CT of the lattices KD-K4 and KD-K5 pass through the central terminal region T2A and directly connect to the connection terminals of the lattices KD-K8 and KD-K9 of the transistor N2, and the lattice KD-K7 on the central terminal region T2A. from that connection to the terminal GT 10 on the central terminal region T2A. Thus, the wiring area for four grids can be reduced as compared with the conventional buffer circuit.

Since the terminal GT2 on the central terminal region T1A can be used as the output terminal N01, the wiring W2 to the output terminal N01 of the transistors P1 and N1 is connected to the terminal G2.
A simple linear wiring via T2 may be used, and a detour to avoid the central terminal region T1A is unnecessary. Thus, the wiring area for three grids can be reduced as compared with the conventional buffer circuit.

Next, a circuit block B1 of a three-input AND circuit common to the conventional one constructed using two basic cells of FIG.
FIG. 3 showing a layout diagram of FIG. 9 using common characters / numerals for common components to FIG. 9 shows transistors PM1, PM2, and PM3 of an equivalent circuit of the three-input AND circuit of the present embodiment shown in FIG. A wiring W3A for an output signal, which commonly connects the drains of the transistors P11, P12, P22, and N11 of the circuit block B1 corresponding to PM3 and NM1,
The transistors PM4 and NM4 on the central terminal region T21A
It is connected to the input gate terminal GT30 of the corresponding transistor P21, N21. Specifically, the wiring W3A is connected to the drain connection terminal CT (the lattice KB) of the transistor N11.
1-K9, KB1-K8) to the terminals GT5, G52 (lattices KB1-K7, KB1-K) on the central terminal region T11A.
6) through the lattice KB1-K on the transistor P11
5 in a straight line, and from the lattice KB1-K5, turn right at right angles to the lattices KC1-K5, KD1-K5, KD2-K5.
Go straight to KC2-K5 and turn right again to connect to terminal GT29 in central terminal area T2A2 and terminal GT30 in central terminal area T21A. Further, the gate terminal of the input terminal H01 can be arranged at the terminal GT20 in the central terminal region T11A. As a result, the wiring W3A is connected to the conventional central terminal region T.
Detour for avoiding 11A is not required, and the wiring area for 5 grids can be reduced.

Similarly, the input gate terminals of the transistors P21 and N21 are located at the terminal GT3 of the central terminal region T21A.
0, the wiring W4A to the output terminal N01
Is a straight line via the terminals GT22 and GT25 in the central terminal region T21A, thereby reducing the wiring area for three grids that does not need to be bypassed.

Referring to FIG. 4A, which is a schematic plan view showing a first modification of the embodiment, FIG. 4A shows a state where two circuit blocks B1 are vertically stacked in the Y direction. And the power lines 101, 100, and 102 extending in the X direction in the region of FIG.

Referring to FIG. 4B, which is a schematic plan view showing a second modification of the present embodiment, circuit blocks B1 are vertically stacked in the Y direction. Power lines 10 extending in the Y direction of each region
3 and 104 are shown.

Further, referring to FIG. 4C, which is a schematic plan view showing a third modification of the present embodiment, FIG. 4C shows that the P and N type diffusion regions are vertically stacked in the Y direction from the circuit blocks B1. Circuit block B1 in which 11, 21, 13, and 23 are omitted
A is shown.

Next, a second embodiment of the present invention will be described with reference to FIG. 5 which is a layout plan view using common characters / numerals for constituent elements common to FIG. Is different from the first embodiment in that four gate terminals GT2, GT5 and GT are used instead of the central terminal region T1A.
9 and a central terminal region T1B for arranging the GT 10,
The point is to provide a conventional two-terminal central terminal region T2 instead of the central terminal region T2.

In the present embodiment, as in the first embodiment, the output wiring in the preceding stage can be arranged in a straight line without bypassing the central terminal region, so that the wiring area can be reduced.

Next, a third embodiment of the present invention will be described with reference to FIG. 6 which is a layout plan view using common characters / numerals for constituent elements common to FIG. The difference between the first embodiment and the first embodiment is that the gate electrode G
Each of the upper terminal area U1A and the lower terminal area S1 and the upper terminal area U2 and the lower terminal area S2 instead of 1A and G2A.
A is to provide gate electrodes G1B and G2B each having A.

The upper terminal region U1A has a gate terminal GT11 in addition to the gate terminal GT1 common to the first embodiment.
The lower terminal region S2A has a gate terminal GT12 in addition to the gate terminal GT8 common to the first embodiment. This increases the degree of freedom in wiring.

[0035]

As described above, according to the semiconductor integrated circuit device of the present invention, the center ends of each of the first and second gate electrodes are provided.
Child area, sums both by having a terminal arrangement candidate points for the arrangement of at least six of the gate line terminal,
Since the number of terminals that can be arranged in the central terminal region of the gate electrode can be substantially increased, the degree of freedom of the input / output wiring of the transistors constituting the circuit block is increased, the wiring for signal transmission can be shortened, and the optimum layout is facilitated. Therefore, there is an effect that the circuit area can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view schematically showing a basic cell of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view schematically showing a layout of a buffer circuit formed using the basic cells of the present embodiment.

FIG. 3 is a schematic plan view schematically showing a layout of a three-input AND circuit configured using the basic cells of the present embodiment.

FIG. 4 is a schematic plan view schematically showing first to third modifications of the present embodiment.

FIG. 5 is a schematic plan view schematically showing a basic cell of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a schematic plan view schematically showing a basic cell of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 7 is a schematic plan view schematically showing a basic cell of a first conventional semiconductor integrated circuit device.

FIG. 8 is a circuit diagram showing an equivalent circuit of a buffer circuit configured using basic cells of a conventional first semiconductor integrated circuit device, and a schematic plan view schematically showing a layout thereof.

FIG. 9 is a circuit diagram showing an equivalent circuit of a three-input AND circuit configured using basic cells of a conventional first semiconductor integrated circuit device, and a schematic plan view schematically showing a layout thereof.

[Explanation of symbols]

1,4 N-type diffusion region 2,3 P-type diffusion region 5-7,8-10 Transistor region G1, G2, G11, G12, G21, G22, G1
A, G2A, G11A, G12A, G21A, G22
A, G1B, G2B Gate electrodes GT1 to GT12 Gate terminals S1, S2, S11, S12, S21, S22, S2B
Lower terminal area T1, T2, T1A, T2A, T11, T12, T2
1, T22, T11A, T12A, T21A, T22
A, T1B Central terminal area U1, U2, U11, U12, U21, U22, U1B
Upper terminal area N1, N2, N11, N12, N21, N22, NM
1, NM2, NM11 to NM14 N-channel type MO
S transistors P1, P2, P11, P12, P21, P22, PM
1, PM2, PM11-PM14 P channel type MO
S transistor

Claims (4)

(57) [Claims] A position coordinate inside the CMOS type basic cell is set based on a horizontal horizontal grid and a vertical vertical grid which are configured by arranging a plurality of CMOS type basic cells at predetermined pitches. in the semiconductor integrated circuit device of the gate Toarei manner, the CMOS-type basic cell, at least the longitudinal grating 3
The first transistor region which is a source region or a drain region formed along the second vertical lattice at the center of the diffusion region of the first conductivity type including the main transistor and shares the left and right sides of the second vertical lattice, respectively. And first and second transistors of the first conductivity type formed along each of the first and right third vertical lattices, respectively; and two of the horizontal lattices in the vertical direction from the first transistor region. A source region or a drain region formed along the second vertical lattice of the diffusion region of the second conductivity type disposed via a central portion having a width including the first and second horizontal lattices, which are the lattices of the book And third and fourth transistors of the second conductivity type, each of which is formed along each of the first and third vertical lattices, sharing the second transistor region, And between the second vertical lattice and the left side of the central part The first of the first transistor and the third has a central terminal area for arranging the gate wiring terminals have
A first gate electrode common to the first and second transistors, and a second central terminal disposed between the second vertical lattice and the third vertical lattice, occupying the right side of the central portion and arranging a terminal for gate wiring. The second transistor and the fourth transistor
And a second gate electrode common to the first and second transistors, and the intersections of the first to third vertical lattices and the first and second horizontal lattices included over the first and second central terminal regions. A semiconductor integrated circuit having at least six terminal arrangement candidate points for arranging the gate wiring terminals that can be arranged only in each of the first and second central terminal regions. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein each of said first and second central terminal regions has at least three terminal arrangement candidate points. 3. The method according to claim 2, wherein the first central terminal area has at least four candidate terminal arrangement points, and the second central terminal area has at least two candidate terminal arrangement points. The semiconductor integrated circuit device according to claim 1. 4. A plurality of CMOS basic cells are arranged and arranged, and position coordinates inside the CMOS basic cells are set based on horizontal horizontal grids and vertical vertical grids respectively set at a predetermined pitch. in the semiconductor integrated circuit device of the gate Toarei manner, the CMOS-type basic cell, at least the longitudinal grating 3
The first transistor region which is a source region or a drain region formed along the second vertical lattice at the center of the diffusion region of the first conductivity type including the main transistor and shares the left and right sides of the second vertical lattice, respectively. And first and second transistors of the first conductivity type formed along each of the first and right third vertical lattices, respectively; and two of the horizontal lattices in the vertical direction from the first transistor region. A source region or a drain region formed along the second vertical lattice of the diffusion region of the second conductivity type disposed via a central portion having a width including the first and second horizontal lattices, which are the lattices of the book And third and fourth transistors of the second conductivity type, each of which is formed along each of the first and third vertical lattices, sharing the second transistor region, And between the second vertical lattice and the left side of the central part A first central terminal region for arranging first and second and third gate wiring terminals on the second vertical lattice and the first transistor on the first vertical lattice; A first gate electrode common to a third transistor; a fourth gate on the second vertical grid, which is disposed between the second vertical grid and the third vertical grid and occupies the right side of the central portion. And a second central terminal region for arranging gate wiring terminals for arranging fifth and sixth gate wiring terminals on the third vertical lattice. The second transistor and the fourth transistor And a second gate electrode common to the first and second gate electrodes.
A first power supply is connected to the source of each of the transistors, and a second power supply is connected to the third and fourth transistors. The drains of the first and third transistors are connected to the second, A first wiring passing through the third gate wiring terminal, and a second drain passing through the fifth and sixth gate wiring terminals connecting the drains of the second and fourth transistors to each other. An input signal is connected to the second gate electrode via the fourth gate wiring terminal, and a third branch from the second wiring is connected to the first gate wiring terminal. A semiconductor integrated circuit device comprising a two-stage buffer circuit formed by connecting wiring.