JP3039474B2 - Asynchronous pulse signal retiming circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous pulse signal retiming circuit, and more particularly to a retiming circuit for outputting a pulse signal asynchronous with a clock signal as a pulse signal synchronized with the clock signal.

[0002]

2. Description of the Related Art A conventionally known retiming circuit for outputting a pulse signal asynchronous with a clock signal as a pulse signal synchronized with the clock signal is composed of two flip-flops and outputs a signal of the asynchronous pulse signal. Retiming of an asynchronous pulse signal is performed using a clock signal whose cycle is shorter than the width (Japanese Patent Application Laid-Open No. 2-42518).

FIG. 3 is a circuit diagram showing an example of the above-mentioned conventional asynchronous pulse signal retiming circuit. As shown in FIG. 3, this conventional asynchronous pulse retiming circuit comprises two cascade-connected flip-flops 21 and 22, and an inverter which inverts a clock signal from a terminal 12 and applies the inverted signal to a clock terminal of the flip-flop 21. 23, an asynchronous pulse signal is input to the terminal 11,
The flip-flop 22 outputs a retimed synchronization pulse signal to the output terminal 18 using a clock signal.

The flip-flops 21 and 22 are D-type flip-flops. An asynchronous pulse signal is input from a terminal 11 to a data input terminal D of the flip-flop 21, and an inverted clock signal from an inverter 23 is applied to a clock terminal. Is done. In addition, flip-flop 2
The Q output signal of the flip-flop 21 is applied to the second data input terminal D, and the clock signal input from the terminal 12 is applied to the clock terminal.

Next, the operation of the conventional asynchronous pulse signal retiming circuit having the above configuration will be described with reference to the timing charts of FIGS. FIGS. 4A and 5A show asynchronous pulse signals, which are asynchronous with the clock signals shown in FIGS. 4B and 5B. 4C and FIG. 5C show the inverter 23.
And the clock signal shown in FIG. 4B and FIG. 5B have an opposite phase relationship. FIG. 4 (d) and FIG.
FIG. 4D shows the Q output signal of the flip-flop 21, FIG.
5E and 5E show the Q output signal of the flip-flop 22. FIG.

First, a flip-flop 21 is supplied from a terminal 11.
The asynchronous pulse signal applied to the data input terminal D of
As shown in FIG. 4A, when the logic value changes from “0” to “1” at time T1, the inverter 23 applied to the clock terminal of the flip-flop 21
The output signal of the flip-flop 21 at time T2, which rises first after time T1, as shown in FIG.
Holds the logical value "1", and the Q output signal of the flip-flop 21 becomes the logical value "1" at time T2 as shown in FIG.

Further, the flip-flop 22 is
The clock signal applied to the data input terminal D of FIG.
As shown in (b), the logic value "1" is held in the flip-flop 22 at the first rising time T3 after the time T2, and the Q output signal of the flip-flop 22 at the time T3 as shown in FIG. Becomes the logical value “1”.

As described above, the asynchronous pulse signal is
As shown in (a), when the logic value changes from “1” to “0” at time T4 after time T3, the clock signal applied from the terminal 12 to the data input terminal D of the flip-flop 22 changes as shown in FIG. As shown in FIG. 4 (b), at time T3
At time T5 when the signal first rises later, the logic value "0" is held in the flip-flop 22. At time T5, the Q output signal of the flip-flop 22 becomes logic value "0" at time T5.

As described above, according to this embodiment, the asynchronous pulse signal input to the terminal 11 is converted into a synchronized pulse signal synchronized in phase with the clock signal input to the terminal 12, and the flip-flop 22 18 is output.

[0010]

However, in the above-mentioned conventional asynchronous pulse signal retiming circuit, in order for the retiming operation to be performed stably, the asynchronous pulse signal is changed from a logical value "0" to a logical value "1". After the change, the condition is that the logic value "1" is held until time T2, that is, the clock signal is sufficiently fast with respect to the signal widths T1 to T4 of the asynchronous pulse signal. Synchronization pulse signal cannot be output.

The operation of the conventional asynchronous pulse signal retiming circuit when the cycle of the clock signal is longer than the signal widths T1 to T4 of the asynchronous pulse signal will be described with reference to the timing chart of FIG. FIG.
As shown in (a), the asynchronous pulse signal has the logical value “1”.
During the period (T1 to T4) in which
Does not rise, and as shown in FIG.
When the rising of the output signal of the inverter 23 occurs at the time T2 after the time T4, the flip-flop 21 holds the logical value “0” of the input asynchronous pulse signal at the time T2.
The output signal remains at the logical value "0", and the Q output signal of the flip-flop 22 holding the Q output signal of the flip-flop 21 also remains at the logical value "0" as shown in FIG. It is. That is, in the above case, the conventional asynchronous pulse signal retiming circuit cannot output the synchronization pulse signal normally and malfunctions.

The present invention has been made in view of the above points,
It is an object of the present invention to provide an asynchronous pulse signal retiming circuit that can output a synchronized pulse signal even when using a clock signal having a longer cycle than the asynchronous pulse signal width.

[0013]

According to the present invention, there is provided a pulse signal in which a clock signal and an asynchronous pulse signal asynchronous to the clock signal are received as input signals, and the asynchronous pulse signal is synchronized with the clock signal. An asynchronous pulse signal retiming circuit that outputs a detection signal when detecting that the asynchronous pulse signal has changed from the first logical value to the second logical value, and outputs a detection signal while maintaining the detection state; Longer than signal width of asynchronous pulse signal
Holding means for holding and outputting an output signal of a detection circuit when a clock signal having a long cycle changes from a third logic value to a fourth logic value, and outputting a signal of a predetermined logic value when holding the detection signal A logic circuit that outputs a synchronized pulse signal by passing a clock signal only during a period in which a signal of a predetermined logic value is output from the holding unit, and cancels the detection state of the detection circuit to return to the initial state. It has the structure which has.

[0014]

In the present invention, it is detected that the asynchronous pulse signal has changed from the first logical value to the second logical value, and the detection state is changed from the third logical value in one cycle of the clock signal to the fourth logical value. Since the clock signal is detected during the period of one cycle of the clock signal and is output from the logic circuit when the change to the logical value is detected, the edge at which the asynchronous pulse signal changes from the first logical value to the second logical value A signal indicating information can be output from the logic circuit in synchronization with the clock signal.

The output signal of the above logic circuit is output within one cycle of the clock signal, and a clock signal having a cycle longer than the signal width of the asynchronous pulse signal can be used.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of an asynchronous pulse signal retiming circuit according to the present invention. As shown in FIG. 1, the asynchronous pulse retiming circuit according to this embodiment inverts a clock signal from two cascade-connected flip-flops 13 and 14 and a terminal 12 and applies the inverted signal to the clock terminal of the flip-flop 14. Inverter 15, an AND circuit 16, and an output terminal 18
And an inverter 17 for inverting the output pulse signal of the flip-flop 13 and applying the inverted pulse signal to the clear terminal of the flip-flop 13. The asynchronous pulse signal is input to the terminal 11, and the synchronous signal retimed by the flip-flop 14 using the clock signal. And outputs the signal to the output terminal 18 through the AND circuit 16.

The flip-flop 13 is a D-type flip-flop having a reset terminal. An asynchronous pulse signal is input from a terminal 11 to a clock terminal, and a voltage of logical value "1" is fixedly applied to a data input terminal D. Then, the synchronization pulse inversion signal output from the inverter 17 is applied to the reset terminal. The flip-flop 14
Is a D-type flip-flop. The Q output signal of the flip-flop 13 is applied to the data input terminal D, and the output signal of the inverter 15 for inverting the clock signal input from the terminal 12 is applied to the clock terminal. The AND circuit 16 calculates the logical product of the clock signal from the terminal 12 and the output signal of the flip-flop 14, and outputs the output signal to the inverter 17 and the output terminal 18, respectively.

Next, the operation of the asynchronous pulse signal retiming circuit having the configuration of FIG. 1 will be described with reference to the timing chart of FIG. FIG. 2A shows an asynchronous pulse signal, which is asynchronous with the clock signal shown in FIG. 2B. FIG. 2C shows an output signal of the inverter 15, which has an opposite phase relationship to the clock signal shown in FIG. 2B. 2D shows the Q output signal of the flip-flop 13, FIG. 2E shows the Q output signal of the flip-flop 14,
FIG. 2F shows an output signal of the AND circuit 16, and FIG. 2G shows an output signal of the inverter 17.

First, a flip-flop 13 is supplied from a terminal 11.
The asynchronous pulse signal applied to the clock input terminal of
As shown in FIG. 2A, when the logical value changes from “0” to “1” at time T11, the logical value “1” always applied to the data input terminal D is held. The Q output signal of the flip-flop 13 is shown in FIG.
, The logical value becomes “1” from time T11. The output state of the flip-flop 13 is held until a logical value “0” is input to the reset terminal. The flip-flop 14 holds the Q output signal of the flip-flop 13 input to the data input terminal D when the output signal of the inverter 15 input to the clock terminal rises.

Here, the signal width T11 of the asynchronous pulse signal
To T12 are smaller than the periods of the clock signal and its inverted signal shown in FIGS. 2B and 2C, and the logical value of the clock signal and its inverted signal at time T13 after the falling time T12 of the asynchronous pulse signal has elapsed. Is inverted (changed), the flip-flop 14 holds the logical value “1” of the Q output signal of the flip-flop 13 due to the rise of the inverted signal of the clock signal output from the inverter 15 at time T13. 14 Q
The output signal changes from the logical value “0” to the logical value “1” at time T13 as shown in FIG.

Since the AND circuit 16 takes the logical product of the Q output signal of the flip-flop 14 and the clock signal from the terminal 12, as shown in FIG. In response to the clock signal changing from the logical value “0” to the logical value “1” at time T14, the logical value changes from the logical value “0” to the logical value “1” at time T14. The output signal of the AND circuit 16 is
Therefore, the output signal of the inverter 17 changes from the logical value “1” to the logical value “0” at time T14 as shown in FIG. 2 (g). Since the logic value changes to “0” at the time T14, the flip-flop 13 is reset (the detection state is released), and the Q output signal of the flip-flop 13 becomes the logic at the time T14 as shown in FIG. The state is returned to the initial state of the value “0”.

As described above, according to this embodiment, even if a clock signal having a longer cycle than the signal width of the asynchronous pulse signal input to the terminal 11 is used, the asynchronous pulse signal which rises at the time T11 is converted to the clock signal. , And can be output from the AND circuit 16 to the terminal 18 as a synchronization pulse signal which rises at time T14.

It should be noted that the present invention is not limited to the above-described embodiment. For example, instead of the AND circuit 16, N
An AND circuit may be provided, an inverter may be provided between the NAND circuit and the output terminal 18, and the logical relationship with the embodiment may be inverted.

[0025]

As described above, according to the present invention,
Even if a clock signal having a longer cycle than the signal width of the asynchronous pulse signal is used, the synchronized pulse signal can be output normally, and a clock signal shorter than the signal width of the asynchronous pulse signal is newly used for retiming. Can be eliminated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a circuit diagram of a conventional example.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

FIG. 5 is a timing chart for explaining a problem in FIG. 3;

[Explanation of symbols]

 Reference Signs List 11 Asynchronous pulse signal input terminal 12 Clock signal input terminal 13 D-type flip-flop with reset terminal 14 D-type flip-flop 15, 17 inverter 16 AND circuit

Claims (1)

(57) [Claims] 1. An asynchronous pulse signal retiming circuit for receiving a clock signal and an asynchronous pulse signal asynchronous to the clock signal as input signals, and outputting the asynchronous pulse signal as a pulse signal synchronized with the clock signal. A detection circuit that outputs a detection signal while maintaining the detection state when detecting that the asynchronous pulse signal has changed from the first logical value to the second logical value; and a period longer than the signal width of the asynchronous pulse signal. wherein when the clock signal changes to a fourth logic value from the third logic value, and outputs the held output signal of said detecting circuit having,
Holding means for outputting a signal of a predetermined logic value when the detection signal is held; and only as long as the signal of the predetermined logic value is being output from the holding means, the clock signal is passed and the synchronized pulse signal is output. A logic circuit for outputting and returning a detection state of the detection circuit to an initial state.