JP3559749B2 - Pulse generation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pulse generation circuit that is useful when applied to, for example, an address transition detection circuit (ATD; Address Trasion Detector) of a semiconductor memory.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor memory such as an SRAM, an ATD circuit is used to detect an address transition and control timing of reading memory cell data. FIG. 6 shows a general configuration of the ATD circuit. The ATD circuit includes a delay circuit 1 for delaying an input signal IN, a NAND gate 2 and a NOR gate 3 for taking the logic of the delay output and the input signal, and a signal obtained by inverting the NAND gate 2 by an inverter 4 and an output of the NOR gate 3. It is constituted by a NOR gate 5 which takes logic. The delay circuit 1 delays both rising and falling edges of the input signal.
[0003]
FIG. 7 shows operation waveforms of the ATD circuit. The delay time of the delay circuit 1 is τ, and in the case of FIG. 7, the “L” period T1 and the “H” period T2 of the input signal IN are larger than the delay time τ. At this time, a signal obtained by delaying the input signal IN is obtained at the output node N1 of the delay circuit 1. By performing a positive logical product and a negative logical product between the delay output and the input signal IN by the NAND gate 2 and the NOR gate 3, respectively, signals as shown in FIG. 7 are obtained at the nodes N2 and N3. Further, by taking the negative logical product of these signals by the NOR gate 5, address transition detection signals (ATD pulses) P1 and P2 synchronized with the falling edge and the rising edge of the input signal IN are obtained as the output signal OUT. .
[0004]
The pulse width of each of the ATD pulses P1 and P2 is equal to the delay time τ of the delay circuit 1. For example, by setting the delay time τ = 5 ns, a pulse signal having a width of 5 ns can be obtained.
[0005]
[Problems to be solved by the invention]
However, the ATD circuit shown in FIG. 6 has a disadvantage that it can operate normally only when the pulse width of the input signal is larger than the delay time τ. For example, FIG. 8 shows an operation when an input signal IN whose pulse width T is smaller than the delay time τ is input. At this time, since the delay circuit 1 cannot respond to the pulse width of the input signal, a pulse signal output is obtained in which the change of the input signal IN is passed through as the output signal OUT as shown. That is, the transition of the input signal IN from “L” to “H” is ignored, and an ATD pulse requiring a constant pulse width cannot be obtained from this transition.
[0006]
A negative pulse having a narrow pulse width T as shown in FIG. 8 is a noise component for the address signal. If such a high frequency noise component exists, a normal ATD pulse cannot be generated. Such high-frequency noise components can be removed by using a low-pass filter LPF. However, if the LPF is inserted directly before the conventional ATD circuit, the "L" level width of the address signal actually input to the ATD circuit becomes small. As a result, if the "L" level period of the address signal is shorter than the delay time τ of the delay circuit, a normal ATD pulse cannot be generated as described above.
[0007]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a pulse generation circuit capable of performing level transition detection with a high response to an input signal having a short pulse width.
[0008]
[Means for Solving the Problems]
The pulse generation circuit according to the present invention includes a first latch circuit that is set by detecting a first transition point of an input signal from a first level to a second level, and a first latch circuit that is set from a second level of the input signal to a first level. A second latch circuit that is set by detecting a second transition point to a level, and a logical product of an output of the first latch circuit and the input signal, following the first transition point of the input signal; A first logic gate that outputs an output that changes in level at a third transition point from the second level to the first level, and a logical product of the output of the second latch circuit and the input signal, the first logic gate of the input signal A second logic gate outputting a level-changing output at a fourth transition point from the first level to the second level following the second transition point; and in synchronization with an edge of the output of the first logic gate. A first pulse generator for outputting a first pulse signal having a constant pulse width; A second edge detection circuit for outputting a second pulse signal having the same pulse width as the first pulse signal in synchronization with an edge of an output of the second logic gate; A first reset circuit for generating a reset signal for resetting the first latch circuit at a trailing edge of a first pulse signal obtained from the edge detection circuit, and a second reset signal obtained from the second edge detection circuit A second reset circuit for generating a reset signal for resetting the second latch circuit at a trailing edge of the pulse signal.
[0009]
According to the present invention, a pulse signal can be generated at a rising edge and a falling edge of the input signal in response to an input signal having a pulse width smaller than the pulse width of a pulse signal to be generated. . Therefore, it is effective when applied to an ATD circuit or the like of a semiconductor memory. In particular, even in an ATD circuit in which a low-pass filter with a pulse width change is provided at a signal input end to remove noise, it is possible to generate an ATD pulse having a required pulse width.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a pulse generation circuit according to an embodiment of the present invention. This pulse generation circuit is preferably used as an ATD circuit of a semiconductor memory, but is not limited to this. This pulse generation circuit includes a first pulse transition detection circuit 10 and a second pulse transition detection circuit 20. The first pulse transition detection circuit 10 detects a transition point of the input signal IN from the “H” level to the “L” level, and is constant at a subsequent transition point from the “L” level to the “H” level. This is a circuit for outputting a pulse signal P11 having a pulse width. The second pulse transition detection circuit 20 detects a transition point from the “L” level to the “H” level of the input signal, and sets a constant pulse at the subsequent transition point from the “H” level to the “L” level. This is a circuit for outputting a pulse signal P12 having a width.
[0011]
The first pulse transition detection circuit 1 is a latch circuit (RS flip-flop) 11 configured using NAND gates G11 and G12, which is set when the input signal IN transitions from “H” level to “L” level. Having. The NAND gates G11 and G12 are two-input NANDs, and one input terminal thereof is cross-connected to the other output terminal, and the other input terminals constitute a latch terminal 11 with a set terminal S and a reset terminal R. The output node of the NAND gate G11 of the latch circuit 11 is provided with the product of the positive logic between the signal obtained by inverting the signal by the inverter INV11 (that is, the set output which becomes “H” at the time of setting) and the input signal IN. A NAND gate G13 is provided.
[0012]
An output node N12 of the NAND gate G13 is provided with an edge detection circuit 13 which detects a falling edge of the signal of the output node N12 and outputs a pulse signal P11 having a constant pulse width from this edge. The edge detection circuit 13 includes an inverter INV12 and a delay circuit 12 that invert the signal of the node N12 and delay the signal by a delay time τ1, and a negative logic between the signal of the output node N13 of the delay circuit 12 and the signal of the node N12. It is constituted by a NOR gate G14 which takes a product.
[0013]
A pulse signal P11 having a pulse width of the delay time τ1 of the delay circuit 12 is generated at the output node N14 of the edge detection circuit 13. An output node N14 of the edge detection circuit 13 is provided with a reset circuit 15 for resetting the latch circuit 11. The reset circuit 15 is an edge detection circuit that detects a falling edge of the pulse signal P11, and includes an inverter INV13, a delay circuit 14, and a NAND gate G15. At the output node N15 of the reset circuit 15, a negative reset signal having a pulse width determined by the delay time τ2 of the delay circuit 14 is obtained, which enters the reset terminal R of the NAND gate G11 of the latch circuit 11.
[0014]
The second pulse transition detection circuit 20 is a latch circuit (RS flip-flop) configured by using NOR gates G21 and G22, which is set at a transition point of the input signal IN from “L” level to “H” level. 21. Each of the NOR gates G21 and G22 is a two-input NOR, one input terminal of which is cross-connected to the other output terminal, and the other input terminals constitute a latch terminal 21 having a set terminal S and a reset terminal R. At the output node of the NOR gate G22 of the latch circuit 21, the product of the negative logic between the signal obtained by inverting the signal by the inverter INV21 (that is, the set output which becomes "L" at the time of setting) and the input signal IN is obtained. A NOR gate G23 is provided.
[0015]
An output node N22 of the NOR gate G23 is provided with an edge detection circuit 23 which detects a rising edge of the signal of the output node N22 and outputs a pulse signal P12 having a constant pulse width from this edge. The edge detection circuit 23 includes an inverter INV22 for inverting the signal at the node N22 and a delay circuit 22 for the delay time τ1, and a negative logical product between the signal at the output node N23 of the delay circuit 22 and the signal inverted by the inverter INV22. , And a NOR gate G24. The delay time τ1 of the delay circuit 22 is the same as that of the delay circuit 12 of the first pulse generation circuit 1.
[0016]
A pulse signal P12 having a pulse width of the delay time τ1 of the delay circuit 22 is generated at the output node N24 of the edge detection circuit 23. An output node N24 of the edge detection circuit 23 is provided with a reset circuit 25 for resetting the latch circuit 21. The reset circuit 25 is an edge detection circuit that detects a falling edge of the pulse signal P12, and includes a delay circuit 24, an inverter INV23, and a NOR gate G25. At the output node N25 of the reset circuit 25, a positive reset signal having a pulse width determined by the delay time τ2 of the delay circuit 24 is obtained, which enters the reset terminal R of the NOR gate G22 of the latch circuit 21. The delay time τ2 of the delay circuit 24 is the same as that of the delay circuit 14 in the first pulse generation circuit 1.
[0017]
The pulse signal P11 output from the first pulse generation circuit 1 and the pulse signal P12 output from the second pulse generation circuit 2 are such that the “L” and “H” level periods of the input signal IN are shorter than the delay time τ1. If it is larger, it is generated at each level transition point of the input signal IN. These pulse signals P11 and P12 are output as output signals OUT by the OR gate G31.
[0018]
The first and second pulse transition detection circuits 10 and 20 can respond to pulse signals narrower than the pulse widths of the pulse signals P11 and P12 to be output, respectively. Specifically, the first pulse transition detection circuit 10 is capable of responding to a negative pulse having an “L” level width shorter than the delay time τ1, and the second pulse transition detection circuit 20 is shorter than the delay time τ1. It can respond to the "H" level positive pulse. This operation will be described below.
[0019]
FIG. 2A shows a response waveform of the first pulse transition detection circuit 10 to a negative pulse having an “L” level width T <τ1. At the falling edge of the input signal IN, the latch circuit 11 is set, and the node N11 becomes "H". By the logic of the NAND gate G13 for the signal of the node N11 and the input signal IN, a signal that falls at the rising edge of the input signal IN is obtained at the node N12. The edge detection circuit 13 generates a pulse signal P11 having a pulse width τ1 at the node N14 from the signal at the node N12 and the signal at the node N13 which is inverted and delayed by τ1. The reset circuit 14 outputs a reset signal RP11 composed of a negative pulse having a pulse width of τ2 at the falling edge of the pulse signal P11, whereby the latch circuit 11 is reset.
[0020]
FIG. 2B shows a response waveform of the second pulse transition detection circuit 20 to a positive pulse having an “H” level width T <τ1. At the rise of the input signal IN, the latch circuit 21 is set, and the node N21 becomes "L". By the logic of the NOR gate G23 for the signal of the node N21 and the input signal IN, a signal which rises at the falling edge of the input signal IN is obtained at the node N22. The edge detection circuit 23 generates a pulse signal P12 having a pulse width τ1 at the node N24 from the inverted signal of the signal at the node N22 and the signal at the node N23 delayed by τ1. The reset circuit 25 outputs a reset signal RP12 composed of a positive pulse having a pulse width of τ2 at the falling edge of the pulse signal P12, whereby the latch circuit 21 is reset.
[0021]
When the “H” level period and the “L” level period of the input signal IN are longer than the delay time τ1, the pulse generation circuit of FIG. 1 changes from “H” to “L” as in the conventional ATD circuit. A transition detection pulse signal can be output at each of the transition points and transition points from “L” to “H”. This is shown in FIG. As shown in the figure, the “L” level period T1 and the “H” level period T2 are longer than the delay time τ1. 2A and 2B will not be described. At the transition point t2 from the "L" level to the "H" level of the input signal, the latch circuit 11 is set at the transition point t1 from the "H" level to the "L" level before the first pulse transition. The pulse signal P11 is generated from the detection circuit 10. At the transition point t1, the latch circuit 21 is set at the previous transition point from “L” to “H” (not shown), and the second pulse transition detection circuit 20 generates the pulse signal P12. . These pulse signals P11 and P12 are directly output as an output signal OUT through the OR gate G31.
[0023]
As described above, the pulse generation circuit according to this embodiment can respond to an input signal having a narrow pulse width, and can generate a transition detection pulse signal having a constant pulse width at each level transition of the input signal. . However, when the pulse generating circuit of this embodiment is actually applied as an ATD circuit of a semiconductor memory, it is necessary not to respond to high-frequency noise having a small pulse width.
[0024]
FIG. 4 shows an ATD circuit of such an embodiment. The LPF 3 is inserted between the signal input terminals IN0 and IN1, and the pulse generation circuit connected to the input terminal IN1 is the same as that in FIG. However, the LPF 3 actually has a waveform shaping circuit at its output stage.
[0025]
FIG. 5 shows operation waveforms of the ATD circuit in this embodiment. The input signal IN0 is an address signal, and it is assumed that both the "L" level period T1 and the "H" level period T2 are longer than the delay time τ1 required for ATD pulse generation. The high-frequency pulse noise superimposed on the input signal IN0 as shown in the figure is removed by the LPF 3 to become the input signal IN1 to the pulse generation circuit. At this time, the input signal IN1 has the “L” level period T1 ′ shorter than the original “L” level period T1 and the “H” level period T2 ′ is larger than the original “H” level period T2 due to the LPF processing. Become.
[0026]
Here, the “H” level period T2 ′ corresponds to a period between adjacent transition points of the input signal IN1 for which a level transition is to be detected, that is, a time period from t11 to t13 or a time period from t12 to t14. The time constant of the LPF 3 is set such that the "H" level period T2 'is equal to or greater than the sum of the pulse width τ1 of the output pulse signal and the pulse width τ2 of the reset signals RP11 and RP12. .
[0027]
In response to such an input signal IN1, as described above, the first pulse transition detection circuit 10 outputs a pulse signal P11 of time τ1 at the rising edges t12 and t14, and the second pulse transition detection circuit 20 outputs a pulse signal P12 at time τ1 at falling edges t11 and t13. At this time, even if the “L” level period T1 ′ is shorter than the delay time τ1 as shown in the figure, the output signal OUT is a signal obtained by combining the two pulse signals P11 and P12, which is an ATD pulse.
[0028]
That is, according to this embodiment, even if the "L" level period of the address signal is reduced by the LPF processing, the rising edge from "L" to "H" is not ignored as in the related art. An ATD pulse can be generated by securing the time τ1 from this edge. As shown in the figure, when the “L” level period T1 ′ becomes smaller, a combined ATD pulse is obtained with a pulse width of τ1 or more, but when the “L” level period T1 ′ is τ1 or more, If there are, as in the case described above with reference to FIG. 3, independent pulse signals are generated at the falling edge and the rising edge of the input signal IN1.
[0029]
【The invention's effect】
As described above, according to the present invention, it is possible to detect a level transition and generate a pulse signal having a predetermined pulse width or more regardless of the pulse width of an input signal. And a useful pulse generating circuit can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a pulse generation circuit according to an embodiment of the present invention.
FIG. 2A is a diagram showing a response waveform to a negative pulse signal having a small pulse width by a first pulse transition detection circuit of the pulse generation circuit.
FIG. 2B is a diagram showing a response waveform to a positive pulse signal having a small pulse width by a second pulse transition detection circuit of the pulse generation circuit.
FIG. 3 shows a response waveform of the pulse generation circuit to an input signal having a large pulse width.
FIG. 4 is a diagram showing a configuration of an ATD circuit according to another embodiment of the present invention.
FIG. 5 is a diagram showing a response waveform of the ATD circuit.
FIG. 6 is a diagram showing a configuration of a conventional ATD circuit.
FIG. 7 is a diagram showing a normal operation waveform of the ATD circuit.
FIG. 8 is a diagram showing operation waveforms for explaining a response limit of the ATD circuit.
[Explanation of symbols]
10 first pulse transition detection circuit, 11 latch circuit, G13 NAND gate, 12 delay circuit, 13 edge detection circuit, 14 delay circuit, 15 reset circuit, 20 second pulse transition detection circuit , 21 ... Latch circuit, G23 ... NOR gate, 22 ... Delay circuit, 23 ... Edge detection circuit, 24 ... Delay circuit, 25 ... Reset circuit.

Claims (7)

A first latch circuit that is set by detecting a first transition point of the input signal from the first level to the second level;
A second latch circuit that is set by detecting a second transition point of the input signal from a second level to a first level;
A logical product of the output of the first latch circuit and the input signal to output an output that changes in level at a third transition point from a second level following the first transition point of the input signal to a first level; One logic gate,
An output that changes in level at a fourth transition point from a first level following the second transition point of the input signal to a second level is obtained by ANDing the output of the second latch circuit and the input signal. A second logic gate to output,
A first edge detection circuit that outputs a first pulse signal having a constant pulse width in synchronization with an edge of an output of the first logic gate;
A second edge detection circuit that outputs a second pulse signal having the same pulse width as the first pulse signal in synchronization with an edge of an output of the second logic gate;
A first reset circuit for generating a reset signal for resetting the first latch circuit at a trailing edge of a first pulse signal obtained from the first edge detection circuit;
A second reset circuit for generating a reset signal for resetting the second latch circuit at a trailing edge of a second pulse signal obtained from the second edge detection circuit. . The first latch circuit is an RS flip-flop configured using a NAND gate and set at a falling edge of the input signal;
2. The pulse generation circuit according to claim 1, wherein the second latch circuit is an RS flip-flop configured using a NOR gate, which is set at a rising edge of the input signal. The first logic gate is a first NAND gate that takes a positive AND of an “H” level set output of the first latch circuit and the input signal,
3. The pulse generator according to claim 2, wherein the second logic gate is a first NOR gate that performs a NAND operation of an "L" set output of the second latch circuit and the input signal. circuit. The first edge detection circuit includes a first inverter for inverting the output of the first NAND gate, a first delay circuit for delaying the output of the first inverter by time τ1, and the first delay. A second NOR gate to which an output of a circuit and an output of the first NAND gate are input, and which generates the first pulse signal having a pulse width of time τ;
The second edge detection circuit includes a second inverter for inverting the output of the first NOR gate, a second delay circuit for delaying the output of the first NOR gate by a time τ1, and a second delay circuit for inverting the output of the first NOR gate. A third NOR gate to which an output of the delay circuit and an output of the second inverter are inputted, and which outputs the second pulse signal having a pulse width of time τ1. The pulse generating circuit according to claim 3, wherein The first reset circuit includes a third edge detection circuit that detects a trailing edge of the first pulse signal and generates the first reset signal,
5. The device according to claim 4, wherein the second reset circuit comprises a fourth edge detection circuit that detects a trailing edge of the second pulse signal and generates the second reset signal. Pulse generation circuit. The pulse generation circuit according to claim 1, further comprising a low-pass filter for removing the high frequency noise from the input signal and supplying the input signal to the first and second latch circuits. 2. The pulse generation circuit according to claim 1, wherein the pulse generation circuit is an address transition detection circuit of a semiconductor memory.

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