JP3053466B2 - Encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding apparatus for inputting an analog signal and performing PCM coding or DPCM coding.

More specifically, the present invention relates to an encoding device suitable for encoding an output signal from, for example, an optical sensor to generate input data for a computer.

[0003]

2. Description of the Related Art Conventionally, when an output signal from an optical sensor is encoded, it is encoded using an analog / digital converter (hereinafter, referred to as an ADC) corresponding to the accuracy required for the system.

[0004]

However, the above-mentioned prior art has the following disadvantages.

[0005] 1) For an ADC of high speed (about 20 Mbps), a low-cost ADC of up to 8 bits is available, but an ADC having an accuracy of 10 bits or more is very expensive.

2) When an optical sensor output signal is processed by a computer and output to a monitor television or a printer, a bit loss of 3 to 4 bits occurs in the processing process, and when the precision of the sensor output signal is 8 bits, the image quality is reduced. Degradation occurs.

For the above reasons, the encoding accuracy of the optical sensor output signal is desirably 12 bits or more, and it is necessary to realize it at low cost.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an encoding apparatus which enables highly accurate encoded output despite a simple configuration.

[0009]

According to the present invention, there is provided a subtraction means for inputting a sampled analog signal to a first input terminal, and an A / D converter for converting an output of the subtraction means into an m-bit digital signal. Means, addition means for inputting the output of the A / D conversion means to a first input terminal, n-bit (n> m) storage means for inputting the output of the addition means, and n bits of the storage means Means for supplying an output to a second input terminal of the addition means, and D / A conversion means for converting an n-bit output of the storage means into an analog signal and supplying the analog signal to a second input terminal of the subtraction means. Equipped, m-bit PCM code, n
Bit PCM code, (m + 1) bit DPCM code or (m-1) bit PCM code, n bit PM code
A CM code and an m-bit DPCM code are generated.

[0010]

According to the present invention, by using the differential encoding method, an output with n-bit (for example, 12-bit) precision can be obtained while using A / D conversion means for m-bit (for example, 8-bit).

[0011]

Embodiments of the present invention will be described below in detail.

Embodiment 1 FIG. 1 shows an embodiment of the present invention. In this embodiment, CC
A case where the output of the D line sensor 2 is encoded will be described.

In this embodiment, there are two modes, a conventional mode and a high gradation mode.
It has two modes, and their characteristics are shown in FIG.

In the CCD line sensor 2, the sensor 2
The output charge of A is FDA (Floating Diffusion Amplifie).
r) Converted to voltage at 2B. Thereafter, the signal is input to a subtractor 6 via a sample-and-hold (S / H) circuit 4, and is further converted to a digital signal by an A / D converter (hereinafter referred to as ADC) 10 via an absolute value circuit 8. . The +/− sign obtained by the absolute value circuit 8 is
After adding a sign, the data is stored in the 12-bit memory 16 shown in FIG.

The output of the memory 16 is sent to a D / A converter (hereinafter, referred to as DAC) 18 and an adder 14. The DAC 18 converts a 12-bit input into an analog signal and applies the analog signal to the subtractor 6.

Next, the operation of this embodiment will be described.

In the conventional mode, the data is output from the terminal 1 in 8-bit precision and the output format is 8-bit PCM. At this time, the system controller 20 holds the memory 16 in the reset state, and the output of the DAC 18 becomes zero.

The conversion reference voltage V _ref = V of the ADC 10
_Let it be _dr . This _Vdr indicates the dynamic range of the code as shown in FIG. In this conventional mode, the output signal of the image sensor 2A is obtained with 8-bit accuracy.

In the high gradation mode, the precision is 12 bits, and the output format is 12-bit PCM or 9-bit DPCM.
Output from terminals 3 and 2, respectively. At this time, the system control unit 20 encodes the first pixel in two cycles.

First, the first pixel signal is sampled and held, A / D conversion is performed with _Vref = _Vdr , and the upper 4 bits of the output are input to the upper 8 to 11 of the memory 16, and the next cycle is performed. Then, V _ref = V _dr / 16 is input to the lower 0 to 7 of the memory 16 (see FIG. 4).

Next, the second pixel signal of the sensor 2A is converted to S / H
The difference is obtained from the previous pixel by the circuit 4, and the difference is accumulated in the memory 16. This will be described with reference to FIG.

When the signal V of the pixel (i) is held by the S / H circuit 4, the output of the memory 16 becomes the pixel (i-
The signal Vi _-1 of 1) is stored. The output of the subtractor 6 is V _i −V _i−1 = ΔV _i , the absolute value is obtained, and the ADC
It is digitized at 10 and accumulated in the memory 16. Thus, a signal of ΔV _i is obtained at the output terminal 2 and a signal of V _i is obtained at the output terminal 3 in 9 bits and 12 bits, respectively.

The case of the line sensor has been described above. However, the case of the area sensor can be similarly applied.

Although the case where the precision is 8 or 12 bits has been described, the present invention can be easily extended to combinations of other values.

Embodiment 2 FIG. 5 shows a second embodiment of the present invention. In this embodiment,
An 8-bit ADC having both polarities is used as the ADC 10 '.

FIG. 6 shows points different from the first embodiment.
In this case, the DPCM code in the high gradation mode has 8 bits, and there is an advantage that the conventional computer parallel IF can be used as it is.

Effects of the Embodiment As described above, when reading and coding the optical sensor, it is possible to perform 12-bit precision coding using an 8-bit ADC. Moreover, in terms of cost, a 12-bit AD
The cost was significantly lower than using C.

If a DPCM signal is used, a parallel interface (SCSI
Etc.) can be used as it is. further,
Since conventional data can be easily obtained, compatibility with the system is excellent.

[0029]

As described above, according to the present invention, by using the differential encoding method, an output with n-bit precision (n> m) can be obtained while using m-bit A / D conversion means. A high-performance coding device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation mode in the first embodiment.

FIG. 3 is a waveform chart showing the operation of FIG.

FIG. 4 is a configuration diagram of a memory 16 shown in FIG. 1;

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing an operation mode in the second embodiment.

[Explanation of symbols]

 2 CCD line sensor 4 Sample / hold circuit 6 Subtractor 8 Absolute value circuit 10 A / D converter 12 Multiplier 14 Adder 16 Memory 18 D / A converter 20 System control unit 22 Reference voltage generation circuit 24 CCD driver

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 3/04 H03M 1/12 H03M 1/14 H03M 1/20 H03M 7/36

Claims (4)

(57) [Claims] 1. A subtractor for inputting a sampled analog signal to a first input terminal, an A / D converter for converting an output of the subtractor into an m-bit digital signal, and the A / D conversion. Addition means for inputting the output of the means to a first input terminal; n-bit (n> m) storage means for inputting the output of the addition means; and n-bit output of the storage means for the second output of the addition means. And a D / A conversion means for converting an n-bit output of the storage means into an analog signal and supplying the analog signal to a second input end of the subtraction means. n-bit PCM code, (m + 1) -bit DPCM code or (m-
1) An encoding device which generates a PCM code of bits, a PCM code of n bits, and a DPCM code of m bits. 2. An encoding apparatus according to claim 1, wherein an output of said storage means is set to zero to obtain an m-bit PCM code. 3. The method according to claim 1, wherein when performing DPCM encoding, the first pixel signal is first quantized by multiplying a reference voltage of the A / D conversion means by 2 ^(nm) , and then specified. An encoding device for performing quantization back to a reference voltage. 4. The A / D conversion means according to claim 1, wherein said A / D conversion means is of a bipolar type, and is a (m-1) -bit PCM.
A coding apparatus for generating a code, an n-bit PCM code, and an m-bit DPCM code.