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JP3073145B2 - Electric field treatment method for optical element - Google Patents
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JP3073145B2 - Electric field treatment method for optical element - Google Patents

Electric field treatment method for optical element

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Publication number
JP3073145B2
JP3073145B2 JP07136729A JP13672995A JP3073145B2 JP 3073145 B2 JP3073145 B2 JP 3073145B2 JP 07136729 A JP07136729 A JP 07136729A JP 13672995 A JP13672995 A JP 13672995A JP 3073145 B2 JP3073145 B2 JP 3073145B2
Authority
JP
Japan
Prior art keywords
voltage
optical element
electric field
insulating film
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07136729A
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Japanese (ja)
Other versions
JPH08327992A (en
Inventor
政美 城戸
光浩 繁田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Priority to JP07136729A priority Critical patent/JP3073145B2/en
Publication of JPH08327992A publication Critical patent/JPH08327992A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、液晶光学素子、ACタ
イプのプラズマディスプレイ、発光素子、調光素子等の
光学素子における絶縁膜の耐電圧性の向上のために施さ
れる電界処理方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric field processing method for improving the withstand voltage of an insulating film in an optical element such as a liquid crystal optical element, an AC type plasma display, a light emitting element, and a light adjusting element. .

【0002】[0002]

【従来の技術】液晶素子のように電界を印加することに
よって、透過光、反射光又は発光量等を調整する光学素
子においては、該素子の電極表面に絶縁層を必要として
いるものが存在する。
2. Description of the Related Art Some optical elements, such as liquid crystal elements, which adjust transmitted light, reflected light or light emission amount by applying an electric field, require an insulating layer on an electrode surface of the element. .

【0003】これらの絶縁膜層は、例えば、MgO,SiO2,T
iO2,Al2O3 などの薄膜をスパッタ等の方法で形成された
り、MgO,SiO2,TiO2,Al2O3 単体又はそれらの混合物を加
熱、薬品処理等で作成した化合物溶液を塗布する等の方
法で形成されたりする。
These insulating film layers are made of, for example, MgO, SiO 2 , T
A thin film of iO 2 , Al 2 O 3 or the like is formed by a method such as sputtering, or a compound solution prepared by heating MgO, SiO 2 , TiO 2 , Al 2 O 3 alone or a mixture thereof, or by chemical treatment, etc. It is formed by such a method.

【0004】ところが、現状の多くの素子に用いられて
いるガラス基板の表面にはミクロン単位、サブミクロン
単位の微小な突起が存在する。これら突起物はガラス基
板そのものの作成時に発生したもの、ガラス基板上に形
成される電極に存在するものなど、その由来は多様であ
る。これらの突起物はそれの上に形成される絶縁膜上に
も突起を形成し、絶縁性を低下させて耐電圧性を劣化さ
せる。
However, microscopic projections on the order of microns or submicrons are present on the surface of glass substrates used in many current devices. These protrusions have various origins, such as those generated during the production of the glass substrate itself and those present on the electrodes formed on the glass substrate. These protrusions also form protrusions on the insulating film formed thereon, thereby deteriorating the insulation and deteriorating the withstand voltage.

【0005】すなわち電極間において、これらの突起部
分には周辺に比べ高い電圧が印加されることになって、
局部的な放電現象が置き、その部分に絶縁破壊が進行す
る。そして電圧が印加され続けることにより、大きな絶
縁破壊が発生する。当然のことであるが、この傾向は電
極間の距離が短いほど、より顕著になる。
In other words, a higher voltage is applied to these projections between the electrodes than to the surroundings.
A local discharge phenomenon occurs, and dielectric breakdown proceeds in that portion. When the voltage is continuously applied, a large dielectric breakdown occurs. As a matter of course, this tendency becomes more remarkable as the distance between the electrodes becomes shorter.

【0006】現在、この原因による絶縁破壊を防ぐ方法
としては、絶縁層を十分に厚く形成する、ガラス基板や
電極等、突起物が存在すると思われる素子基板全てを研
磨処理する等の方法が取られている。
At present, methods for preventing dielectric breakdown due to this cause include a method of forming an insulating layer sufficiently thick and a method of polishing all element substrates on which projections are considered to exist, such as glass substrates and electrodes. Have been.

【0007】[0007]

【発明が解決しようとする課題】しかし、絶縁膜を厚く
形成することは、例えば液晶層、発光ガス層などに印加
される実効電圧を低下させるために、各種素子に対する
表示品位や発光量の低下、スイッチングスピードの減
少、さらには製造コストの増加など多くの欠点を持って
いる。また、素子基板の研磨方法は作業そのものの困難
さに加え、製造プロセス、コストの増加を招き、決して
良い方法とは言えない。
However, the formation of a thick insulating film requires a reduction in display quality and light emission amount for various devices, for example, in order to reduce an effective voltage applied to a liquid crystal layer, a luminescent gas layer, and the like. However, there are many disadvantages such as a decrease in switching speed and an increase in manufacturing cost. In addition, the method of polishing an element substrate adds to the difficulty of the operation itself, increases the manufacturing process and the cost, and is not a good method.

【0008】本発明の目的は、光学素子の絶縁膜の耐電
圧性を向上させる光学素子の電界処理方法を提供するこ
とにある。
An object of the present invention is to provide a method for treating an electric field of an optical element, which improves the withstand voltage of an insulating film of the optical element.

【0009】[0009]

【課題を解決するための手段】本発明は、電極と該電極
を被膜する絶縁膜とが形成された透明基板を用いた光学
素子に対し、前記電極にパルス電圧を印加して、前記絶
縁膜上の微小突起を破壊する光学素子の電界処理方法で
ある。
According to the present invention, a pulse voltage is applied to an electrode on an optical element using a transparent substrate on which an electrode and an insulating film covering the electrode are formed. This is an electric field processing method for an optical element that destroys the upper minute projection.

【0010】このパルス電圧は、光学素子の駆動電圧の
0.1〜1.2倍を印加電圧とし、1μsec〜1se
cの電圧印加時間と該電圧印加時間以上の休止時間との
繰り返しである電圧が好ましい。
The pulse voltage is applied at a voltage of 0.1 to 1.2 times the drive voltage of the optical element, and is applied for 1 μsec to 1 sec.
A voltage which is a repetition of a voltage application time of c and a pause time longer than the voltage application time is preferable.

【0011】さらにパルス電圧は、光学素子の駆動電圧
の0.1〜1.2倍の印加電圧内で、より低電圧から高
電圧へと段階的に又は時間を追って変化するようにして
もよい。
Further, the pulse voltage may be changed from a lower voltage to a higher voltage stepwise or with time within an applied voltage of 0.1 to 1.2 times the drive voltage of the optical element. .

【0012】[0012]

【作用】素子電極間における絶縁破壊は、従来技術でも
述べたように、突起部分に周辺に比べ高い電圧が印加さ
れる為に局部的な放電現象がおき、突起部分の絶縁破壊
が進行する。そこで本発明において、電極に印加電圧の
時間幅とタイミングを調節したパルス電圧を印加すると
いう電界処理を行えば突起部分のみが破壊された状態を
実現でき、突起部分の無い絶縁膜層を持った素子を作り
だすことができる。これにより、以後に印加される電界
に対して電界処理以前よりも耐電圧性が向上した光学素
子を実現することができる。
In the dielectric breakdown between the device electrodes, as described in the related art, since a higher voltage is applied to the protruding portion than in the periphery, a local discharge phenomenon occurs, and the dielectric breakdown of the protruding portion proceeds. Therefore, in the present invention, by performing an electric field treatment of applying a pulse voltage with the time width and timing of the applied voltage adjusted to the electrode, it is possible to realize a state in which only the protruding portion is broken, and to have an insulating film layer without the protruding portion. An element can be created. This makes it possible to realize an optical element in which the withstand voltage of a subsequently applied electric field is higher than that before the electric field treatment.

【0013】ここでいう印加電圧の時間幅とタイミング
を調節したパルス電圧は、実際に電界処理を行おうとす
る光学素子の種類、駆動電圧、電極形状及びそれらの電
極間距離などにより種々の条件が考えられる。光学素子
の駆動電圧の0.1〜1.2倍を印加電圧とし、1μs
ec〜1secの電圧印加時間と該電圧印加時間以上の
休止時間との繰り返しからなるパルス電圧や、さらに光
学素子の駆動電圧の0.1〜1.2倍の印加電圧内で、
より低電圧から高電圧へと段階的に又は時間を追って変
化する1μsec〜1secの電圧印加時間と該電圧印
加時間以上の休止時間との繰り返しからなるパルス電圧
を印加することで、光学素子の耐電圧性が向上すること
が確認できている。
The pulse voltage obtained by adjusting the time width and timing of the applied voltage may vary depending on the type of optical element to be actually subjected to electric field processing, the driving voltage, the shape of the electrodes, the distance between the electrodes, and the like. Conceivable. The applied voltage is 0.1 to 1.2 times the drive voltage of the optical element, and 1 μs
Within a pulse voltage consisting of a repetition of a voltage application time of ec to 1 sec and a rest time longer than the voltage application time, or within an application voltage of 0.1 to 1.2 times the drive voltage of the optical element,
By applying a pulse voltage consisting of a repetition of a voltage application time of 1 μsec to 1 sec, which changes stepwise or with time from a lower voltage to a higher voltage, and a pause time longer than the voltage application time, the resistance of the optical element is increased. It has been confirmed that the voltage property is improved.

【0014】[0014]

【実施例】以下、図面を用いて本発明の実施例を詳細に
説明する。図1は、本発明に係る電界処理方法を用いた
液晶セルの構造を示す概略断面図である。この液晶セル
は、2枚のガラス基板1a,1bが互いに対向して配置
され、その間にセルギャップ制御用のスペーサー4を介
在させ隙間を設けて、該隙間に液晶5を注入して封止し
た構造である。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic sectional view showing the structure of a liquid crystal cell using the electric field processing method according to the present invention. In this liquid crystal cell, two glass substrates 1a and 1b are arranged to face each other, a gap is provided therebetween with a spacer 4 for controlling a cell gap therebetween, and a liquid crystal 5 is injected into the gap and sealed. Structure.

【0015】一方のガラス基板1aの表面には、インジ
ウム錫酸化物(以下ITOと略称する)からなる透明な
信号電極Sが複数本互いに平行に配置され、該信号電極
Sは絶縁膜2aで被膜されている。他方のガラス基板1
bの表面にはITOからなる透明な走査電極Lが信号電
極Sと直行する向きに複数本互いに平行に配置されてお
り、該走査電極Lは絶縁膜2aと同じ材料の絶縁膜2b
で被膜されている。各絶縁膜2a,2b上には配向膜3
a,3bが形成され、この配向膜3a,3bはラビング
により一軸配向処理が施されている。
On a surface of one glass substrate 1a, a plurality of transparent signal electrodes S made of indium tin oxide (hereinafter abbreviated as ITO) are arranged in parallel with each other, and the signal electrodes S are coated with an insulating film 2a. Have been. The other glass substrate 1
b, a plurality of transparent scanning electrodes L made of ITO are arranged in parallel with each other in a direction perpendicular to the signal electrodes S, and the scanning electrodes L are made of an insulating film 2b made of the same material as the insulating film 2a.
It is coated with. An alignment film 3 is formed on each of the insulating films 2a and 2b.
a, 3b are formed, and the alignment films 3a, 3b are subjected to a uniaxial alignment treatment by rubbing.

【0016】2枚のガラス基板1a,1bは、一部に液
晶の注入口を設けて貼り合わせし、該注入口から配向膜
3a,3bで挟まれ、スペーサ4により設けられた空間
5内に、液晶を注入した後、上記注入口は封止剤6で封
止される。
The two glass substrates 1a and 1b are provided with a liquid crystal injection port in a part thereof and bonded together. From the injection port, the two glass substrates 1a and 1b are sandwiched by alignment films 3a and 3b, and are placed in a space 5 provided by a spacer 4. After the liquid crystal is injected, the injection port is sealed with a sealant 6.

【0017】この液晶セルに、パルス電圧による電界処
理を行う。このパルス電圧は、光学素子の駆動電圧の
0.1〜1.2倍を印加電圧とし、1μsec〜1se
cの電圧印加時間と該電圧印加時間以上の休止時間との
繰り返しからなる電圧である。この処理を行うことによ
り、絶縁膜上の微小突起を破壊し、耐電圧性を向上させ
る。すなわち従来技術でも述べたように、周辺に比べ高
い電圧が印加されることになる突起部分がなくなるた
め、その部分から絶縁膜の絶縁破壊が進行することがな
く、耐電圧性が向上する。
The liquid crystal cell is subjected to an electric field treatment using a pulse voltage. This pulse voltage is applied at a voltage of 0.1 to 1.2 times the drive voltage of the optical element, and applied for 1 μsec to 1 sec.
The voltage is a voltage obtained by repeating the voltage application time c and the pause time longer than the voltage application time. By performing this process, minute projections on the insulating film are broken, and the withstand voltage is improved. That is, as described in the related art, since there is no protruding portion to which a higher voltage is applied compared to the periphery, the dielectric breakdown of the insulating film does not proceed from that portion, and the withstand voltage improves.

【0018】前述のような効果が得られるか否かを、図
2に示すパルス電圧を用いた電界処理を行い確認した。
このパルス電圧は、図2に示すように、電圧印加時間が
500μsecで、1sec毎に、+、−に印加する。
印加電圧を2,4,6,8,10Vと順次大きくしてい
き、各電圧毎の印加時間は5分とする。そして前記液晶
セルに対して下記5種類のパルス電圧で電界処理を行っ
た。ここで、液晶セルの絶縁膜材料として、東京応化
(株)社製 OCD TYPE2 P-59310-SGを用い、絶縁膜厚を
約100nmとし、450℃にて焼成して使用した。ま
た、この液晶セルには、チッソ(株)社製配向膜材料 P
SI-A-X007-S01及びメルク社製強誘電性液晶SCE8 を使用
した。 ・パルス1:印加電圧が2,4,6,8,10V ・パルス2:印加電圧が2,4,6,8,10,20V ・パルス3:印加電圧が2,4,6,8,10,20,
30,40V ・パルス4:印加電圧が2,4,6,8,10,20,
30,50,60V ・パルス5:印加電圧が2,4,6,8,10,20,
40,60,80V
Whether or not the above-mentioned effects were obtained was confirmed by performing an electric field treatment using a pulse voltage shown in FIG.
As shown in FIG. 2, this pulse voltage is applied to + and-every 1 second with a voltage application time of 500 μsec.
The applied voltage is sequentially increased to 2, 4, 6, 8, and 10 V, and the application time for each voltage is 5 minutes. The liquid crystal cell was subjected to electric field treatment with the following five types of pulse voltages. Here, OCD TYPE2 P-59310-SG manufactured by Tokyo Ohka Co., Ltd. was used as the insulating film material of the liquid crystal cell, the insulating film thickness was about 100 nm, and the film was fired at 450 ° C. before use. In addition, this liquid crystal cell includes an alignment film material P manufactured by Chisso Corporation.
SI-A-X007-S01 and ferroelectric liquid crystal SCE8 manufactured by Merck were used. Pulse 1: applied voltage is 2, 4, 6, 8, 10 V Pulse 2: applied voltage is 2, 4, 6, 8, 10, 20 V Pulse 3: applied voltage is 2, 4, 6, 8, 10 , 20,
30, 40V ・ Pulse 4: applied voltage is 2, 4, 6, 8, 10, 20,
30, 50, 60 V ・ Pulse 5: applied voltage is 2, 4, 6, 8, 10, 20,
40,60,80V

【0019】その後、液晶セルに60V、50kHzの
矩形波を5秒間印加して耐電圧性の測定を行ったとこ
ろ、表1に示す結果が得られた。いずれのセルもセルギ
ャップ1.5μm換算において60V以上の耐電圧性を
有していた。ここで、印加電圧60Vにおいても絶縁破
壊されなかった液晶セルは○、絶縁破壊された液晶セル
は×で表し、括弧内の数値は液晶セルのセルギャップを
示し、印加電圧はセルギャップ1.5μmに換算してあ
る。
Thereafter, a rectangular wave of 60 V, 50 kHz was applied to the liquid crystal cell for 5 seconds to measure the withstand voltage. The results shown in Table 1 were obtained. Each cell had a withstand voltage of 60 V or more in terms of a cell gap of 1.5 μm. Here, a liquid crystal cell that did not undergo dielectric breakdown even at an applied voltage of 60 V is represented by 、, a liquid crystal cell that has undergone dielectric breakdown is represented by x, the numerical value in parentheses indicates the cell gap of the liquid crystal cell, and the applied voltage is 1.5 μm. It has been converted to.

【0020】[0020]

【表1】 [Table 1]

【0021】また、実施例1と同様の条件で液晶セルを
作成し(絶縁膜の焼成温度は350℃と450℃とし
た)、上記の電界処理を行うことなく、60V,50k
Hzの矩形波を5秒間印加して耐電圧性の測定を行っ
た。その結果は、表2に示すように、電界処理を行った
ものに比べ、低い耐電圧性を示した。このことから、こ
のパルス電圧による電界処理を行うことにより、明らか
に耐電圧性が向上することが確認できた。
Further, a liquid crystal cell was prepared under the same conditions as in Example 1 (the sintering temperature of the insulating film was set at 350 ° C. and 450 ° C.).
Hz rectangular wave was applied for 5 seconds to measure the withstand voltage. As shown in Table 2, the results showed lower withstand voltage than those subjected to the electric field treatment. From this, it was confirmed that by performing the electric field treatment using the pulse voltage, the withstand voltage was clearly improved.

【0022】[0022]

【表2】 [Table 2]

【0023】ITO上に作成された上記絶縁膜に対し
て、蒸着によってAlの対向電極を取り付けて絶縁単体
における直流電界絶縁性を測定したところ、上記の電界
処理を行わなかった絶縁膜は3〜40Vで絶縁破壊を起
こしたのに対し、上記の電界処理を行った絶縁膜は60
Vまで絶縁破壊を起こさず上記電界処理の有効性が認め
られた。従って、上記電界処理は本実施例に挙げた構成
をもつ液晶光学素子だけでなく、広く絶縁膜を有する液
晶光学素子、ACプラズマディスプレイ、液晶光シャッ
ター、EL素子などの耐電圧特性を向上させる上で有効
である。
A DC electric field insulating property of the insulating unit alone was measured by attaching an Al counter electrode to the insulating film formed on the ITO by vapor deposition. While insulation breakdown occurred at 40 V, the insulation film subjected to the electric field treatment described above
The effectiveness of the electric field treatment was confirmed without causing dielectric breakdown up to V. Accordingly, the electric field treatment is not limited to improving the withstand voltage characteristics of not only the liquid crystal optical element having the configuration described in this embodiment but also a liquid crystal optical element having an insulating film, an AC plasma display, a liquid crystal optical shutter, and an EL element. Is effective in

【0024】こうして、パルス電圧による電界処理によ
って耐電圧性が向上するので、絶縁膜を厚くしたり、透
明基板の研磨を行ったりせずに、光学素子の絶縁性の向
上を図ることができる。従って、素子の機能低下を招か
ず、コスト増加も防ぐことができる。
As described above, since the withstand voltage is improved by the electric field treatment using the pulse voltage, the insulation of the optical element can be improved without thickening the insulating film or polishing the transparent substrate. Therefore, it is possible to prevent a decrease in function of the element and an increase in cost.

【0025】この電界処理に用いるパルス電圧は、光学
素子の駆動電圧の0.1〜1.2倍の印加電圧内で、よ
り低電圧から高電圧へと段階的に又は時間を追って変化
するものでも、同様の効果が得られる。
The pulse voltage used in the electric field processing changes from a lower voltage to a higher voltage stepwise or with time within an applied voltage of 0.1 to 1.2 times the driving voltage of the optical element. However, the same effect can be obtained.

【0026】[0026]

【発明の効果】本発明によれば、光学素子にパルス電圧
による電界処理を行うことにより、絶縁膜上の微小突起
を破壊することができるため、絶縁膜を厚くしたり、透
明基板の研磨を行ったりせずに、光学素子の絶縁性の向
上を図ることができるとともに、素子の機能低下を招か
ず、コスト増加も防ぐことができる効果がある。
According to the present invention, by subjecting an optical element to an electric field treatment using a pulse voltage, it is possible to destroy minute projections on the insulating film. It is possible to improve the insulating properties of the optical element without performing the steps, and to prevent the function of the element from deteriorating and prevent the cost from increasing.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る光学素子の電界処理を用いた液晶
セルの一例を示す概略断面図である。
FIG. 1 is a schematic sectional view showing an example of a liquid crystal cell using electric field processing of an optical element according to the present invention.

【図2】この電界処理のためのパルス電圧を示す波形図
である。
FIG. 2 is a waveform diagram showing a pulse voltage for the electric field processing.

【符号の説明】[Explanation of symbols]

1a,1b ガラス基板 2a,2b 絶縁膜 1a, 1b Glass substrate 2a, 2b Insulating film

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) G02F 1/1333 505 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. 7 , DB name) G02F 1/1333 505

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電極と該電極を被膜する絶縁膜とが形成
された透明基板を用いた光学素子に対し、前記電極にパ
ルス電圧を印加して、前記絶縁膜上の微小突起を破壊す
る光学素子の電界処理方法。
1. An optical element using a transparent substrate on which an electrode and an insulating film covering the electrode are formed, wherein a pulse voltage is applied to the electrode to break a minute protrusion on the insulating film. An electric field treatment method for a device.
【請求項2】 パルス電圧は、光学素子の駆動電圧の
0.1〜1.2倍を印加電圧とし、1μsec〜1se
cの電圧印加時間と該電圧印加時間以上の休止時間との
繰り返しであることを特徴とする請求項1記載の光学素
子の電界処理方法。
2. The pulse voltage is applied at a voltage of 0.1 to 1.2 times the drive voltage of the optical element, and applied for 1 μsec to 1 sec.
2. The electric field processing method for an optical element according to claim 1, wherein the voltage application time of c and the pause time longer than the voltage application time are repeated.
【請求項3】 パルス電圧は、光学素子の駆動電圧の
0.1〜1.2倍の印加電圧内で、より低電圧から高電
圧へと段階的に又は時間を追って変化することを特徴と
する請求項2記載の光学素子の電界処理方法。
3. The pulse voltage changes stepwise or from time to time from a lower voltage to a higher voltage within an applied voltage of 0.1 to 1.2 times the drive voltage of the optical element. The electric field processing method for an optical element according to claim 2.
JP07136729A 1995-06-02 1995-06-02 Electric field treatment method for optical element Expired - Fee Related JP3073145B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07136729A JP3073145B2 (en) 1995-06-02 1995-06-02 Electric field treatment method for optical element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07136729A JP3073145B2 (en) 1995-06-02 1995-06-02 Electric field treatment method for optical element

Publications (2)

Publication Number Publication Date
JPH08327992A JPH08327992A (en) 1996-12-13
JP3073145B2 true JP3073145B2 (en) 2000-08-07

Family

ID=15182144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07136729A Expired - Fee Related JP3073145B2 (en) 1995-06-02 1995-06-02 Electric field treatment method for optical element

Country Status (1)

Country Link
JP (1) JP3073145B2 (en)

Also Published As

Publication number Publication date
JPH08327992A (en) 1996-12-13

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