JP3082674B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly, to a microcomputer capable of effectively performing screening by a dynamic BT (burn-in test).

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a conventional microcomputer. Referring to FIG. 5, a conventional microcomputer 30 outputs a test ROM (read only memory) 3 that can be read only during a test, and a signal 9 for setting the microcomputer 30 to a state for testing. A test mode setting unit 2, a CPU 1, external terminals such as a clock terminal 5, a reset terminal 6, and a test terminal 7,
CPU 1 has a test RO during a test.
The program stored in M3 can be executed.

When the dynamic BT mode is set by a signal input to the test terminal 7, the test mode setting unit 2 outputs a dynamic BT mode signal 9 to the CPU 1 and the test ROM 3. The microcomputer 30 is set to the dynamic BT mode by the dynamic BT mode signal 9.

A reset generator 14 for outputting a pulse signal is connected to a reset terminal 6 of the microcomputer 30. When a reset signal 12 is input from the reset generator 14, an output of the clock generator 13 connected to the clock terminal 5 is output. In synchronization with the clock signal 8 input from the CPU 1, the CPU 1 reads an instruction from the test ROM 3 and starts operation.

[0005] Regardless of the operation of the microcomputer 30, the reset generator 14 supplies the next pulse (reset pulse) to the reset terminal 6 of the microcomputer 30 at the set frequency.

A reset signal 1 of the microcomputer is generated by a pulse output from the reset generator 14.
2, the reset signal 12 initializes the CPU 1 and the test ROM 3, and the CPU 1 operates by reading an instruction from the beginning of the program stored in the test ROM 3.

Since the time between one reset and the next reset is determined by the frequency of the pulse signal set in the reset generator 14, the time between resets is increased and stored in the test ROM 3. Command CP
In order for U1 to perform more, reset generator 14 is typically set to its lowest frequency.

On the other hand, since the CPU 1 executes instructions in synchronization with the clock signal 8, as the number of clocks input between resets increases, the CPU 1 can execute more instructions. Therefore, the clock generator 13 is normally set to the highest frequency.

As described above, in the conventional microcomputer 30, the number of instructions that can be executed in the dynamic BT mode is determined by the lowest frequency of the reset generator 14 and the highest frequency of the clock generator.

[0010]

As described above, in a conventional microcomputer, a dynamic BT is used.
After setting the mode, a pulse generator provided outside a BT (burn-in test) furnace is used as the clock generator 13 and the reset generator 14, respectively, and a reset signal and a clock signal are supplied to the microcomputer 30 under test, respectively. Test ROM
The screening is performed by causing the program stored in No. 3 to be executed.

However, in the dynamic BT mode, a program command executed by the microcomputer is executed only during a period from the input of one reset pulse to the input of the next reset pulse.

When a BT (burn-in test) is performed by operating all the functions of the microcomputer, the size of the test program increases, and the test ROM is increased.
As a result, the interval between resets determined by the lowest frequency of the pulse generator and the execution clock determined by the limit of the driving capability of the pulse generator are stored in the test ROM 3. There is a problem that the entire program cannot be executed.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a built-in test ROM.
In a dynamic BT that runs by
It is an object of the present invention to provide a microcomputer capable of performing screening effectively even when the memory capacity of the OM is increased.

[0014]

In order to achieve the above object, a microcomputer according to the present invention comprises: a test ROM for storing a program and data for testing a built-in function; and a program stored in the test ROM.
Is read and executed, and when the execution of the program ends,
A CPU for outputting a program end signal, a test mode setting means for generating a test mode signal that becomes active during a test, and when the test mode signal changes to active, and when the program end signal is output.
Then, the test ROM and the CPU are initialized and the program is initialized.
And means for outputting an internal reset signal to start program read and execute, and during the test, the CPU
Does not depend on an externally supplied reset signal.
Der those to run the program returns Ru.

[0015] It should be noted that, when the test signal is active,
The apparatus may further include means for multiplying a clock supplied to the inside of the microcomputer.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a microcomputer according to a first embodiment of the present invention.

Referring to FIG. 1, microcomputer 20 has a test RO which can be read only during a test.
M3 and a test mode setting unit 2 which outputs a signal for setting for testing the microcomputer 20
A reset generation circuit 4 for outputting an internal reset signal 11 for resetting the inside of the microcomputer 20,
The CPU 1 includes a clock terminal 5, a reset terminal 6, and a test terminal 7 as external terminals.
1 is capable of executing a program stored in the test ROM 3.

When the dynamic BT mode is set by a signal input to the test terminal 7, the test mode setting unit 2 sends a dynamic BT mode signal 9 to the CPU 1, the test ROM 3, and the reset generation circuit 4. Output.

When the microcomputer 20 is set to the dynamic BT mode by the dynamic BT mode signal 9, the reset generation circuit 4 outputs the internal reset signal 11 to the CPU 1 and the test ROM 3.

When the internal reset signal 11 is input, the clock generator 1 connected to the clock terminal 5
3 in synchronization with the clock signal 8 output from the
Reads an instruction from the test ROM 3 and starts operation.

The reset generation circuit 4 according to the embodiment of the present invention will be described below. FIG. 2 is a diagram showing an example of the circuit configuration of the reset generation circuit 4, and FIG. 3 is a timing chart for explaining the operation of the reset generation circuit.

Referring to FIG. 2, reset generation circuit 4
Is a two-input NAND circuit 22 that receives an output of an inverter 21 that outputs an inverted signal of a program end signal 10 and a dynamic BT mode signal 9, and a two-input NAN.
A delay circuit 24 for delaying the output of the D circuit 22 (referred to as signal A), an inverter 25 for outputting an inverted signal of the delay output of the delay circuit 24 (referred to as "signal B"), and the signal A and the signal B as inputs. A two-input OR circuit 27, an inverter 23 that outputs an inverted signal of the reset signal 12 input from the reset terminal 6, and a dynamic BT mode signal 9
And a two-input OR circuit 2 for receiving the output of the inverter 23
6 and NANDs having outputs of OR circuits 26 and 27 as inputs
And an internal reset signal 11 from the output of the NAND circuit 28. Note that the delay circuit 24 is composed of, for example, an analog delay using a resistor or a capacitor.

When the dynamic BT mode signal 9 is at a low level, the two-input NAND circuit 22 outputs a high level irrespective of the input signal level of the other input terminal, and the two-input OR circuit 27 does not depend on the level of the signal B. Output a high level.

The two-input OR circuit 26 has a dynamic BT
Since the mode signal 9 is at low level, the reset signal 1
The inverted signal from the second inverter 23 is output as it is.

The outputs of the two-input OR circuits 26 and 27 are input to the two input terminals of the two-input NAND circuit 28. Since the output of the two-input OR circuit 27 is at a high level, the two-input NAND circuit 28 Outputs the inverted output of the two-input OR circuit 26.

That is, the output (internal reset signal 11) of the two-input NAND circuit 28 has the same logic level as the reset signal 12.

The operation when the dynamic BT mode signal 9 is at a high level will be described below with reference to the timing chart of FIG.

When the dynamic BT mode signal 9 changes from low level to high level, the two-input OR circuit 26
Outputs a high level regardless of the output of the inverter 23.

At first, the program end signal 10 is at a low level and the inverter 21 outputs a high level. Therefore, the two-input NAND circuit 22 outputs an inverted signal (low level) of the dynamic BT mode signal 9 as a signal A. .

The signal B, which is the output of the inverter 25, is delayed from the signal A (transition from low level to high level) by the delay time of the delay circuit 24.

For this reason, during the delay time (DELAY),
Both inputs of the two-input OR circuit 27 become low level,
The two-input OR circuit 27 outputs a low level signal.

Therefore, the two-input NAND circuit 28 outputs a high level as the internal reset signal 11 during this delay time.

After the delay time of the delay circuit 24, the inverter 2
Since the signal 5 is output after inverting the high level of the signal A, the signal B is at the high level.

When signal B goes high, a two-input OR
The circuit 27 outputs a high level, and accordingly, a two-input N
The AND circuit 28 outputs a low level as the internal reset signal 11.

When the execution of the program stored in the test ROM 3 is completed, the CPU 1 sets the program end signal 10 to a high level for a certain period.

At this time, since the dynamic BT mode signal 9 input to one input terminal is at a high level, the two-input NAND circuit 22 inverts the output signal of the inverter 21 to which the program end signal 10 is input. Output.

When the program end signal 10 changes from the low level to the high level, the inverter 21, the two-input NAND
The level of the circuit 22 is inverted twice, and the signal A becomes the high level of the same logic as the program end signal 10.

The output of the two-input OR circuit 27 remains at the high level, and the output of the two-input NAND circuit 28 remains at the low level.

After a delay time determined by the delay circuit 24, the signal B output from the inverter 25 changes from a high level to a low level.

When the program end signal 10 changes from high level to low level, the signal A changes to low level.

Thereafter, the internal reset signal 11 is output for the delay time of the delay circuit 24 and the program stored in the test ROM 3 is executed in the same manner as when the dynamic BT signal first changes from low level to high level. Is done.

As described above, in the embodiment of the present invention, all the programs stored in the test ROM 3 can be executed regardless of the frequency of the reset generator 14 input from the reset terminal 6.

A modification of the above-described first embodiment of the present invention
This will be described below as a reference example . Referring to Figure 4, the
In the reference example , the microcomputer 20 executes a program stored in the test ROM 3, a test ROM 3 that can be read only at the time of a test, a test mode setting unit 2 that outputs a signal for setting a setting for testing the microcomputer, and the like. A CPU 1 capable of
The pulse input from the clock terminal 5 is multiplied, and the internal clock signal 16 is stored in the CPU 1 and the test mode setting unit 2 in the microcomputer 20 and in the test ROM 3.
, And a reset terminal 6 and a test terminal 7 as external terminals.

The multiplying circuit 15 has a built-in selector function for selecting whether the internal clock signal 16 is a signal after multiplication or the clock signal 8.

When the dynamic BT mode is set by the test terminal 7, the test mode setting unit 2
Dynamic BT for PU1 and test ROM3
The mode signal 9 is output.

The microcomputer 20 is set to the dynamic BT mode by the dynamic BT mode signal 9.

The clock signal 8 input from the clock generator 13 connected to the clock terminal 5 is multiplied by the multiplying circuit 15 and supplied as an internal clock signal 16 to the inside of the microcomputer.

When the CPU 1 receives the reset signal 12 from the reset generator 14 connected to the reset terminal 6, the CPU 1 reads a command from the test ROM 3 and starts operation in synchronization with the internal clock signal 16.

The internal clock signal 1 is
6 has a larger number of clocks than the clock signal, so that the number of instructions that can be executed by the CPU 1 can be larger than the number of instructions determined by the maximum frequency of the clock generator 13.

[0050]

As described above, according to the present invention,
The program stored in the built-in test ROM can be automatically reset after execution by the signal indicating the dynamic BT mode.
Even if the content (size) of the OM increases, all can be executed. Therefore, according to the present invention, it is possible to operate all the functions of the microcomputer, and it is possible to perform more effective screening than the conventional dynamic BT.

[0051] Then, by multiplying the execution clock, by increasing the number of execution clocks, it is possible to run a program stored in the test ROM to the end.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a reset generation circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart of the reset generation circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a microcomputer according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a microcomputer capable of performing a conventional dynamic BT.

[Explanation of symbols]

 1 CPU 2 Test mode setting unit 3 Test ROM 4 Reset generation circuit 5 Clock terminal 6 Reset terminal 7 Test terminal 8 Clock signal 9 Dynamic BT mode signal 10 Program end signal 11 Internal reset signal 12 Reset signal 13 Clock generator 14 Reset generator 15 Multiplication Circuit 16 Internal clock signal 21, 23, 25 Inverter element 22, 28 2-input NAND circuit element 24 Delay element 26, 27 2OR element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 15/78 G01R 31/28-31/30

Claims (1)

(57) [Claims] 1. A test ROM for storing a program and data for testing a built-in function, and a program stored in the test ROM for reading out the program
Program, and when the execution of the program ends, the program ends.
A CPU for outputting a completion signal, a test mode setting means for generating a test mode signal which becomes active during the test, and when the test mode signal is changed to active, before
When the program end signal is output,
ROM and the CPU are initialized to read the program.
Means for outputting an internal reset signal for initiating output and execution , during the test,
Repeatedly execute the program without depending on the trigger signal
Formed by way, microcomputer, characterized in that.