JP3085276B2 - Logic simulation verification method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit (L).
The present invention relates to a method and apparatus for logic simulation of an apparatus, and more particularly, to a method for creating a library.

[0002]

2. Description of the Related Art In recent years, semiconductor LSI devices have been miniaturized, highly integrated, and highly functional. As a result, libraries of logic simulators used for logic design have become complicated. For this reason, it is required that the library be created with high accuracy in a short time.

In the logic simulator library, mainly, for each block (cell): 1. Input terminal-output terminal delay time information Logic function information representing an output signal is described for an input signal.

FIG. 8 is a configuration diagram for creating an LSI logic cell library which is a conventional logic simulation verification device (refer to Japanese Patent Application Laid-Open No. 5-129435). FIG.
1 is an input data file for characterizing, 2 is a circuit simulator (characterizing), and 3 is an input data file between input terminals and output terminals of each cell of the input data file 1 calculated by characterization performed using the circuit simulator 2. Is a delay time file that stores the delay time.

[0005] Here, it is determined whether or not the delay time from which the library of the logic simulator is created is intuitively, that is, visually correct, from the result of the delay time calculated by the characterization performed using the circuit simulator. ing. As a result, if the delay time is not appropriate, the input data of the input data file 1 is reviewed.

Next, if the delay time of the delay time file 3 is appropriate, the library conversion tool 4 converts the delay time of the delay time file 3 and the logic function information of the logic description file 5 into a logic cell library. It is stored in the logic cell library file 6.

Next, the logic simulator 7 performs a logic simulation of the library of the logic cell library file 6 using the test vector 8. This logic simulation result is stored in the logic simulation result vector 9.

[0008] Here, a person determines with naked eyes whether or not logic function information representing an output signal has been correctly assigned to the above-mentioned input signal and a logic simulation has been performed. As a result, if not, the logic function information of the logic description file 5 is reviewed.

[0009]

In the above-described conventional logic simulation method, once the logic function information representing the output signal with respect to the input signal is created, it can be used even if the design rule becomes new. The input terminal-output terminal delay time information is such that the design rule is 0.5, for example.
When shifting from μm to 0.35 μm, it is necessary to rewrite everything.

After the library is stored in the logical cell library file 6, if there is an error in the delay time calculated by the characterization that is the basis of the conversion of the library, the processing is naturally redone. However, there is a problem that if a human performs the verification of the delay time after the above-mentioned characterization intuitively, much time is required and accuracy is low.

Further, when the library of the logic simulator 7 is created, the logic function information is created in advance, and a delay time is assigned to the logic description by the library conversion tool 4, so that it is considered that the logic function information is correct. For this purpose, a logic simulation is performed using the test vector 8. However, if humans instinctively verify the results of logic simulation, it will still take a lot of time,
There was a problem that accuracy was low.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention calculates an improvement rate of the delay time of the basic circuit in the new design rule with respect to the delay time of the basic circuit in the old design rule. The delay time of the block in the new design rule is predicted from the delay time and the improvement rate of the block other than the basic circuit in the rule. That is, the delay time in the new design rule is predicted from the delay amount in the past old design rule, and the delay time after the characterization is compared and verified. After that, a library for logic simulation is created, and the library verification by logic simulation is compared for each block by comparing the delay time calculated from the logic simulation result vector with the delay time of the delay time as the generation source. Verifies the output schedule time for the test vector. As a result, the total verification time is reduced and the accuracy is improved.

[0013]

FIG. 1 is a block diagram showing an embodiment of a logic simulation verification apparatus according to the present invention.
This is obtained by adding a delay time verification unit 10 and a logic simulation verification unit 20 to the components shown in FIG.

The delay time verifying section 10 will be described. The delay time file 11 stores a basic circuit and each block delay time in the old design rule. Prediction tool 12
Calculates the improvement rate of the delay time of the basic circuit in the new design rule of the delay time file 3 with respect to the delay time of the basic circuit in the old design rule of the delay time file 11. For example, assuming that the inverter shown in FIG. 2A is used as a basic circuit, the prediction tool 12 uses the inverter shown in FIG.
Output signal OUT with respect to the fall of the input signal IN1 shown in FIG.
Entering a delay time tau ₂ of the fall of the output signal OUT1 for the rise of the first rising edge of the delay time tau ₁ and the input signal IN1. Here, an example of the delay time of the basic circuit in the old design rule is shown in FIG. 3A, and an example of the delay circuit of the basic circuit in the new design rule is shown in FIG. Next, the prediction tool 12 calculates an improvement rate. Here, the improvement rate is (T _old -T _new ) / T _old × 100% where T _old is the delay time of the basic circuit in the old design rule, and T _new is the delay time of the basic circuit in the new design rule. In the case of the examples of FIGS. 3A and 3B, FIG.
(C) is obtained.

Next, the prediction tool 12 calculates a minimum value of 70.9% and a maximum value of 83.4% among the improvement rates shown in FIG.
A predicted delay time range in a new design rule of a circuit (block) other than the basic circuit is obtained by using only Here, the minimum value and the maximum value of the predicted delay time range of a certain block are represented by F
_min (t), if _{F max (t), F min} (t) = t × (1-0.790) + α F max (t) = t × (1-0.834) + α , however, t is The delay time α of the block in the old design rule is a constant. That is, from the respective delay times t, which have been characterized by the old design rule of blocks other than the basic circuit, using the above two equations, the predicted delay time ranges F _min (t), F _max (t) in the new design rule Is calculated. FIG. 4 shows an example of a certain block. The calculated predicted delay time range in the new design rule is stored in the predicted delay time range file 13.

The verification tool 14 reads the delay time of each block characterized by the new design rule from the delay time file 3 and determines whether or not it is within the predicted delay time range of each block in the predicted delay time range file 13. For example, the delay time characterized by the new design rule of the other block shown in FIG. 5 corresponding to the predicted delay time range of the other block in the new design rule of FIG. 4 is read and compared. The result of this comparison is indicated by "OK" and "NG" at the right end of FIG.
This is output as a report 15 for each vector for each block. Here, if it is determined as “NG” outside the predicted delay time range, the input data of the input data file 1 is reviewed and necessary correction is made. In this manner, characterization can be verified.

The verification of the characterization results is all "O
If “K”, the logic simulation verification unit 20 is operated. The logic simulation verification unit 20 compares the delay time after characterization according to the new design rule of the delay time file 3 with the simulation result (vector) in the logic simulation result vector 14 for each block vector, and allocates the delay time to the library correctly. It has a verification tool 21 for verifying that it has been performed. For example, a result vector shown in FIG. Note that FIG.
FIG. 6B shows the result vector of FIG. Next, as shown in FIG. 7, the verification tool 21 calculates an inter-terminal delay time PAT from the result vector, and uses the delay time of the delay time file 3 as a reference value REF to obtain an error ERR (= REF) from the inter-terminal delay time PAT. −
PAT) is calculated, and the determination results “OK” and “NG” are displayed based on whether ERR = 0 or not and output as a report 22 for each vector for each block.

As described above, the logic description can be verified by comparing the result after the logic simulation with the delay time at the time of characterization.

[0019]

As described above, according to the present invention, when a logic cell library is developed, verification is performed in each of characterization and library conversion, thereby shortening the verification time and improving accuracy. it can. As a result, an accurate library can be provided to the user without delay.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a logic simulation verification device according to the present invention.

2A and 2B show an example of a basic circuit used in FIG. 1, wherein FIG. 2A is a circuit diagram, FIG. 2B is a timing diagram of an input signal, and FIG. 2C is a timing diagram of an output signal.

FIG. 3 is a table showing characteristics of the basic circuit of FIG. 2, wherein (A) shows a delay time under an old design rule, (B) shows a delay time under a new design rule, and (C) shows an improvement rate. .

FIG. 4 is a table showing a predicted delay time range according to a new design rule of another block in FIG. 1;

FIG. 5 is a table showing an example of a delay time after characterization according to a new design rule of another block in FIG. 1;

6A and 6B show the results of the logic simulation in FIG. 1, wherein FIG. 6A is a table and FIG. 6B is a timing chart.

FIG. 7 is a table illustrating an example of a verification report of a logic simulation result in FIG. 1;

FIG. 8 is a configuration diagram showing a conventional logic simulation verification device.

[Explanation of symbols]

 1 Input data file 2 Circuit simulator (characterize) 3 Delay time file 4 Library conversion tool 5 Logic description file 6 Logic cell library file 7 Logic simulator 8 Test vector 9 Logic simulation result vector 10 Delay time verification unit 11 Delay time file 12 Prediction tool 13 Predicted delay time range file 14 Verification tool 15 Report 20 Logical simulation verification unit 21 Verification tool 22 Report

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-320440 (JP, A) JP-A-7-36957 (JP, A) JP-A-5-225278 (JP, A) JP-A-9-9 305650 (JP, A) JP-A-7-56980 (JP, A) Satoshi Kato et al., Et al., "Automation of library data verification in ASIC design", IPSJ, IPSJ Symposium, In August 1993, Vol. 93, no. 5, p. 163-168 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 JICST file (JOIS)

Claims (14)

(57) [Claims] Calculating an improvement rate of a delay time of the basic circuit in a new design rule with respect to a delay time of a basic circuit in an old design rule; Estimating a delay time of the block in the new design rule from an improvement rate. 2. The method according to claim 1, further comprising the step of comparing the delay time of the block characterized by the new design rule with the predicted delay time to determine whether the input data of the block conforms to the new design rule. Claim 1
3. The logic simulation verification method according to 1. 3. A step of calculating an improvement rate of a delay time of the basic circuit in a new design rule with respect to a delay time of a basic circuit in an old design rule; and calculating a minimum value and a maximum value of the calculated improvement rate. A logic simulation verification method comprising: estimating a delay time range of the block in the new design rule from delay times of blocks other than the basic circuit and minimum and maximum values of the improvement rate in the old design rule. . And determining whether or not the delay time of the block characterized by the new design rule is within the predicted delay time range, and determining whether the input data is appropriate according to the new design rule of the block. 4. The logic simulation verification method according to claim 3, further comprising the step of: 5. A step of calculating an improvement rate of a delay time of the basic circuit in a new design rule with respect to a delay time of a basic circuit in an old design rule; and calculating a minimum value and a maximum value of the calculated improvement rate. The minimum value of the delay time of the blocks other than the basic circuit in the old design rule, the representative value and the maximum value, and the minimum value of the improvement rate, the minimum value of the delay time of the block in the new design rule from the maximum value, Predicting ranges of the representative value and the maximum value, respectively. 6. A method according to claim 1, wherein the minimum value, the representative value, and the maximum value of the delay time of the block characterized by the new design rule are within the ranges of the minimum value, the representative value, and the maximum value of the predicted delay time. 6. The logic simulation verification method according to claim 5, further comprising a step of determining whether or not the input data is appropriate according to the new design rule of the block. 7. Furthermore, comparison calculating inter-terminal delay time of the block from the results vector that logic simulation, and the block character between rise the terminal delay time calculated inter-terminal delay time of the block of 7. The logic simulation verification method according to claim 2, further comprising the step of determining. 8. A first delay time file (1) storing a delay time after characterization in an old design rule.
1), a second delay time file (3) for storing a delay time after characterization in the new design rule, and a delay after characterization of the basic circuit in the old design rule from the first delay time file Calculate the improvement rate of the delay time after characterization of the basic circuit in the new design rule from the second delay time file with respect to time, and calculate the delay after characterization of blocks other than the basic circuit in the old design rule A logic simulation verification device comprising: a prediction tool (12) for predicting a delay time after characterization of the block in the new design rule from a time and the improvement rate. 9. A verification tool for comparing the delay time of the block characterized by the new design rule with the predicted delay time to determine whether the input data is suitable for the new design rule of the block. The logic simulation verification device according to claim 8, comprising (14). 10. A first delay time file (1) storing delay times after characterization in an old design rule.
1), a second delay time file (3) for storing a delay time after characterization in the new design rule, and a delay after characterization of the basic circuit in the old design rule from the first delay time file Calculating the improvement rate of the delay time after characterization of the basic circuit in the new design rule from the second delay time file with respect to time; calculating the minimum value and the maximum value of the calculated improvement rate; A prediction tool (12) for predicting the delay time range after characterization of the block in the new design rule from the delay time after characterization of blocks other than the basic circuit in the old design rule and the minimum and maximum values of the improvement rate. And a logic simulation verification device comprising: And determining whether or not the delay time of the block characterized by the new design rule is within the predicted delay time range, and determining whether the input data is suitable for the block with the new design rule. Verification tool (1)
The logic simulation verification device according to claim 10, further comprising (4). 12. A first delay time file (1) storing a delay time after characterization in an old design rule.
1), a second delay time file (3) for storing a delay time after characterization in the new design rule, and a delay after characterization of the basic circuit in the old design rule from the first delay time file Calculating an improvement rate of the delay time of the basic circuit in the new design rule from the second delay time file with respect to time; calculating a minimum value and a maximum value of the calculated improvement rate; From the minimum value, representative value, and maximum value of the delay time after characterization of the blocks other than the basic circuit and the minimum value and maximum value of the improvement rate, the minimum value of the delay time after characterization of the block in the new design rule And a prediction tool (12) for predicting ranges of the representative value and the maximum value, respectively. 13. The minimum, representative value and maximum value of the delay time after characterization of the block characterized by the new design rule are the minimum value and representative value of the predicted delay time after characterization. And a verification tool (14) for determining whether the input data is within the respective ranges of the maximum value and determining whether or not the input data is appropriate according to the new design rule of the block.
The logic simulation verification device according to claim 12, comprising: 14. Furthermore, the logical simulation result vector (8) for storing the result of the logic simulation, the calculated inter-terminal delay block from logic simulation result, terminal-to-terminal delay time was characterized of the block and claim comprises a comparator determining verification tool (21) and a delay time between the calculated terminal 9,1
14. The logic simulation verification device according to 1 or 13 .