JP3086342B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device requiring a high access time.

[0002]

2. Description of the Related Art Referring to the drawings, a TLB (Translation Look-aside) which is an example of a conventional semiconductor memory device will be described.
Buffer) CAM (Content Addressable Memory) in the circuit
The array section will be described.

FIG. 5 is a schematic diagram showing a part of a circuit of a reading system in a CAM array section of a conventional TLB circuit ("IEICE Technical Report", vol. 9).
1 No. 215 See pages 13-19. FIG. 6 is a timing chart in the conventional example.

In FIG. 5 , reference numeral 11 denotes a CAM cell corresponding to a memory cell for storing data, a match line ML for reading data, and a data line for controlling data output.
Connected to DL. Reference numeral 12 denotes a precharge P-channel MOS transistor (hereinafter, referred to as "PMOSTr"), the source of which is connected to the potential generation circuit 14, and the drain of which is connected to the match line ML. The gate is supplied with a precharge control signal PR. An inverter 13 receives, amplifies, and outputs data of the match line ML.

The operation of the semiconductor memory device configured as described above will be described below.

Now, the potential generating circuit 14 generates a potential of Vcc-Vth (where Vcc is a power supply voltage and Vth is P
This is the threshold voltage of the MOSTr12. ). While the precharge control signal PR is at the “L” level, the PMOS Tr
12 becomes conductive, and the match line ML is precharged to the potential Vcc-Vth generated by the potential generating circuit 14.

When the precharge control signal PR goes to "H" level, the PMOS Tr 12 is turned off and precharge is stopped, and the potential of the match line ML is fixed at Vcc-Vth.

Therefore, when the data line DL is inverted from "L" to "H" at a time immediately after that, data reading is started. When “H” data is read from the CAM cell 11 to the match line ML, the potential of the match line ML does not change.

Therefore, since the input of the inverter 13 does not exceed the circuit threshold V0 of the inverter 13, the output of the inverter 13 remains at "L".

When "L" data is read from the CAM cell 11 to the match line ML, the potential of the match line ML is dropped from the potential Vcc-Vth in the initial state to the ground potential Vss.

At this time, when the potential of the match line ML becomes equal to or less than the circuit threshold value V0 of the inverter 13, an "H" signal is output to the output of the inverter 13.

[0012]

In the above configuration, in order to output data read from the CAM cell 11 (corresponding to a memory cell) at high speed, a match line is required.
It is necessary to reduce the time required to pull down the potential of ML (corresponding to a bit line) from the potential in the initial state to the circuit threshold of the inverter 13 serving as an output circuit.

Therefore, conventionally, instead of setting the potential of the match line ML in the initial state to the power supply potential Vcc, the potential of the match line ML is set to the potential of Vcc-Vth generated by the potential generating circuit 14. The vertical margin of the circuit threshold of the inverter 13 is reduced to increase the data output speed.

However, since the potential of the match line ML is fixed to a constant value before the data reading is started, if this value is too small, the potential of the match line ML and the circuit of the inverter 13 are not changed. The margin of the upper and lower relations of the threshold values becomes too small, and there is a possibility that the output of the inverter 13 is erroneously inverted due to noise on the match line ML.

Therefore, in order to secure a margin of the vertical relationship between the potential of the match line ML and the circuit threshold of the inverter 13 to a size that does not cause a malfunction due to noise, the description is omitted in the conventional example. Malfunctions are prevented by providing means for suppressing output of erroneous data to the outside.

For this reason, in the above-described configuration, the margin of the vertical relationship between the potential of the match line ML and the circuit threshold of the inverter 13 must be increased to a certain degree or more, and the data output cannot be speeded up much. In addition, there is a problem that the amount of hardware is increased by providing the data output suppressing unit.

In view of the above problems, it is an object of the present invention to provide a semiconductor memory device capable of preventing a malfunction due to noise on a bit line and achieving high-speed data reading.

[0018]

[Means for Solving the Problems] Claim1Semiconductor description
The storage device includes a memory cell for storing data, and a memory cell.
A word line connected to the
A bit line connected to the recell for reading stored data
And data read from the memory cell connected to the bit line.
An output circuit that amplifies and outputs the data, and an output circuit that is connected to the bit line.
The potential of the bit line is determined by the enable signal.PrechargeDo
From precharge circuit and enable signalInverteddelay
A delay circuit that generates an enable signal and connected to a bit line
Bit by the enable signal and the delay enable signal
The potential of the wirePrecharge set by precharge circuit
Potential between the power level and the circuit threshold of the output circuitTo
And a potential setting circuit for setting.

The semiconductor memory device according to the second aspect of the present invention is characterized in that:
2. The semiconductor memory device according to claim 1 , wherein the potential setting circuit is connected in series between a power supply potential and a ground potential, and the first and the second conductivity types are of the same conductivity type.
The second, third and fourth MOS transistors,
A common connection point of the drain and the source of the second and third MOS transistors is connected to the bit line, and one of the gates of the first and second MOS transistors is connected to the third and fourth M transistors.
A delay enable signal is input to one of the gates of the OS transistor and the first, second, third, and fourth MOS
An enable signal is input to a gate to which a delay enable signal has not been input among the gates of the transistors.

According to a third aspect of the present invention, there is provided a semiconductor memory device, a memory cell for storing data, a word line connected to the memory cell for controlling input / output of data, and a bit connected to the memory cell for reading stored data. And an output circuit connected to the bit line for amplifying and outputting data read from the memory cell, a precharge path for precharging the potential of the bit line and a discharge path for discharging, and a precharge path and a discharge by an enable signal. Potential control means for switching the activation period of the path.

The potential control means includes a first P-channel MOS transistor having a drain connected to the bit line and an activation control signal corresponding to a delay signal of the precharge control signal input to the gate, and a drain connected to the first P-channel MOS transistor. P channel M
A second P-channel MOS transistor connected to the source of the OS transistor, a precharge control signal is input to the gate, and an inverted signal of the precharge control signal is input to the source; a second P-channel MOS transistor;
N-channel MOS with common connection of each source and each drain
It consists of transistors.

[0022]

According to the structure of the present invention, the bit line potential is set to a value having a sufficient margin with respect to the circuit threshold value of the output circuit during the period before the start of the data read operation, whereby the noise on the bit line is reduced. By setting the bit line potential to a potential that guarantees a minimum margin with respect to the circuit threshold of the output circuit simultaneously with the start of reading, high-speed reading of data becomes possible.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings.

[First Embodiment; Corresponding to Claims 1 and 2] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
Will be described.

[0025] Figure 1 is Ri schematic diagram der of the semiconductor memory device of the first embodiment of the present invention, FIG 2 is a half of FIG. 1
Ru timing diagram der conductor storage device.

In FIG. 1, reference numeral 200 denotes potential control means for controlling the potential of the bit line BL. Reference numeral 111 denotes a memory cell for storing data, which is connected to a word line WL for controlling data output and a bit line BL for outputting data.

Reference numeral 115 denotes a precharge level for the bit line BL.
A P-channel MOS transistor (hereinafter referred to as “PMOSTr”) corresponding to a precharge circuit for precharging to V1 (V1 >> Vcc-Vth), the source of which is a power supply potential (Vcc) node, and the drain of which is Bit line BL
Are connected, and a precharge control enable signal PR is input to the gate.

Reference numeral 212 denotes a power supply potential (Vcc) and a ground potential
(Vss) N-channel MOS transistors connected in series
Transistors (hereinafter referred to as “NMOS Tr”) 201, 20
, 203, 204, and NMOS Tr 201,
Precharge control enable signal PR is applied to each gate of 204
Is input to each gate of the NMOS Trs 202 and 203.
The delay signal DPR is input and the NMOS Trs 202 and 203 share
Potential setting circuit connecting the common connection point to the bit line BL.
You.

The NMOS Tr 201, 202, 203, 2
04 has a channel length and channel width of NMOS Tr20.
State in which all of 1, 202, 203 and 204 are conducting
At the common connection point of NMOS Trs 202 and 203
To the potential (Vcc-Vth) at which the pump circuit 117 operates.
Value V2 (V1 >>V2> Vcc-Vth)
Has been adjusted.

The delay circuit 216 has a precharge control rice
To generate a delayed signal DPR of the cable signal PR.
You.

Reference numeral 117 denotes NMOS Trs 118, 121 to 1
23 and PMOS Trs 119 and 120,
This is a current mirror type sense amplifier circuit serving as an output circuit which detects, amplifies and outputs a slight potential transition of the bit line BL.

PMO forming sense amplifier circuit 117
The source of the STr 120 is connected to the Vcc potential node,
The drain and the gate are connected to each other.

[0033] PMOSTr119 has a source connected to the Vcc potential node, mutual PMOSTr120 and gate
It is connected to.

The NMOS Tr 123 has a source and a gate connected to a power supply potential (Vcc) node.

The NMOS Tr 118 is a PMOS Tr 119
, The gate is connected to the bit line BL, the NMOS Tr 121 is connected in series to the PMOS Tr 120, the gate is connected to the drain of the NMOS Tr 123, and the sources of the NMOS Trs 118 and 121 are commonly connected.

The NMOS Tr 122 includes an NMOS Tr 11
8, 121 are connected in series between the source interconnection point and the ground potential (Vss) node.

Here, the sense amplifier activation signal SE is input to the gate of the NMOS Tr 122,
A connection point between the NMOS transistor 19 and the NMOS Tr 118 is connected to the output node OUT.

The operation of the semiconductor memory device configured as described above will be described below with reference to FIGS. FIG. 2 is a timing chart of the semiconductor memory device.

In this semiconductor memory device, the initial state,
That sense amplifier activating signal SE is "L", the period of the precharge control enable signal PR is "L", the bit line BL is PMOSTr115 by the precharge level V1
(V1 >> Vcc-Vth) and NMOSTr
Vcc-Vth is applied to the gate of 121 by NMOS Tr123.
(Where Vth is the threshold voltage of the NMOS Tr 123), and the gate of the NMOS Tr 118 is supplied with the Vcc potential by the activated PMOS Tr 115.

This Vcc potential is at the precharge level V1. In this state, the sense amplifier circuit 117 is in an inactive state, a constant potential Vi is output to the output node OUT, and the gate voltage (Vcc-Vth) of the NMOS Tr 121 is set to the circuit threshold value of the sense amplifier circuit 117. Has become.

The potential Vi of the output node OUT is a PMOS
By adjusting the channel lengths and channel widths of the Trs 119 and 120 and the NMOS Trs 118 and 121, it is set so that other logic circuits connected to the output of the sense amplifier circuit 117 do not operate.

At this time, the delay signal DPR is at "H" level.
Thus, the NMOS Trs 202 and 203 are in an activated state.
However, the NMOS Trs 201 and 204 are in an inactive state.
Therefore, a DC current path is not formed by the potential setting circuit 212.
Not.

[0043] Now, from the time Ts ₁ in the period of Ts _2, when the precharge control enable signal PR becomes the "H" PMOS
Tr115 becomes non-conductive, and NMOS Tr201 ,
204 becomes conductive.

As a result, the NMOS transistors 201, 202,
All the transistors 203 and 204 are activated.
As a result, a DC current path is formed, and the potential of the bit line BL is
Charged.

In this embodiment, each transistor is set so that the potential V2 has a value V2 (V2> Vcc-Vth) having a minimum margin with respect to the potential (Vcc-Vth) at which the sense amplifier circuit 117 operates. The channel length and channel width are adjusted.

It should be noted that the potential V2 is equal to the potential of the NMOS transistors 201 and 20.
2, 203 and 204 are turned on and determined by the equivalent resistance ratio of the NMOS Tr when a DC current path is formed.

Next, at a certain time during the period from time Ts ₁ to Ts ₂ , the word line WL becomes “H” and the data stored in the memory cell 111 is read out, and the sense amplifier activation signal
When SE goes to “H”, the sense amplifier circuit 117 is activated and data output is started.

When the data stored in the memory cell 111 is "L", "H" is read from the memory cell 111 to the bit line BL. That is, the potential of the bit line BL is fixed at V2, and the NMOS Tr 118 maintains the conductive state.

When the sense amplifier activating signal SE becomes "H", the NMOS Tr 122 is turned on. Therefore, "L" is rapidly output to output node OUT.

When the data stored in the memory cell 111 is "H", "L" is read out to the bit line BL, and the potential of the bit line BL is lowered from V2 to Vss.

At this time, the potential applied to the gate of the NMOS Tr 118 decreases, and the potential Vcc-Vth (the sense amplifier circuit 11
When the voltage becomes equal to or less than (threshold of 7), the sense amplifier circuit 117 enters an operating state, and the potential Vi is output to the output node OUT at a substantially constant level.

As described above, at the moment when the sense amplifier activation signal SE becomes "H", the potential of the bit line BL is set to the value V1 having a sufficient margin with respect to the threshold voltage of the sense amplifier circuit 117. Then, the output of erroneous data due to noise is prevented, and the potential of the bit line BL is forcibly set to V2 by the potential setting circuit 112 after the sense amplifier activation signal SE becomes "H". The margin for the threshold voltage of the sense amplifier circuit 117 can be reduced and the speed of data output can be increased.

As described above, according to this embodiment, the PMO
A precharge circuit including the STr 115 and the bit line BL
The potential setting circuit 212 for controlling the precharge level and different potential of the precharge circuit is provided, before the start read operation, by the precharge circuit, the bit line
BL is precharged so that the margin of the vertical relationship between the potential of the bit line BL and the circuit threshold of the sense amplifier circuit 117 is sufficiently large. Word line that controls data output
Reading of data from the memory cell 111 onto the bit line BL is started by a signal on WL. In synchronization with this, the potential
The setting circuit 212 adjusts the potential of the bit line BL so that the margin of the vertical relationship between the potential of the bit line BL and the circuit threshold of the sense amplifier circuit 117 is minimized.

As described above, by controlling the potential of the bit line BL in accordance with the data read start time, an erroneous signal due to the noise of the bit line BL at the start of the read can be obtained without increasing the amount of hardware. Data output is prevented, noise is stable, and data can be read at high speed.

[0055] As described above, in this embodiment, the precharge
Control signal and the delay signal DPR.
And a PMOS Tr 115 corresponding to a precharge circuit.
DifferentSet to potential levelA potential setting circuit 212,
Since the delay circuit 216 having a simple configuration is provided,
Data reading at high speed.
Can be.

[ Second Embodiment: Corresponding to Claim 3 ] Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a schematic configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

This semiconductor memory device is different from the first embodiment in that a potential control means 500 different from the potential control means 200 of the semiconductor memory device shown in FIG. 1 is provided. And the same components are denoted by the same reference numerals as in FIG.

The potential control means 500 includes a PMOS Tr 50
1 and 502 and an NMOS Tr 503. This potential control means 500 will be described in detail.

In FIG. 3 , PMOS Trs 501, 50
2 is connected in series between the bit line BL and the signal line of the inverted precharge control enable signal XPR.

The NMOS Tr 503 is a PMOS Tr 50
2 and each gate, each drain, and each source are commonly connected. The sense amplifier activation signal SE is input to the gate of the PMOS Tr 501, and the PMOS Tr
The precharge control enable signal PR is input to each gate of the NMOS Tr2 and the NMOS Tr 503.

[0062] The structure semiconductor memory device as described above, the following 3, the operation will be described with reference to FIG.
Incidentally, FIG. 4 is a timing diagram of the semiconductor memory device shown in FIG.

In this semiconductor memory device, the sense amplifier activation signal SE is “L”, the precharge control enable signal PR is “L”, and the inverted precharge control enable signal is
During the period when XPR is “H”, PM serving as precharge means
Since the OSTrs 501 and 502 become conductive and the inverted precharge control enable signal XPR is "H", the bit line BL is precharged to a potential V1 near Vcc (V1 >> Vcc-Vth).

[0064] Here, the precharge control enable signal PR is "H" at a certain time Ts _1, the inverted precharge control enable signal XPR is inverted to "L", PMOSTr5
02 becomes non-conducting, and P becomes discharge means.
The MOSTr 501 and the NMOS Tr 503 enter a conductive state. The inversion precharge control enable signal XPR is “L”
Therefore, the bit line BL starts to be discharged.

Next, at time Ts ₂ , the sense amplifier activation signal
When SE changes to “H”, the PMOS Tr 501 is turned off, so that the potential control means 500 is turned off and disconnected from the bit line BL.

At this time, sense amplifier circuit 117 is activated at the same time. In this embodiment, the channel length of each transistor so as not to exceed the circuit threshold Vcc-Vth of the potential of the bit line BL in the time _{Ts 2 V2 (V2> Vcc-} Vth) is a sense amplifier circuit 117, a channel width I am adjusting.

In the semiconductor memory device shown in FIG. 3 , similarly to the semiconductor memory device shown in FIG. 1, by controlling the potential of bit line BL in accordance with the data read start timing, the semiconductor memory device is stable against noise, A semiconductor memory device that reads data at high speed can be configured.

As described above, in this embodiment, the potential control means 500 is controlled by the PMOS Trs 501 and 502 and the NMOS Tr.
Control by the sense amplifier activating signal SE, the precharge control enable signal PR, and the inverting precharge control enable signal XPR, which is constituted by the Tr 503, has an effect that noise is stable and data reading is performed at high speed.

The sense amplifier circuit 1 is used as an output circuit.
17, the potential control means 500 and the sense amplifier circuit 1
By inputting and controlling the same sense amplifier activating signal SE to the control circuit 17, there is an effect that the potential control means 500 and the sense amplifier circuit 117 can be reliably synchronized.

In the first and second embodiments, a current mirror type sense amplifier circuit 117 is used as an output circuit.
And using, by providing the potential control hand stage 2 00,500, and enabling entry of the sense amplifier activating signal SE at an early timing, it has been attempted to further speed-up of the data output, the output circuit A simple gate such as an inverter or a NAND may be used. In this case, the degree of integration of the semiconductor integrated circuit can be improved by simplifying the circuit configuration.

[0071]

As described above, according to the present invention, the bit line potential is set to a value having a sufficient margin with respect to the circuit threshold of the output circuit during the period before the start of the data read operation. To prevent malfunction due to noise
By setting the bit line potential to a potential that guarantees a minimum margin with respect to the circuit threshold of the output circuit at the same time as the start of reading, data can be read at high speed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation in the embodiment.

FIG. 3 is a schematic configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation in the embodiment.

FIG. 5 is a schematic configuration diagram of a conventional semiconductor memory device.

FIG. 6 is a timing chart for explaining an operation in the conventional example.

[Explanation of symbols]

 111 memory cells  115 P-channel MOS transistor (Precharge
Circuit)  117 Sense amplifier circuit (output circuit) 201 to 204 N-channel MOS transistor 212 Potential setting circuit 216 Delay circuit 500 Potential control means 501, 502 P-channel MOS transistor 503 N-channel MOS transistor BL Bit line WL Word line PR Precharge control enable signal  SE sense amplifier activation signal DPR delay signal XPR inversion precharge control enable signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/40-11/419 G11C 16/00-17/18

Claims (3)

(57) [Claims] 1. A memory cell for storing data, a word line connected to the memory cell for controlling input / output of data, a bit line connected to the memory cell for reading stored data, and a bit line connected to the memory cell. An output circuit connected to and amplifying and outputting data read from the memory cell;
A precharge circuit connected to the bit line for precharging the potential of the bit line with an enable signal; a delay circuit for generating a delay enable signal inverted from the enable signal; a delay circuit connected to the bit line and the enable signal A precharge circuit for setting the potential of the bit line by an enable signal by the precharge circuit;
A semiconductor memory device comprising: a potential setting circuit for setting a potential at an intermediate level between a di-level and a circuit threshold of the output circuit . 2. A potential setting circuit comprising first, second, third and fourth MOS transistors of the same conductivity type connected in series between a power supply potential and a ground potential.
A common connection point between the drain and the source of the OS transistor is connected to a bit line, and one of the gates of the first and second MOS transistors and one of the gates of the third and fourth MOS transistors are connected to the bit line. Receiving an enable signal from among the gates of the first, second, third, and fourth MOS transistors to which the delay enable signal has not been input. Item 2. The semiconductor memory device according to item 1 . 3. A memory cell for storing data; a word line connected to the memory cell for controlling input / output of data; a bit line connected to the memory cell for reading stored data; An output circuit connected to and amplifying and outputting data read from the memory cell;
A potential control means including a precharge path for precharging the potential of the bit line and a discharge path for discharging, and a potential control means for switching an activation period of the precharge path and the discharge path by an enable signal; A first P-channel MOS transistor having an gate connected to an activation control signal corresponding to a delay signal of a precharge control signal, and a drain connected to a source of the first P-channel MOS transistor. A second P-channel MOS transistor having a gate to which a precharge control signal is input and a source to which an inversion signal of the precharge control signal is input; and a common connection between the second P-channel MOS transistor, each gate, each source and each drain. N-channel MOS transistor Semiconductor storage device.