JP3089121B2 - Test instruction string generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a test instruction sequence for testing the function of a processor in a computer system, and more particularly to a method for testing machine instructions using a combination of instructions used in a user environment. The present invention relates to a test instruction sequence generation method for generating a sequence.

[0002]

2. Description of the Related Art In recent years, a microprocessor is often used in a computer system. And the microprocessor used, in order to increase its processing speed,
It often has a pipeline control mechanism, an instruction cache, a data cache, and various buffers, and has a complicated configuration.

[0003] When testing the function of the microprocessor, that is, comprehensively testing whether the function of the microprocessor is operating normally, there is a time constraint. An important issue is how to effectively perform a combination test of instructions. At present, a test using an instruction sequence generated randomly using random numbers is used as an optimal tool.

In a conventional test method using a random instruction sequence, it is general that a test instruction sequence is generated by randomly selecting instructions using random numbers for all mounted machine instructions. Was the way.

FIG. 10 is a diagram for explaining an example of a conventional test instruction sequence generation method. Reference numeral 51 denotes an instruction selection table; 52, a random number generation unit; 53, a random number generated by the random number generation unit; An instruction selection unit 55 represents a memory unit that expands instructions.

[0006] In the example shown in FIG.
The number 1 to 99 is assigned to the implemented machine instruction by 1, and the instruction selecting unit 54 selects an instruction from the instruction selection table 51 according to the random number from 1 to 99 output by the random number generation unit 52. Then, the instructions are developed in the memory 55 one by one. In this way, a test instruction sequence is generated on the memory 55.

[0007]

In the above-described conventional method for generating a random instruction, a test instruction sequence is generated by selecting an instruction with a random number for all of the mounted instructions, so that a test instruction sequence is generated.・ System (O
S) and the sequence of instructions actually used in the application program are considerably different, and it has been difficult to test effectively with a combination of instructions actually used in the user environment.

The present invention has been made in view of the above problems, and has as its object to provide a test instruction sequence generating method capable of effectively generating a machine instruction sequence based on a combination of instructions used in a user environment. .

[0009]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims.

That is, according to the first aspect of the present invention, an instruction appearance frequency table for registering the appearance frequency of each machine instruction is created based on the load module generated by the general-purpose compiler. This is a test instruction sequence generation method for generating a test machine instruction sequence by selecting each machine instruction at a given ratio and randomly determining the order of appearance of each machine instruction.

According to the second aspect of the present invention, the instruction frequency table is created for each type of compiler.
It is a test instruction sequence generation method described above.

According to a third aspect of the present invention, there is provided the test instruction sequence generating method according to the first aspect, wherein the instruction appearance frequency table is created for each optimization condition at the time of compilation.
According to a fourth aspect of the present invention, there is provided the test instruction sequence generating method according to the first aspect, wherein the instruction occurrence frequency table is created for each profile of the load module.

According to the present invention, a plurality of instruction appearance frequency tables generated based on different standards are prepared in advance, and the instruction appearance frequency according to the purpose of the test is selected from the plurality of instruction appearance frequency tables. 2. The test instruction sequence generation method according to claim 1, wherein a test machine instruction sequence is generated by selectively using a table.

[0014]

According to the test instruction sequence generation method of the present invention, the conventional method of selecting an instruction based only on random numbers is basically changed to a method of selecting an instruction randomly within a range of instruction appearance frequency in a user environment. I have to.

That is, in the test instruction sequence generating method according to the first aspect, the frequency of occurrence of machine instructions in the load module is checked using a load module adapted to a user environment such as an OS or an application program. , Generating a test machine instruction sequence in consideration of the appearance frequency.

Hereinafter, the method will be described using an example. FIG. 1 is a diagram for explaining the basic principle of the test instruction sequence generation method of the present invention, and FIG. 2 is a diagram for explaining an instruction selection table.

In FIG. 1, reference numeral 11 denotes an operating system.
A load module of a system (OS) or an application program, 11a is a text part in the load module, 11b is a data part in the load module, 11c is an instruction (bit configuration) in the text part 11a, and 12 is a load module. An appearance frequency generation program for retrieving the text portion 11a of the module and calculating the occurrence frequency of the instruction. Reference numeral 13 denotes an operation code portion of the instruction in a matrix (in the example of FIG. 1, the 0th and 1st bits of the operation code are set in the horizontal direction and the (Corresponding to the third and fourth bits) to represent an instruction appearance frequency table for recording the appearance frequency. In FIG. 2, reference numeral 14 denotes an instruction appearance frequency table, and reference numeral 15 denotes an adjusted instruction appearance frequency table.

Hereinafter, the method of the present invention will be described step by step. (1) The appearance frequency generation program 12 reads the load module 11 as an input, and reads the text module 11 therein.
The instruction of a is analyzed one by one. In this example, each instruction 11c is 4 bytes long.

(2) An entry in the instruction appearance frequency table 13 corresponding to the first 4 bits of the instruction 11c (where the appearance frequency is%
(Stored as a value), the occurrence frequency is obtained by equation (1), and written again to the corresponding entry of the instruction appearance frequency table 13.

The update logic is as follows. (N × α + 1) / (n + 1) Expression (1) n: The number of instructions that have appeared so far, and the instruction appearance frequency table 13
Is recorded at the top of the number of occurrence instructions.

Α: Appearance frequency of the corresponding instruction so far (3) The appearance frequency of another instruction must be updated (decreased). The appearance frequency is obtained from equation (2), and Write.

(N × α) / (n + 1) Equation (2) (4) Finally, the number of appearing instructions is increased by one and written into the instruction appearance frequency table 13. (5) The processes of (1) to (4) are executed up to the last instruction in the text part.

The instruction frequency table 13 generated by the processing of the above (1) to (5) and the adjusted instruction selection table 15 reflecting the frequency of occurrence of instructions are generated from the prior art. Hereinafter, the generation logic of the adjusted instruction selection table 15 will be described.

(1) An operation code is read from each entry of the instruction selection table 14, and an entry obtained by multiplying the corresponding entry of the instruction appearance frequency table 13 by the appearance frequency is copied to the adjusted instruction selection table 15. I do. (2) In the case of FIG. 1, the first entry (LO
AD instruction) is 50%, so in the example of FIG. 1, one entry is provided for 10% of the instruction appearance frequency, so that one entry × 5 is obtained. Copy to selection table 15. If the accuracy is increased to the unit of 1%, it becomes 1 × 50, and 50 entries are copied to the adjusted instruction selection table 51.

(3) Since the appearance frequency of the second entry (MVI instruction) is 0%, this entry is not copied to the adjusted instruction selection table 15. (4) Since the appearance frequency of the third entry (STORE instruction) is 10%, it becomes 1 × 1 and one entry is copied to the adjusted instruction selection table 15.

In this way, the processing is continued for all the entries of the instruction selection table 14. The adjusted instruction selection table 15 thus created is a generation table in which the appearance frequency is taken into consideration, and thereafter, a test instruction sequence is generated by random numbers using the adjusted instruction selection table 15 in the same manner as in the prior art. I do.

In this way, it is possible to generate a test instruction sequence based on a combination of instructions according to the user environment.

According to the second aspect of the present invention, the above-mentioned instruction appearance frequency table is created for each type of compiler and stored in a file, and the most appropriate instruction appearance frequency table is obtained from the file according to the purpose of the test. Then, a test instruction sequence is generated using the instruction appearance frequency table.

That is, the application program uses a different language depending on its purpose, and the compiler uses and expands the instruction sequence considerably. Therefore, by using the instruction appearance frequency table according to the type of the compiler, it is possible to efficiently generate a test instruction sequence executed in various user environments.

According to the third aspect of the present invention, the instruction appearance frequency table is created and filed for each optimization condition at the time of compiling, and is stored in a file.
The most appropriate instruction frequency table is extracted from the file, and a test instruction sequence is generated based on the instruction frequency table.

That is, the compiler is generally equipped with an optimize level option, and the instruction sequence to be expanded differs depending on the level specification. Therefore,
An instruction frequency table is prepared for each optimization level. In this way, it is possible to efficiently generate an instruction sequence to be executed in various user environments.

According to the fourth aspect of the present invention, the instruction frequency table is created for each profile of the load module and stored in a file.
The most appropriate instruction frequency table is extracted from the file, and a test instruction sequence is generated based on the instruction frequency table.

That is, the load module has a considerably different combination of instructions used depending on the nature of the program. For example, a science and technology operation program often uses floating-point operation instructions, and an OS program often uses privileged instructions. Therefore, in order to generate an instruction sequence suitable for the user environment, an instruction appearance frequency table suitable for the characteristics of the program is prepared.

According to the invention described in claim 5, for example,
An instruction frequency table created for each type of the compiler, an instruction frequency table created for each optimizing condition at the time of the compiler, an instruction frequency table created for each profile of the load module, and the like are pre-filed. In advance, the most appropriate instruction appearance frequency table is extracted from the file corresponding to the purpose of the test, and a test instruction sequence is generated based on the instruction appearance frequency table.

Thus, in accordance with the purpose of the test,
It is possible to efficiently generate an optimal test machine instruction sequence.

[0036]

【Example】

(A) First Embodiment As a first embodiment of the present invention, a method of creating an instruction appearance frequency table from a plurality of load modules will be described. This embodiment is an embodiment corresponding to the first aspect of the present invention.

The first embodiment of the present invention is based on the basic structure shown in FIG. 1 and FIG.
Performs the processing shown in the flowchart of FIG. The appearance frequency generation program 12 is a program that operates under the OS, and the instruction appearance frequency table 13 exists as a file in the storage device of the system.

The operation of the first embodiment of the present invention will be described below with reference to the flowchart of FIG. In the following description, the meaning of the steps in the flowchart is represented by reference symbol [S].

(1) In S301, a file of an instruction appearance frequency table is read. (2) In S302, the text section 11a in the load module 11 is read.

(3) In S303, an entry of the instruction appearance frequency table (instruction appearance frequency table) 13 for the operation code (first 4 bits) of the instruction 11c is obtained. (4) In S304, a new frequency is obtained from equation (1), and the entry is updated.

(5) In S305, the frequency of occurrence of another instruction is updated using equation (2).

(6) In S306, it is determined whether all the entries of the instruction appearance frequency table 13 have been updated.
If the result is YES, the process moves to S307. The result is N
If O, the process returns to S305.

(7) In S307, the number of appearing instructions in the instruction appearance frequency table 13 is incremented by one. (8) In S308, it is determined whether or not the above processing has been performed for all the instructions in the text section 11a. If the result is YES, the process moves to S309. If the result is NO, the process returns to S303.

(9) In S309, all loads
It is determined whether the above processing has been performed for the module. If the result is YES, the process moves to S310. If the result is NO, the process returns to S302 to read another load module.

(10) In S310, the updated instruction appearance frequency table file is written to the storage device.

(11) After that, as in the case of the prior art, the adjusted instruction selection table 15 is obtained from the original instruction selection table 14 by using the instruction appearance frequency table 13.
Is generated, and a test instruction sequence is generated by random numbers using the instruction selection table 15 after the adjustment.

As described above, the appearance frequency generation program 12 receives the plurality of load modules 11 as inputs,
The instruction appearance frequency table 13 is created and updated. In addition, by using various types of load modules 11, it is possible to create a more averaged instruction appearance frequency table 13 suitable for the user environment.

(B) Second Embodiment As a second embodiment of the present invention, a method of creating an instruction appearance frequency table for each type of compiler will be described. This embodiment is an embodiment corresponding to the second aspect of the present invention.

An application program uses a different language depending on its purpose, and its compiler uses and expands an instruction sequence considerably. Therefore, by preparing an instruction appearance frequency table according to the purpose, it is possible to efficiently generate an instruction sequence to be executed in various user environments.

FIG. 4 is a diagram showing a specific example of the instruction appearance frequency table.
By defining a, an instruction appearance frequency table is prepared for each type of compiler. Instruction appearance frequency table 1 in FIG.
In the example of No. 6, the compiler attribute is defined in a character format, but may be coded. Appearance frequency generation program 12
Reads the compiler attributes defined in the load module and determines which instruction frequency table to use when analyzing instructions. If the load module does not have such an attribute, a compiler attribute is given in the startup parameter of the appearance frequency generation program.

The processing in the embodiment described above is shown in the flowchart for explaining the processing in the second embodiment of the present invention in FIG.

Hereinafter, the flowchart of FIG. 5 will be described. (1) In S501, a load module is read. (2) In S502, it is determined whether the read load module has a compiler attribute. If the result is YES, the process moves to S503. If the result is NO, the flow shifts to S504, where the compiler attribute is acquired from the startup parameter, and the flow shifts to S505.

(3) In S503, a compiler attribute is obtained from the load module. (4) In S505, the file of the appearance frequency table corresponding to the compiler attribute is read.

(5) Subsequent processing is the same as in the case of the flowchart shown in FIG.

(C) Third Embodiment As a third embodiment of the present invention, a method of setting an optimizing (optimizing) condition at the time of compilation in an instruction appearance frequency table will be described. This embodiment is an embodiment corresponding to the third aspect of the present invention.

The compiler generally has an optimize level option, and the instruction sequence to be expanded differs according to the level specification. Therefore, an item of the optimization level 16b is provided in the instruction appearance frequency table 16 shown in FIG. 4, and the instruction appearance frequency table is prepared for each optimization level. In the example of the instruction appearance frequency table 16 in FIG. 4, the optimization level is defined in a character format, but may be coded.

The appearance frequency generation program 12 reads the optimization level defined in the load module, and determines which instruction appearance frequency table to use when analyzing instructions. If there is no such level definition in the load module, an optimization level is given in the startup parameter of the appearance frequency generation program.

In this way, it is possible to efficiently generate an instruction sequence to be executed in various user environments. The processing in the embodiment described above is shown in the flowchart of FIG. 6 for explaining the processing in the third embodiment of the present invention.

Hereinafter, the flowchart of FIG. 6 will be described. (1) In S601, a load module is read. (2) In S602, it is determined whether or not there is an optimization definition. If the result is YES, the process moves to S603. If the result is NO, the flow shifts to S604, where the optimization level is obtained from the start-up parameter and S6.
Move to 05.

(3) In S603, an optimization level is obtained from the load module. (4) In S605, the instruction appearance frequency table file corresponding to the optimization level is read.

(5) Subsequent processing is the same as in the flowchart shown in FIG.

(D) Fourth Embodiment As a fourth embodiment of the present invention, a method for setting a profile of a load module in an instruction appearance frequency table will be described. This embodiment is an embodiment corresponding to the invention described in claim 4.

The load module to which the present invention is applied is an OS or an application program of a general user, and the instructions to be used and the combination thereof vary considerably depending on the characteristics of the program. For example, in the case of a science and technology operation program, floating-point operation instructions are frequently used, and in an OS program, privileged instructions are often used. Therefore, it is necessary to prepare an instruction appearance frequency table suitable for the characteristics of the program in order to generate an instruction sequence suitable for the user environment.

Therefore, a profile 16c is defined in the instruction appearance frequency table 16 shown in FIG. 4, and an instruction appearance frequency table is prepared for each profile. In the example of the command appearance frequency table 16 in FIG. 4, the profile is defined in a character format, but may be coded. The appearance frequency generation program 12 reads the profile given from the startup parameter and determines which instruction appearance frequency table to use when analyzing the instruction.

The processing in the embodiment described above is similar to the processing in FIG.
This is shown in a flowchart for explaining the processing in the fourth embodiment of the present invention. Hereinafter, the flowchart of FIG. 7 will be described.

(1) In S701, a load module is read. (2) In S702, a profile is obtained from the activation parameters. (3) In S703, a file of the appearance frequency table corresponding to the profile is read.

(4) Subsequent processing is the same as in the flowchart of FIG.

(E) Fifth Embodiment As a fifth embodiment of the present invention, a method of selecting and using a plurality of instruction appearance frequency tables to generate a test instruction sequence will be described.

The present embodiment is a method for generating a test instruction sequence using the instruction appearance frequency tables created in the first to fourth embodiments described above. This is a corresponding embodiment.

FIG. 8 is a diagram for explaining a fifth embodiment of the present invention. (1) The test instruction sequence generation program 27 reads the instruction appearance frequency table file 21 required according to the type of test, and creates the adjusted instruction selection table 23 according to the appearance frequency.

In the creation method, the content of the file of the original instruction selection table 22 is read, and the frequency of occurrence of the instruction is obtained from the instruction frequency table. If the instruction has an appearance frequency of 50%, the entry is multiplied by 50 and registered in the adjusted instruction selection table 23. If the instruction has an appearance frequency of 5%, the entry is multiplied by 5 and registered.

(2) Thus, for all instructions,
An adjusted instruction selection table 23 according to the appearance frequency table is created. (3) Then, it requests the random number generation unit 24 to generate a random number, obtains an instruction from the adjusted instruction selection table 23 using the random number 25, and writes it in the test instruction sequence file 26 as a test instruction. Then, instructions of a size required as a test instruction sequence are developed in the same procedure.

FIG. 9 is a flow chart for explaining the processing in the fifth embodiment of the present invention. Hereinafter, the flowchart of FIG. 9 will be described.

(1) In S901, the command frequency table file 21 corresponding to the activation request is read. (2) In S902, the file of the original instruction selection table 22 is read.

(3) In S903, an instruction appearance frequency corresponding to an entry in the instruction selection table 22 is obtained from the instruction appearance frequency table. (4) In S904, the instructions of the number of entries corresponding to the instruction appearance frequency are stored in the adjusted instruction selection table 23.

(5) In S905, it is determined whether or not the processing of S903 and S904 has been executed for all entries of the instruction selection table 22. If the result is YES, the process moves to S906, and if the result is NO, the process returns to S903.

(6) In S906, an instruction is selected from the adjusted instruction selection table 23 based on the random number. (7) In S907, it is determined whether an instruction sequence of a designated size has been generated as a test machine instruction sequence. If the result is YES, the process moves to S907, and if the result is NO, the process returns to S906.

(8) In S908, the generated test instruction sequence is stored in the test instruction sequence file 26.

[0079]

As described above, the following effects can be obtained by using the test instruction sequence generation method of the present invention.

(1) A test instruction sequence can be generated without waste by using only instructions suitable for a test purpose. (2) The method of the present invention has versatility, even if the microprocessor to be tested is different, only the original instruction selection table needs to be changed in correspondence with the microprocessor.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a basic principle of a test instruction sequence generation method according to the present invention.

FIG. 2 is a diagram for describing an instruction selection table.

FIG. 3 is a flowchart illustrating a process according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a specific example of an instruction appearance frequency table.

FIG. 5 is a flowchart illustrating a process according to a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating a process according to a third embodiment of the present invention.

FIG. 7 is a flowchart illustrating a process according to a fourth embodiment of the present invention.

FIG. 8 is a diagram for explaining a fifth embodiment of the present invention.

FIG. 9 is a flowchart illustrating a process according to a fifth embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of a conventional test instruction sequence generation method.

[Explanation of symbols]

 Reference Signs List 11 load module 11a text part in load module 11b data part in load module 11c instruction in text part (bit configuration) 12 appearance frequency generation program 13 instruction appearance frequency table 14 instruction selection table 15 instruction selection table after adjustment 16 Instruction Appearance Frequency Table 16a Compiler Attributes in Instruction Appearance Frequency Table 16b Optimize Level in Instruction Appearance Frequency Table 16c Profile in Instruction Appearance Frequency Table 21 Instruction Appearance Frequency Table File 22 Instruction Selection Table 23 Adjusted Instruction Selection Table 24 Random number generator 25 Random number 26 Test instruction sequence file 27 Test instruction sequence file generation program

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 CSDB (Japan Patent Office)

Claims (5)

(57) [Claims] A load generated by a general-purpose compiler.
Based on the module, create an instruction frequency table to register the frequency of each machine instruction, select each machine instruction at a ratio according to the instruction frequency table, and randomly arrange the order of appearance of each machine instruction. A method for generating a test instruction sequence, comprising determining a test instruction sequence and generating a test instruction sequence. 2. The test instruction sequence generation method according to claim 1, wherein the instruction appearance frequency table is created for each type of compiler. 3. The test instruction sequence generation method according to claim 1, wherein the instruction appearance frequency table is created for each optimization condition at the time of compilation. 4. The test instruction sequence generating method according to claim 1, wherein the instruction appearance frequency table is created for each profile of the load module. 5. A plurality of instruction appearance frequency tables generated based on different standards are prepared in advance, and an instruction appearance frequency table according to the purpose of the test is selected and used from among the plurality of instruction appearance frequency tables. 2. A method for generating a test instruction sequence according to claim 1, wherein a machine instruction sequence is generated.