JP6451989B2 - Information processing apparatus, information processing method, and information processing program - Google Patents

Description

  The present invention relates to an information processing apparatus, an information processing method, and an information processing program.

  In recent years, with the high integration of LSI (Large Scale Integration), the manufacturing cost of LSI has increased and the lead time has also increased. Under these circumstances, if the quality of the LSI is poor, it will not be possible to ship as planned due to increased costs due to rework and an increase in manufacturing TAT (Turn Around Time), which will inconvenience the customer. Will lose their trust. For this reason, it is becoming increasingly important to improve the quality before manufacturing the LSI. In order to ensure the quality of the LSI, it is necessary for the designer to check by himself / herself, but it is also important for the third party to confirm, and the evaluation by simulation is given as a representative method, and the test program used there The importance of is increasing.

  For this reason, each manufacturer has traditionally used a test program or the like to sufficiently improve the quality before manufacturing the LSI, but in reality, there are still many cases where LSI rework occurs. . This may be different from the instruction sequence that is actually executed at the customer site because the test program used in the simulation before the LSI release is an instruction sequence created manually or an automatically generated random instruction sequence. It is also one of the factors. However, in order to use the instruction sequence output by the compiler as a test program, it has been difficult due to system call processing, memory capacity limitations, and the like.

  In order to solve these problems, Patent Document 1 registers the appearance frequency of each machine instruction in the instruction appearance frequency table, creates an instruction selection table reflecting the appearance frequency of the instruction, and this instruction selection table. A technique for generating a test instruction sequence by randomly selecting an instruction from a random number is disclosed. Japanese Patent Application Laid-Open No. 2004-151867 discloses a technique for creating an instruction weight table and a test area address table from a log information tabulation result table, and creating a test instruction string of a test instruction string table based on the instruction weight table and the test area address table. Is disclosed.

Japanese Patent No. 3089121 Japanese Patent Laid-Open No. 11-265298

  However, the technique described in Patent Document 1 only considers the order of instructions. For example, in LSI development, problems that are likely to occur when executing instruction sequences are often caused not only by the order of instructions, but also by the dependency of registers and memory addresses. It was inadequate. On the other hand, Patent Document 2 creates a test area address table and refers to a memory address when generating a test instruction sequence. However, such a memory address is an address indicating a location where a failure has occurred. It does not reflect address dependencies.

  The objective of this invention is providing the technique which solves the above-mentioned subject.

In order to achieve the above object, an information processing apparatus according to the present invention provides:
Appearance frequency calculating means for calculating the appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determining unit that determines a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
Test instruction sequence generation means for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
Is provided.

In order to achieve the above object, an information processing method of an information processing apparatus according to the present invention includes:
An appearance frequency calculating means for calculating an appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determining unit that determines a relation between an access target of the predetermined instruction and an access target of the at least two preceding and following instructions in the execution instruction sequence;
A test instruction sequence generation means uses, as a test instruction sequence for testing the predetermined instruction, an instruction sequence including the predetermined instruction and maintaining the association of the access target, based on the appearance frequency of the instruction and the relationship of the access target A test instruction sequence generation step to be generated;
including.

In order to achieve the above object, an information processing program according to the present invention provides:
An appearance frequency calculating step for calculating an appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determination step for determining a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
A test instruction sequence generation step for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
Is executed on the computer.

  According to the present invention, a test instruction sequence having the characteristics of an execution instruction sequence generated by a compiler can be generated, and quality before manufacture in designing LSIs can be easily ensured.

It is a block diagram which shows the structure of the information processing apparatus which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the test instruction sequence processing system containing the information processing apparatus which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the function structure of the information processing apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the instruction code table which concerns on 2nd Embodiment of this invention, an instruction appearance frequency table, a register related table, and a memory area related table. It is a figure which shows the structure of the instruction table classified by frequency concerning 2nd Embodiment of this invention. It is a figure which shows the structure of the test instruction sequence table which concerns on 2nd Embodiment of this invention. It is a figure which shows the hardware constitutions of the information processing apparatus which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the information processing apparatus which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the execution instruction sequence analysis process which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the instruction table production | generation process classified by frequency which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the test instruction sequence production | generation process which concerns on 2nd Embodiment of this invention. It is a figure which shows the example of the appearance number used as the origin of the command appearance frequency table which concerns on 2nd Embodiment of this invention, a register related table, and a memory area related table. It is a figure which shows the example of appearance frequency normalization of the instruction appearance frequency table which concerns on 2nd Embodiment of this invention, a register related table, and a memory area related table. It is a block diagram which shows the structure of the example of a production | generation of the command table classified by frequency produced | generated from the example of appearance frequency normalization which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the production | generation example of the test instruction sequence table produced | generated from the production | generation example of the instruction table classified by frequency concerning 2nd Embodiment of this invention. It is a block diagram which shows the function structure of the information processing apparatus which concerns on 3rd Embodiment of this invention. It is a figure which shows the structure of the test instruction sequence learning database which concerns on 3rd Embodiment of this invention. It is a figure which shows the structure of the learning table which concerns on 3rd Embodiment of this invention. It is a flowchart which shows the process sequence of the information processing apparatus which concerns on 3rd Embodiment of this invention.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the constituent elements described in the following embodiments are merely examples, and are not intended to limit the technical scope of the present invention only to them.

[First Embodiment]
An information processing apparatus 100 as a first embodiment of the present invention will be described with reference to FIG. The information processing apparatus 100 is an apparatus that tests execution of an instruction sequence by a processor or the like.

  As illustrated in FIG. 1, the information processing apparatus 100 includes an appearance frequency calculation unit 101, an access target association determination unit 102, and a test instruction sequence generation unit 103. The appearance frequency calculation unit 101 calculates the appearance frequency 112 of at least two instructions before and after the predetermined instruction 111 in the execution instruction sequence generated by the compiler. The access target relation determination unit 102 determines a relation 122 between an access target of the predetermined instruction 111 and an access target of at least two preceding and following instructions in the execution instruction sequence. The test instruction sequence generation unit 103 tests a predetermined instruction for an instruction sequence including the predetermined instruction 111 and maintaining the access target relation (132, 133) based on the instruction appearance frequency 112 and the access target relation 122. The test instruction sequence 130 is generated.

  According to the present embodiment, it is possible to generate a test instruction sequence reflecting the appearance frequency of instructions executed by a compiler and the relationship of access targets, and easily ensure quality before manufacturing in designing LSIs and the like. can do.

[Second Embodiment]
Next, an information processing apparatus according to the second embodiment of the present invention will be described. The information processing apparatus according to the present embodiment reflects the relation of the access target including at least one of the register and the memory accessed by the instruction together with the appearance frequency of the instruction in the generation of the test instruction sequence. Among them, in the memory to be accessed, it is determined that there is a relationship when at least a part of the access areas overlap. In the generation of the test instruction sequence, an instruction to be used for the test instruction sequence is selected based on the appearance frequency of the instruction, and the access target between the predetermined instruction and the selected instruction is associated based on the relationship with the access target. In addition, a frequency-specific instruction table is generated in the test instruction sequence generation process. The frequency-specific instruction table includes a predetermined instruction and at least two instructions before and after the occurrence frequency of at least two instructions before and after the predetermined instruction and the relationship between an access target of the predetermined instruction and an access target of the preceding and following instructions. Are stored in the order of appearance frequency and whether or not there is an association of an access target between the predetermined instruction and the instruction string. Then, a test instruction sequence is generated with reference to the frequency-specific instruction table.

《Test instruction sequence processing system》
FIG. 2 is a block diagram illustrating a configuration of a test instruction sequence processing system 200 including the information processing apparatus 210 according to the present embodiment. FIG. 2 illustrates a case where the information processing apparatus 210 generates an execution instruction sequence from source code by a compiler, but the compiler is performed by an external device, and an execution instruction sequence group is input to the information processing apparatus 210. It may be a configuration.

  The information processing apparatus 210 generates an execution instruction sequence group from the various input source code groups using the corresponding compiler module 212. In the information processing apparatus 210, the test instruction sequence generation unit 213 analyzes the execution instruction sequence group and generates a test instruction sequence reflecting the characteristics of the execution instruction sequence. The analysis of the execution instruction string group in the test instruction string generation unit 213 analyzes the appearance frequency indicating the relation between instructions of the execution instruction string and the relation of the access target between the instructions, that is, the relation of the register and the memory area. Then, a test instruction sequence reflecting the analysis result is generated.

  The processor model 220 basically includes a CPU (Central Processing Unit) and a storage medium such as a ROM (Read Only Memory) or a RAM (Random Access Memory), and a test instruction sequence provided from the information processing apparatus 210. Is executed and the execution result is output. The processor model 220 is, for example, an integrated circuit that cannot be checked internally, such as an LSI (Large Scale Integration), and the execution result is not limited to the execution contents of instructions, but also includes generation of heat and noise. In order for the test to have the same conditions as those at the time of mounting, a test instruction sequence that more reflects the characteristics of the execution instruction sequence generated by the compiler as in this embodiment is required.

<< Functional configuration of information processing device >>
FIG. 3 is a block diagram illustrating a functional configuration of the information processing apparatus 210 according to the present embodiment. In FIG. 3, the execution instruction sequence group is generated by a compiler of an external device and input to the information processing device 210 to avoid complexity.

  The information processing apparatus 210 includes an appearance frequency calculation unit 311, an access target association determination unit 312, and a test instruction sequence generation unit 213. The appearance frequency calculation unit 311 has an instruction appearance frequency table 311a, acquires an execution instruction group, and calculates the appearance frequency. The access target association determination unit 312 includes a register association determination unit 321 and a memory area association determination unit 322. The register relation determination unit 321 has a register relation table 321a, and determines the degree of dependency that shares a register between instructions. The memory area association determination unit 322 has a memory area association table 322a, and determines the degree of dependency that shares a memory area between instructions.

  The test instruction sequence generation unit 213 includes a frequency-specific instruction table generation unit 331 and a test instruction sequence table generation unit 332. The frequency-specific instruction table generation unit 331 has a frequency-specific instruction table 331a, and generates a frequency-specific instruction table indicating the relationship between the frequency-specific (in frequency order) and the sharing of registers and memory areas. The test instruction sequence table generation unit 332 includes a test instruction sequence table 332a, and generates a test instruction sequence by referring to the frequency-specific instruction table 331a. Although not shown, the test instruction sequence table generation unit 332 accesses the predetermined instruction and the selected instruction based on the relationship between the instruction selection unit that selects an instruction used for the test instruction sequence and the access target. An access target associating unit for associating a target.

(Analysis table)
FIG. 4 is a diagram showing a configuration of the instruction code table 410, the instruction appearance frequency table 311a, the register related table 321a, and the memory area related table 322a according to the present embodiment. In FIG. 4, in consideration of ease of explanation, it is assumed that there are eight opcodes indicating the type of instruction, and OPn (n = 0 to 7). Further, an example is shown in which a test instruction sequence is created based on information of up to three instructions before and after the test target instruction. However, since the number of instructions before and after depends on the logic of the LSI, it is necessary to set the optimum number of instructions for the LSI. Further, the instruction appearance frequency table 311a, the register related table 321a, and the memory area related table 322a are used to count the number of appearances in the previous stage of analysis, and are normalized with respect to the total number of appearances of each appearance number in the subsequent stage of analysis. Used to store the appearance rate, which is the proportion that was made.

  The instruction code table 410 is a table for storing the instruction code of the test target instruction. In the figure, X, Y, Z, and D indicate instruction code fields, where X is an update register number, Y and Z are reference registers, and D is a field for designating an immediate value. For example, in the case of an instruction for loading data from a memory, the data is extracted from the memory area indicated by the memory address generated by adding the register value indicated by Y, Z and the immediate value of the D field, and indicated by X. Store the data in a register. That is, memory address = R (Y) + R (Z) + M, but for example, only one of the registers may be used with R (Y) or R (Z) set to “0”. Further, the use of the register and the memory area may be different for other instructions. The memory area indicated by the memory address differs depending on the computer architecture. When the memory address starts with 8 bytes (or 8 words), 4 bytes (4 words), 2 bytes (2 words), 1 byte (1 word) ) Etc.

  The instruction appearance frequency table 311a represents the appearance frequencies of instructions for three instructions before and after the test target instruction. B1 in the instruction appearance frequency table 311a represents an instruction position immediately before the test target instruction, B2 represents an instruction position immediately before B1, and B3 represents an instruction position immediately before B2. A1 of the instruction appearance frequency table 311a represents an instruction position immediately after the test target instruction, A2 represents an instruction position immediately after A2, and A3 represents an instruction position immediately after A2. In each frame, the appearance frequency (%) of OPn (n = 0 to 7) is stored. For example, if the number “40” is written in the OP0 column of B1, this means that the probability that the instruction OP0 is executed immediately before the test target instruction is 40%.

  The register relation table 321a represents the frequency of register dependency for three instructions before and after the test target instruction. B1, B2, B3, A1, A2, and A3 show the same contents as the instruction appearance frequency table 311a. The frequency (%) of register dependency of OPn (n = 0 to 7) is stored in each frame. For example, if the number 25 is written in the OP3 column of A1, this indicates that the register dependency between the test target instruction and the instruction OP3 immediately after that occurs at a rate of 25%. This register dependency means that a subsequent instruction refers to a register that is updated by a test target instruction, or a preceding instruction updates a register that is referred to by a test target instruction.

  The memory area association table 322a stores the frequency of memory address duplication for three instructions before and after the test target instruction. B1, B2, B3, A1, A2, and A3 show the same contents as the instruction appearance frequency table 311a. The frequency (%) of memory address duplication of OPn (n = 0 to 7) is stored in each frame. For example, if the number 18 is written in the OP5 column of B3, this indicates that the test target instruction and the address of the instruction OP5 three instructions before it overlap with each other at a frequency of 18%. This duplication of addresses indicates that a memory area that is referred to or updated by the test target instruction and a memory area that is referenced or updated by instructions before and after the test target instruction overlap at least. For example, in the case of an 8-byte access computer architecture, even when the test target instruction updates the memory address 0x00000000 to 0x00000007 and B3 OP5 refers to the memory address 0x00000006 to 0x0000000D, some areas overlap. Therefore, it is determined that there is an overlap. Even in the case of 4 bytes or 2 bytes, if some areas overlap, it is determined that they overlap.

  The frequency of the instruction appearance frequency table 311a, the register related table 321a, and the memory area related table 322a is expressed as a percentage obtained by dividing the counted number of appearances by the total number of appearances, but is not limited thereto. Further, a table for counting the number of appearances and a table for storing the appearance frequency may be provided separately.

(Instruction table by frequency)
FIG. 5 is a diagram showing a configuration of the frequency-specific instruction table 331a according to the present embodiment. In this frequency-specific instruction table 331a, in consideration of ease of explanation, there are eight opcodes representing instruction types, represented by OPn (n = 0 to 7), and the analysis range is 3 before and after the instruction to be tested. It is an instruction.

  The instruction table by frequency 331a includes an instruction table by frequency 501 for the instruction OP0, an instruction table by frequency by the instruction OP1,..., And an instruction table by frequency 50n by the instruction OPn.

  In the instruction table classified by frequency of each instruction, B1, B2, B3, A1, A2, and A3 having the same contents as the instruction appearance frequency table 311a are stored centering on each instruction. For the three instructions before and after the test target instruction, instructions from the first frequency to the third frequency are stored based on the instruction appearance frequency table 311a. The number of instructions is not limited to three from the first frequency to the third frequency. The instruction frame of each frequency stores an instruction, “R” indicating register dependency, and “M” indicating memory area dependency.

  Various conditions are conceivable as conditions for storing “R” and “M” indicating the dependency. For example, when the instructions B1, B2, B3, A1, A2, and A3 are determined, “R” is set to the instruction having the highest dependency between the test target instruction and the register, and the dependency between the test target instruction and the memory area is set. “M” may be set to the instruction having the highest degree. In this case, the degree of overlap may be added to the comparison of the dependence of the memory area. Alternatively, “R” and “M” may be stored in an instruction having a higher dependency than the average value, with the average value of the dependency in the instruction table classified by frequency of each instruction as a threshold value. Alternatively, “R” or “M” may be stored when the degree of dependence uniformly exceeds a predetermined percentage (for example, 20%).

(Test instruction sequence table)
FIG. 6 is a diagram showing a configuration of the test instruction sequence table 332a according to the present embodiment. Also in the test instruction sequence table 332a, in consideration of ease of explanation, there are eight operation codes representing instruction types, represented by OPn (n = 0 to 7), and the analysis range is 3 before and after the instruction to be tested. It is an instruction.

  In the test instruction sequence table 332a, seven instruction sequences centered on the test target instruction are arranged. In FIG. 6, OPi, OPj, OPk, and OPm are used as test target instructions, the frequency-specific instruction table 331a is referred to, and instructions having three predetermined frequency ranks are arranged. Then, the same register is accessed for the values of R (X), R (Y), R (Z), and D from the dependency relationship between the registers and memory areas between instructions, and the same (including overlapping) memory area is accessed. To write.

  Note that the instruction to be tested may be selected randomly from all the instructions of the computer or processor architecture to be tested, or the instructions may be grouped to increase the selection probability for each group. You may make a weighted selection. In addition, the selection of instruction sequences before and after the test target instruction may be selected by sequentially weighting the ratio of selecting the first frequency, second frequency, third frequency,. For example, frequency 1st is 50%, frequency 2nd is 30%. The 3rd frequency is set to 20% and so on, and is selected with this probability. Alternatively, the selection weight may be changed depending on the instruction and the instruction group.

<< Hardware configuration of information processing equipment >>
FIG. 7 is a diagram illustrating a hardware configuration of the information processing apparatus 210 according to the present embodiment.

  In FIG. 7, a CPU (Central Processing Unit) 710 is a processor for arithmetic control, and implements a functional configuration unit of the information processing apparatus 210 in FIG. 3 by executing a program. A ROM (Read Only Memory) 720 stores fixed data and programs such as initial data and programs. The communication control unit 730 communicates with other devices via a network. Note that the number of CPUs 710 is not limited to one, and may be a plurality of CPUs. The communication control unit 730 preferably includes a CPU independent of the CPU 710 and writes or reads transmission / reception data in a RAM (Random Access Memory) 740 area. It is desirable to provide a DMAC (Direct Memory Access Controller) that transfers data between the RAM 740 and the storage 750 (not shown). Further, the input / output interface 760 preferably has a CPU independent of the CPU 710 and writes or reads input / output data to / from the area of the RAM 740. Therefore, the CPU 710 recognizes that the data has been received or transferred to the RAM 740 and processes the data. Further, the CPU 710 prepares the processing result in the RAM 740 and leaves the subsequent transmission or transfer to the communication control unit 730, the DMAC, or the input / output interface 760.

  The RAM 740 is a random access memory that the CPU 710 uses as a work area for temporary storage. In the RAM 740, an area for storing data necessary for realizing the present embodiment is secured. The source code group 741 is a source code group acquired when the information processing apparatus 210 compiles. The execution instruction sequence group 742 is an execution instruction sequence group generated by compiling the source code group 741 by the compiler module group 759 of the information processing apparatus 210 or being compiled and input by an external apparatus. The test target instruction 743 is an instruction to be a test target for analyzing the appearance frequency. The instruction appearance frequency table 311a is a table for analyzing the appearance frequency of the instruction shown in FIG. The register-related table 321a is a table for analyzing the register dependency between instructions shown in FIG. The memory area related table 322a is a table for analyzing the dependency relation of the memory area between the instructions shown in FIG. The frequency-specific instruction table 331a is a table directly used for test instruction sequence generation in which the dependency relationship between the preceding and following instructions and their registers and memory areas is analyzed in the order shown in FIG. The test instruction sequence table 332a is a table of test instruction sequences generated based on the frequency-specific instruction table 331a. The input / output data 744 is data input / output by the input / output device via the input / output interface 760. Transmission / reception data 745 is data transmitted / received via the communication control unit 730.

  The storage 750 stores a database, various parameters, or the following data or programs necessary for realizing the present embodiment. The related command selection threshold 751 is a threshold value serving as a reference for selecting as a related command. The related register determination threshold 752 is a threshold serving as a reference for determining that there is a dependency relationship between registers. The related memory area determination threshold 753 is a threshold serving as a reference for determining that there is a dependency relationship in the memory area. The test instruction sequence generation algorithm 754 is an algorithm for generating a test instruction sequence in the present embodiment.

  The storage 750 stores the following programs. The information processing device control program 755 is a program that controls the entire information processing device 210. The execution instruction sequence analysis module 756 is a module that analyzes the appearance frequency of instructions from the execution instruction sequence group and the relationship (dependency relationship) between registers and memory areas. The frequency-specific instruction table generation module 757 refers to the instruction appearance frequency table 311a, the register-related table 321a, and the memory area-related table 322a as a result of analysis by the execution instruction sequence analysis module 756, and generates the frequency-specific instruction table 331a. This is the module to generate. The test instruction sequence generation module 758 is a module that generates the test instruction sequence table 332a with reference to the frequency-specific instruction table 331a. The compiler module group 759 is a module group when the information processing apparatus compiles.

  The input / output interface 760 interfaces input / output data with input / output devices. A display unit 561 and an operation unit 562 are connected to the input / output interface 760. The input / output interface 760 is connected to an RW (read / write) unit of the storage medium. If necessary, a voice input / output unit, a GPS (Global Positioning System) position determination unit, or the like may be connected.

  Note that the RAM 740 and storage 750 in FIG. 7 do not show programs and data related to general-purpose functions and other realizable functions of the information processing apparatus 210.

<< Processing procedure of information processing device >>
FIG. 8 is a flowchart illustrating a processing procedure of the information processing apparatus 210 according to the present embodiment. This flowchart is executed by the CPU 710 in FIG. 7 using the RAM 740, and implements the functional configuration unit in FIG.

  In step S801, the information processing apparatus 210 generates an execution instruction sequence group from a source code group as an option by a compiler group. When the information processing apparatus 210 does not compile, an execution instruction string group is acquired from an external apparatus. In step S803, the information processing apparatus 210 executes an execution instruction sequence analysis process. In step S805, the information processing apparatus 210 normalizes the appearance table in which the number of appearances is tabulated with the appearance rate. In step S <b> 807, the information processing apparatus 210 refers to the appearance table normalized by the appearance rate and executes a frequency-specific instruction table generation process. In step S809, the information processing apparatus 210 refers to the frequency-specific instruction table and executes a test instruction sequence generation process.

(Execution instruction sequence analysis processing)
FIG. 9A is a flowchart showing the procedure of the execution instruction sequence analysis process (S803) according to the present embodiment.

  In step S911, the information processing apparatus 210 reads the load module output by the compiler and searches for the head of the instruction sequence. In step S913, the information processing apparatus 210 reads the first instruction in the instruction sequence. In step 915, the information processing apparatus 210 determines whether the instruction is the current test target instruction. If it is not the current test target instruction, the process returns to step S913 to read the next instruction and confirm again whether it is the test target instruction. If it is a test target instruction, the information processing apparatus 210 proceeds to step S917, determines the X, Y, Z, and D fields of the test target instruction and writes them in the instruction code table 410.

  In step S919, the information processing apparatus 210 reads the instruction immediately before the test target instruction, refers to the operation code, and counts “+1” in the corresponding column of the B1 line of the instruction appearance frequency table 311a. Subsequently, the X field is referred to and compared with R (Y) and R (Z) in the instruction code table 410 to confirm whether they match. If they match, the corresponding opcode column in the B1 row of the register relation table 321a is counted as “+1”. Further, when the test target instruction is a memory access instruction and the immediately preceding instruction is also a memory access instruction, a memory address is generated from each of the Y, Z, and D fields. Then, it is checked whether or not the access areas are duplicated. If they are duplicated, the corresponding column of the B1 row of the memory area relation table 322a is counted as “+1”.

  In step S921, the information processing apparatus 210 reads the instruction immediately before the test target instruction, refers to the operation code, and counts “+1” in the corresponding column in the B2 line of the instruction appearance frequency table 311a. Subsequently, the X field is referred to and compared with R (Y) and R (Z) in the instruction code table 410 to confirm whether they match. If they match, “+1” is counted in the corresponding opcode column in the B2 line of the register relation table 321a. Further, if the test target instruction is a memory access instruction and the previous instruction is also a memory access instruction, memory addresses are generated from the Y, Z, and D fields, respectively. Then, it is checked whether or not the access areas are duplicated. If they are duplicated, the corresponding column of the B2 line of the memory area relation table 322a is counted as “+1”.

  In step S923, the information processing apparatus 210 reads the instruction three instructions before the test target instruction, refers to the operation code, and counts “+1” in the corresponding column in the B3 line of the instruction appearance frequency table 311a. Subsequently, the X field is referred to and compared with R (Y) and R (Z) in the instruction code table 410 to confirm whether they match. If they match, “+1” is counted in the corresponding opcode column in line B3 of the register relation table 321a. Further, if the test target instruction is a memory access instruction and the previous instruction is also a memory access instruction, memory addresses are generated from the Y, Z, and D fields, respectively. Then, it is checked whether or not the access areas are duplicated. If they are duplicated, the corresponding column of the B3 line of the memory area relation table 322a is counted as “+1”.

  In step S925, the information processing apparatus 210 reads the instruction immediately after the test target instruction, refers to the operation code, and counts “+1” in the corresponding column of the A1 line of the instruction appearance frequency table 311a. Subsequently, the X field is referred to and compared with R (Y) and R (Z) in the instruction code table 410 to confirm whether they match. If they match, the corresponding opcode column in the A1 line of the register relation table 321a is counted as “+1”. Further, if the test target instruction is a memory access instruction and the previous instruction is also a memory access instruction, memory addresses are generated from the Y, Z, and D fields, respectively. Then, it is checked whether or not the access areas are duplicated. If they are duplicated, the corresponding column in the A1 line of the memory area relation table 322a is counted as “+1”.

  In step S927, the information processing apparatus 210 reads the instruction after the test target instruction, refers to the operation code, and counts “+1” in the corresponding column in the A2 line of the instruction appearance frequency table 311a. Subsequently, the X field is referred to and compared with R (Y) and R (Z) in the instruction code table 410 to confirm whether they match. If they match, the corresponding opcode column in the A2 line of the register relation table 321a is counted as “+1”. Further, if the test target instruction is a memory access instruction and the previous instruction is also a memory access instruction, memory addresses are generated from the Y, Z, and D fields, respectively. Then, it is checked whether or not the access areas are duplicated. If they are duplicated, the corresponding column in the A2 line of the memory area relation table 322a is counted as “+1”.

  In step S929, the information processing apparatus 210 reads the instruction three times after the test target instruction, refers to the operation code, and counts “+1” in the corresponding column in the A3 line of the instruction appearance frequency table 311a. Subsequently, the X field is referred to and compared with R (Y) and R (Z) in the instruction code table 410 to confirm whether they match. If they match, the corresponding opcode column in the A3 line of the register relation table 321a is counted as “+1”. Further, if the test target instruction is a memory access instruction and the previous instruction is also a memory access instruction, memory addresses are generated from the Y, Z, and D fields, respectively. Then, it is checked whether or not the access areas are duplicated. If they are duplicated, the corresponding column of the A3 line of the memory area relation table 322a is counted as “+1”.

  In step S931, the information processing apparatus 210 determines whether or not the instruction sequence of the load module output by the compiler is the last one. If not, the information processing apparatus 210 returns to step S913, reads the next instruction, and performs the above-described steps S915 to S929. Perform the action. If it is the last instruction, the information processing apparatus 210 performs n = n + 1 in step S933. If n ≦ 7 in step S935, the process returns to step S913 to read the next instruction, and the above-described steps S915 to S915 are performed. The operation of S929 is performed. If n = 8, a series of processing ends here.

(Instruction table generation by frequency)
FIG. 9B is a flowchart showing the procedure of the frequency-specific instruction table generation process (S807) according to the present embodiment.

  In step S941, the information processing apparatus 210 acquires the command appearance frequency table 311a normalized by the appearance rate. In step S943, the information processing apparatus 210 stores a predetermined number of commands in the frequency-specific command table 331a in the order of appearance frequency. In this example, the number is not limited as long as it is ranked first to third frequency.

  In step S945, the information processing apparatus 210 selects one instruction from the instructions stored in the frequency-specific instruction table 331a. In step S947, the information processing apparatus 210 refers to the register relation table 321a and determines whether or not there is a relation between the register to be used between the test target instruction and the selected instruction. When there is a relation between the register used between the test target instruction and the selected instruction, the information processing apparatus 210 writes “R” in the selected instruction of the instruction table by frequency in step S949. In step S951, the information processing apparatus 210 refers to the memory area association table 322a and determines whether there is a relation between the memory area to be accessed between the test target instruction and the selected instruction. If there is a relationship between the memory area to be accessed between the test target instruction and the selected instruction, the information processing apparatus 210 writes “M” in the selected instruction in the instruction table by frequency in step S953. As described in the explanation of the frequency-specific instruction table 331a in FIG. 5, there are various criteria for determining whether the register is related to the used register or the memory area. Standards are used.

  In step S955, the information processing apparatus 210 determines whether or not the processing of all instructions stored in the frequency-specific instruction table 331a has been completed. If processing of all instructions has not been completed, the information processing apparatus 210 returns to step S945 and repeats processing for other instructions stored in the frequency-specific instruction table 331a. If all the instructions have been processed, the process in step S807 ends.

(Test instruction sequence generation processing)
FIG. 9C is a flowchart showing the procedure of the test instruction sequence generation process (S809) according to the present embodiment.

  In step S961, the information processing apparatus 210 selects a test target instruction. In step S963, the information processing apparatus 210 reads the instruction table 331a according to frequency of the test target instruction (501 to 50n in FIG. 5). In step S965, the information processing apparatus 210 selects the preceding and following instruction sequences having the same frequency order and stores them in the test instruction sequence table 332a. Note that the test target instruction in step S961 may be selected at random, or may be selected with weights such as grouping instructions to increase the selection probability for each group. Further, the selection of the frequency rank in step S965 may be performed by weighting the ratio of selecting the frequency first, frequency second, frequency third,... In order, or by the instruction, by the instruction group. The weight may be changed.

  In step S967, the information processing apparatus 210 selects one instruction from the instructions stored in the test instruction sequence table 332a. In step S969, the information processing apparatus 210 determines whether “R” is stored in the selection instruction. If “R” is stored in the selected instruction, the information processing apparatus 210 associates a corresponding register between the test target instruction and the selected instruction in step S971. In step S973, the information processing apparatus 210 determines whether “M” is stored in the selection instruction. If “M” is stored in the selected instruction, the information processing apparatus 210 associates a corresponding memory address between the test target instruction and the selected instruction in step S975.

  In step S977, the information processing apparatus 210 determines whether or not the processing of the test instruction sequence of one test target instruction has been completed. If the processing of the test instruction sequence of one test target instruction has not been completed, the information processing apparatus 210 returns to step S957 and repeats the processing of other instructions in the test instruction sequence.

  When the processing of the test instruction sequence of one test target instruction is completed, the information processing apparatus 210 determines whether there is another test target instruction in step S979. If there is another test target instruction, the information processing apparatus 210 returns to step S961 and repeats the process of generating a test instruction sequence from the other test target instruction. If there is no other test target instruction, the test instruction sequence generation process is terminated.

<< Specific example of test instruction sequence generation >>
Hereinafter, a procedure for generating a test instruction sequence in a specific example will be described in detail with reference to FIGS. In addition, the example of FIG. 10A-FIG. 12 is an example, Comprising: It is not limited to this.

(Number of occurrences)
FIG. 10A is a view showing appearance number examples 1011, 1021 and 1022 which are the basis of the instruction appearance frequency table 1011a, the register related table 1021a and the memory area related table 1022a according to the present embodiment. The instruction appearance frequency table 1011a, the register related table 1021a, and the memory area related table 1022a can store the appearance number examples 1011, 1021, and 1022, and then can store the calculated appearance frequencies.

  Examples of appearance numbers 1011, 1021 and 1022 are generated by the instruction appearance frequency table 1011a, the register related table 1021a and the memory area related table 1022a when OP0 is generated according to the execution instruction sequence analysis process of FIG. It is an example of the frequency | count of appearance counted in each frame.

  Although not shown in FIG. 10A, the number of appearances using other instructions (OP1 to OP7 in this example) as test target instructions is also counted.

(Appearance frequency normalization example)
FIG. 10B is a diagram showing an example of appearance frequency normalization of the instruction appearance frequency table 1011a, the register related table 1021a, and the memory area related table 1022a according to the present embodiment. Note that the appearance frequency in FIG. 10B is expressed as a rounded percentage of the total number of appearances, but the method of calculating the appearance frequency is not limited to this.

  In FIG. 10A, the number of appearances is stored in the instruction appearance frequency table 1011a, the register related table 1021a, and the memory area related table 1022a. I can't compare. The appearance frequency normalization example in FIG. 10B is obtained by normalizing the appearance frequency (%), the dependency ratio (%), and the duplication ratio (%) to clarify the weights of the numbers. For example, in the case of the B3 row of the instruction appearance frequency table 1011a, the ratio to the total instructions can be obtained by dividing the values of OP0 to OP7 by the sum of the B3 rows. As for the register related table 1021a and the memory area related table 1022a, the total is obtained from the instruction appearance frequency table 1011a, whereby the ratio to the total number of instructions is obtained.

  The instruction frequency table 1011a, the register relation table 1021a, and the memory area relation table 1022a in FIG. 10B are obtained by normalizing the appearance number examples 1011, 1021, and 1022 in FIG. 10A by the above-described method. For example, the most frequently occurring instruction as the instruction immediately before OP0 is OP7, which accounts for 56% of the total number of instructions appearing as the instruction immediately preceding OP0. The higher order is OP5 which accounts for 20%.

(Example of command table generation by frequency)
FIG. 11 is a diagram showing a configuration of a generation example of the frequency-specific instruction table 1131a generated from the appearance frequency normalization example according to the present embodiment. The frequency-specific instruction table 1131a is a table in which information necessary for assembling a test instruction sequence is compiled, and the test instruction sequence generation unit assembles a test instruction sequence based on the information in this table. The frequency-specific instruction table 1131a has a frequency-specific instruction table 1101 where OP0 is a test target instruction, OP1 is a frequency-specific instruction table 1102 where OP1 is a test target instruction,.

  A specific way of viewing the frequency-specific instruction table 1131a will be described. For example, when testing an OP0 instruction, the test instruction sequence that should be the highest in frequency is ranked first in frequency, and the instruction sequence that increases the frequency second or third is ranked second in frequency and third in frequency. The instruction sequence with the highest frequency is OP7 immediately before OP0, OP5 before it, and OP3 before it, and OP6 immediately after OP0, OP4 next, and OP2 next. Here, the dependency relationship between the registers and the presence or absence of duplication of memory addresses are further determined and held. In this specific example, if the instructions B1, B2, B3, A1, A2, and A3 are determined to set “R” and “M”, the dependency between the test target instruction and the register is 15%. A method is adopted in which “R” is set for the highest instruction and “M” is set for the highest instruction when the dependency between the test target instruction and the memory area is 15% or more. Explaining the first place in frequency, the register dependency is the OP7 immediately before OP0 and the OP4 instruction that is two after OP0, and the memory address is duplicated in OP5 two before OP0. Become. In this example, the first frequency to the third frequency are described, but how many of these are taken into consideration depends on the architecture of the computer, the evaluation period, and the like.

(Example of test instruction sequence table generation)
FIG. 12 is a diagram showing a configuration of a generation example of the test instruction sequence table 1232a generated from the generation example of the frequency-specific instruction table according to the present embodiment. The test instruction sequence includes a regular instruction sequence and a random instruction sequence. By applying the above table to various generation methods, a test instruction sequence with a high bug extraction effect can be generated. A method of using the frequency-specific instruction table 1131a when randomly generating an instruction sequence will be described.

  In general, the number of instructions is given as an input as a parameter when generating a test instruction sequence. This is a parameter that determines how many instructions in the test instruction sequence are to be used, but in order to simplify the explanation, 30 instructions are used here. In general, a case where there are hundreds to tens of thousands of instructions is also conceivable.

  Next, the operation code is extracted at random based on the number of instructions. There is a method of extracting this opcode at random. Also, divided into memory access system instruction group, fixed-point operation instruction group, floating-point operation instruction group, etc., specify the weight of these groups, the higher this weight, the higher the appearance frequency, There are ways to include rules. Here, description will be made by a method of extracting completely at random. In addition, the frequency is used by 50% for the first frequency and 30% for the second frequency, in common with the frequency-specific instruction tables 1101 to 1108. The 3rd frequency is set to 20% or the like and is selected with this probability. In this example, when OP0 is extracted at the first frequency, second frequency, and third frequency in the frequency-specific instruction tables 1101 to 1108 in FIG. 11, the first frequency is selected with a probability of 50%, and OP1 Suppose that frequency 2 is selected with a probability of 30% when is extracted, and frequency 3 is selected with a probability of 20% when OP7 is extracted.

  OP0 is extracted as the first instruction, and the instruction sequence with the highest frequency is selected from numbers 1 to 7 from the instruction table 1101 by frequency. The opcode is generated according to the instruction sequence of the frequency-specific instruction table 1101. From the dependency of R (X), R (Y), R (Z), R (X) of OP7 of number 3 and OP0 of number 4 Match the number of R (Y) or R (Z). Further, R (X) or R (Y) of OP4 of number 4 and the number of R (X) or R (Y) of OP4 of number 6 are matched. In order to overlap the memory address, R (Y), R (Z) and D of OP4 of number 4 are made to coincide with R (Y), R (Z) and D of OP5 of number 2. Random numbers are set in the R (X), R (Y), R (Z), and D fields of other instructions. As a result, a test instruction sequence 1201 is generated.

  When OP1 is extracted as the second instruction, an instruction string with the second highest frequency is selected from numbers 8 to 14 from the instruction table 1102 by frequency. The operation code is generated according to the instruction sequence of the frequency-specific instruction table 1102, and from the dependency relationship of R (X), R (Y), and R (Z), R (X) of OP0 of number 8 and OP1 of number 11 The numbers of R (Y) are matched, and further, the R (X) of OP1 of number 11 is matched with the R (Y) number of OP5 of number 14. In order to overlap the memory address, R (Z) and D of OP1 of number 11 are made to coincide with R (Z) and D of OP5 of number 14. Random numbers are set in the R (X), R (Y), R (Z), and D fields of other instructions. As a result, a test instruction sequence 1202 is generated.

  When OP7 is extracted as the third instruction, the instruction sequence having the third highest frequency is selected from numbers 15 to 21 from the frequency-specific instruction table 1108. The opcode is generated according to the instruction sequence of the frequency-specific instruction table 1108. From the dependency relationship of R (X), R (Y), R (Z), R (X) of OP1 of number 17 and OP7 of number 18 The numbers of R (Y) are matched. Random numbers are set in the R (X), R (Y), R (Z), and D fields of other instructions. As a result, a test instruction sequence 1203 is generated.

  When OP0 is extracted again as the fourth instruction, the instruction sequence with the third highest frequency is selected from numbers 22 to 28 from the frequency-specific instruction table 1101. The opcode is generated in accordance with the instruction sequence from the frequency-specific instruction table 1101. From the dependency of R (X), R (Y), R (Z), R (X) of OP6 of number 23 and OP0 of number 25 The numbers of R (Y) are matched. Random numbers are set in the R (X), R (Y), R (Z), and D fields of other instructions. As a result, a test instruction sequence 1204 is generated.

  In the above example, in order to avoid complications, there is a dependency relationship between registers, which register has a dependency relationship in the memory region dependency relationship, or a relationship between each register when there is a memory region dependency relationship, etc. Omitted. In practice, it may be used which register is matched or the frequency of dependency between registers is obtained and the result is related to which register. In addition, in the present example, the same value is set for R (Y) and R (Z), although it may be taken into consideration which register has a dependency relationship in the memory region dependency relationship.

  As a result, the test instruction sequence shown in FIG. 12 is generated. Unlike the normal random instruction sequence, the test instruction sequence generated in this example is generated from statistical information obtained by analyzing the load module output from the compiler. In addition, instruction order, register dependency, and memory address duplication reflect the tendency of execution instruction sequences that actually run on the OS, and are extremely effective in terms of quality assurance prior to LSI release. This is a test instruction sequence.

  According to the present embodiment, it is possible to generate a test instruction sequence that reflects the appearance frequency of the instruction that is the characteristic of the execution instruction sequence generated by the compiler and the relationship between the register to be accessed and the memory area. Quality can be ensured before production.

  In other words, using a tool that analyzes the execution module output by the compiler, it is possible to generate a test instruction sequence that takes into consideration the opcodes of the preceding and succeeding instructions with respect to the instruction to be tested, whether there are register dependencies, and whether addresses are duplicated . Therefore, since the logic evaluation can be performed with the test instruction sequence having the same tendency as the actual JOB before the LSI release, the LSI quality can be improved and the delay of the development schedule accompanying the LSI rework and the rework can be prevented. .

[Third Embodiment]
Next, an information processing apparatus according to the third embodiment of the present invention will be described. The information processing apparatus according to the present embodiment is different from the second embodiment in that the generation history of a test instruction sequence is accumulated and learning is performed to generate the next test instruction sequence. Since other configurations and operations are the same as those of the second embodiment, the same configurations and operations are denoted by the same reference numerals, and detailed description thereof is omitted.

<< Functional configuration of information processing device >>
FIG. 13 is a block diagram illustrating a functional configuration of the information processing apparatus 1310 according to the present embodiment. In FIG. 13, the same functional components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The information processing apparatus 1310 includes a test instruction sequence learning database 1314, a test instruction execution instruction unit 1315, a test instruction sequence execution result acquisition unit 1316, and a test instruction sequence generation condition update unit 1317.

  The test instruction sequence learning database 1314 stores the test instruction sequence generated by the test instruction sequence generation unit 213 and instructed to be executed by the test target processor, and the test instruction sequence execution result acquired from the test target processor in association with each other. . The test instruction execution instruction unit 1315 instructs the test target processor to execute the test instruction sequence generated by the test instruction sequence generation unit 213. The test instruction sequence execution result acquisition unit 1316 acquires the execution result of the test instruction sequence in the test target processor. The execution result of the test instruction sequence may be acquired directly from the test target processor, or may be acquired from another test execution evaluation device or the like.

  The test instruction sequence generation condition updating unit 1317 has a learning table 1317a. The test instruction sequence generation unit 213 refers to the test instruction sequence and the execution result stored in the test instruction sequence learning database 1314, and the test instruction sequence generation unit 213 determines the test instruction sequence. The conditions for generating are updated to further improve the quality of the processor under test.

(Test instruction sequence learning database)
FIG. 14 is a diagram showing a configuration of the test instruction sequence learning database 1314 according to the present embodiment.

  The test instruction sequence learning database 1314 is associated with the test instruction sequence 1401 generated by the test instruction sequence generation unit 213 and is based on the frequency-based instruction table 1402, instruction appearance frequency table 1403, access target related information 1404, test The instruction sequence execution result 1405 is stored. Then, a test instruction sequence evaluation result 1406 based on these pieces of information is stored. The access target related information 1404 includes a register related table and a memory area related table.

(Learning table)
FIG. 15 is a diagram showing a configuration of the learning table 1317a according to the present embodiment. The learning table 1317a is used to update the test instruction sequence generation condition by the test instruction sequence generation unit 213 based on the test instruction sequence history accumulated in the test instruction sequence learning database 1314.

  The learning table 1317a stores the test instruction sequence evaluation result 1502 and the updated test instruction sequence update condition 1503 in association with the test instruction sequence generation condition 1501. The test instruction sequence generation condition 1501 includes a related instruction selection threshold, a related register determination threshold, a related memory area determination threshold, a test instruction sequence generation algorithm, and the like.

<< Processing procedure of information processing device >>
FIG. 16 is a flowchart showing a processing procedure of the information processing apparatus 1310 according to this embodiment. This flowchart is executed by the CPU 710 in FIG. 7 using the RAM 740, and implements the functional configuration unit in FIG. In FIG. 16, steps similar to those in FIG. 8 are denoted by the same step numbers, and description thereof is omitted.

  In step S <b> 1611, the information processing apparatus 1310 instructs execution of the test instruction sequence on the test target processor. In step S1613, the information processing apparatus 1310 acquires the execution result of the test instruction sequence. In step S1615, the information processing apparatus 1310 refers to the history of the test instruction sequence stored in the test instruction sequence learning database 1314 and analyzes the execution result. In step S <b> 1617, the information processing apparatus 1310 uses the learning table 1317 a to update the test instruction sequence generation conditions by the test instruction sequence generation unit 213.

  According to the present embodiment, it is possible to update the conditions for generating the test instruction sequence and further improve the quality of the test target processor.

[Other Embodiments]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, a system or an apparatus in which different features included in each embodiment are combined in any way is also included in the scope of the present invention.

  In addition, the present invention may be applied to a system composed of a plurality of devices, or may be applied to a single device. Furthermore, the present invention can also be applied to a case where an information processing program that implements the functions of the embodiments is supplied directly or remotely to a system or apparatus. Therefore, in order to realize the functions of the present invention on a computer, a program installed in the computer, a medium storing the program, and a WWW (World Wide Web) server that downloads the program are also included in the scope of the present invention. . In particular, at least a non-transitory computer readable medium storing a program for causing a computer to execute the processing steps included in the above-described embodiments is included in the scope of the present invention.

[Other expressions of embodiment]
A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
Appearance frequency calculating means for calculating the appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determining unit that determines a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
Test instruction sequence generation means for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
An information processing apparatus comprising:
(Appendix 2)
The information processing apparatus according to appendix 1, wherein the access target includes at least one of a register and a memory accessed by the instruction.
(Appendix 3)
The information processing apparatus according to appendix 2, wherein the access target memory is determined to be relevant when at least a part of access areas overlap.
(Appendix 4)
The test instruction sequence generation means includes:
Instruction selection means for selecting an instruction to be used for the test instruction sequence based on the appearance frequency of the instruction;
An access target associating means for associating an access target between the predetermined instruction and the selected instruction based on the relation with the access target;
The information processing apparatus according to any one of appendices 1 to 3, further comprising:
(Appendix 5)
The test instruction sequence generation means includes:
Based on the appearance frequency of at least two instructions before and after the predetermined instruction and the relationship between the access target of the predetermined instruction and the access target of the instruction before and after the predetermined instruction, the predetermined instruction and at least 2 before and after the predetermined instruction A frequency-specific instruction table generating means for generating a frequency-specific instruction table for storing an instruction sequence in the order of appearance frequency of one instruction and whether or not the access target is related between the predetermined instruction and the instruction sequence; Prepared,
The information processing apparatus according to any one of appendices 1 to 4, wherein the test instruction sequence is generated with reference to the instruction table classified by frequency.
(Appendix 6)
Execution instruction means for causing a processor to execute the generated test instruction sequence;
Execution result acquisition means for acquiring an execution result by the processor of the test instruction sequence;
Further comprising
The information processing apparatus according to any one of appendices 1 to 5, wherein the test instruction sequence generation unit evaluates the execution result and reflects the result in the generation of the test instruction sequence.
(Appendix 7)
An appearance frequency calculating step for calculating an appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determination step for determining a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
A test instruction sequence generation step for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
An information processing method including:
(Appendix 8)
An appearance frequency calculating step for calculating an appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determination step for determining a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
A test instruction sequence generation step for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
An information processing program that causes a computer to execute.

Claims (8)

Appearance frequency calculating means for calculating the appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determining unit that determines a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
Test instruction sequence generation means for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
An information processing apparatus comprising:   The information processing apparatus according to claim 1, wherein the access target includes at least one of a register and a memory accessed by the instruction.   The information processing apparatus according to claim 2, wherein the memory to be accessed is determined to be relevant when at least part of access areas overlap. The test instruction sequence generation means includes:
Instruction selection means for selecting an instruction to be used for the test instruction sequence based on the appearance frequency of the instruction;
An access target associating means for associating an access target between the predetermined instruction and the selected instruction based on the relation with the access target;
The information processing apparatus according to claim 1, further comprising: The test instruction sequence generation means includes:
Based on the appearance frequency of at least two instructions before and after the predetermined instruction and the relationship between the access target of the predetermined instruction and the access target of the instruction before and after the predetermined instruction, the predetermined instruction and at least 2 before and after the predetermined instruction A frequency-specific instruction table generating means for generating a frequency-specific instruction table for storing an instruction sequence in the order of appearance frequency of one instruction and whether or not the access target is related between the predetermined instruction and the instruction sequence; Prepared,
The information processing apparatus according to claim 1, wherein the test instruction sequence is generated with reference to the instruction table classified by frequency. Execution instruction means for causing a processor to execute the generated test instruction sequence;
Execution result acquisition means for acquiring an execution result by the processor of the test instruction sequence;
Further comprising
The information processing apparatus according to claim 1, wherein the test instruction sequence generation unit evaluates the execution result and reflects the result in generation of the test instruction sequence. An appearance frequency calculating means for calculating an appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determining unit that determines a relation between an access target of the predetermined instruction and an access target of the at least two preceding and following instructions in the execution instruction sequence;
A test instruction sequence generation means uses, as a test instruction sequence for testing the predetermined instruction, an instruction sequence including the predetermined instruction and maintaining the association of the access target, based on the appearance frequency of the instruction and the relationship of the access target A test instruction sequence generation step to be generated;
An information processing method for an information processing apparatus including: An appearance frequency calculating step for calculating an appearance frequency of at least two instructions before and after a predetermined instruction in the execution instruction sequence generated by the compiler;
An access target relation determination step for determining a relation between an access target of the predetermined instruction and an access target of the at least two instructions before and after the execution instruction sequence;
A test instruction sequence generation step for generating an instruction sequence including the predetermined instruction and maintaining the access target relationship as a test instruction sequence for testing the predetermined instruction based on the appearance frequency of the instruction and the relationship of the access target When,
An information processing program that causes a computer to execute.

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