JP3092408B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a column and a SAM which are provided with a random access memory and a serial access memory (hereinafter referred to as SAM) and which are effective when an image memory for storing image information is used. The present invention relates to a semiconductor memory having a selection circuit and a redundancy repair circuit.

[0002]

2. Description of the Related Art A semiconductor memory has a plurality of bits of data I / I.
It has an O terminal, and the wider the I / O data width, the larger the number of bits that can be read / written in a single access, thus enabling high-speed data access. Therefore, I
A / O data width of about 8 to 19 bits has been put to practical use, and it is expected that the data width will be further increased. Therefore, the semiconductor memory has a configuration in which the memory cell array is accessed with data having a plurality of bit widths (hereinafter, referred to as words).

The column and S in a conventional image memory
FIG. 13 shows the configuration of the AM-based selection circuit. 1 is a memory cell array for storing data, 2 is a redundant cell array for redundancy relief, 3 is a serial register for storing any one row of data in a memory cell array 1 having a plurality of registers R, and 32 is a register R. This is a redundant serial register for storing data of an arbitrary row of the redundant cell array 2 provided with a plurality.

Reference numeral 28 denotes a column decoder for generating a selection signal for selecting an arbitrary row data of the memory cell array 1, and 25 denotes a column signal for selectively selecting bit line data of the memory cell array 1 by a selection signal from the column decoder 28. The column selection gate 26 connected to the bus 18
The data on the bit lines of the redundant cell array 2 is selectively selected by a signal from the column redundant decoder 27.
8, a redundant column selection gate.

Reference numeral 9 denotes a SAM decoder for generating a selection signal for selecting arbitrary data in the serial register 3;
Selects a signal stored in the serial register 3 in response to a selection signal from the SAM decoder 9 and selectively outputs the signal to the SAM data bus 2.
This is a SAM selection gate that outputs 0.

Reference numeral 30 denotes a column predecoder for generating an address to be given to a column decoder 28 from a column address input signal 31; 27, a column redundancy decoder for detecting a column address input 31 corresponding to a defective memory cell in the memory cell array 1; An address control circuit that controls the supply of addresses to the column decoder 28 based on the output of the column redundancy decoder 27.

[0007] 13 is a SAM address input signal 17 to S
A SAM pre-decoder 14 generates an address to be given to the AM decoder 9. A SAM pre-decoder 14 detects a SAM address input 17 corresponding to a defective memory cell in the memory cell array 1.
The redundant decoder 29 selects SAM data from the SAM data bus 20 or the redundant serial
This is a SAM data selection circuit that outputs data 19.

In FIG. 1, the bit width of the column data bus 18, the SAM data 19 and the SAM data bus 20 is 2 bits, and the size of the redundant cell array 2 is 2 columns (the rescue address is 1 column).

[0011] The column-related data access will be described.
It is supplied to the column redundancy decoder 27 together with 0. The output of the column predecoder 30 is applied to the column decoder 28 via the address control circuit 12,
The column selection gate 5 is driven by the selection signal output of 8 to select any data in the memory cell array 1 and connected to the column data bus 18.

When a defective memory cell exists in the memory cell array 1 and a column address signal 31 corresponding to the defective memory cell is input, the column redundancy decoder 2
7, the redundant address is detected, and the output of the column redundant decoder 27 becomes "1". Address control circuit 12
Block the address signal to the column decoder 28 by the output signal of the redundant decoder 27, select the redundant memory cell by the redundant column selection gate 26 connected to the redundant cell array 2, and connect it to the column data bus 18.

Since high-speed performance is required in SAM data access, the redundant serial register 32 is generally accessed at all times. The SAM address signal 17 is supplied to the SAM redundancy decoder 14 together with the SAM predecoder 13. SAM output of the pre-decoder 13 is found given to the SAM decoder 9 is connected to drive the SAM selection gate 7 by selecting the output signal of the SAM decoder 9 to any bit select SAM data bus 20 of the serial register 3.

When the SAM address 17 corresponding to the defective column address is input, the SAM redundancy decoder 1
4, the redundant address is detected, and the output of the redundant decoder 14 becomes "1". With this signal, the SAM data selecting circuit 29 selects the data of the redundant serial register 32 and outputs it to the SAM data 19. With such a configuration, the critical path at the time of SAM access is shortened, and high-speed SAM access is realized.

In the figure, the column data bus 18 and the SAM data bus 20 are 2 bits and access is made in units of 2 bits.
The M decoder 9 generates a selection signal in units of 2 bits, and an address for accessing the column address 31 and the SAM address 17 in units of 2 bits is input.

FIG. 14 shows an image data arrangement when the semiconductor memory shown in FIG. 13 is applied to an image memory for storing image data. In the configuration shown in FIG. 13, since the unit of word data is 2 bits, the position of the image data accessed by the input address is specified at a two-pixel pitch as indicated by the symbol a.
In image processing in the image processing system, a code b
The image data access in pixel units as shown in FIG.

Therefore, there has been proposed a semiconductor memory having a function (hereinafter, referred to as a pixel alignment access function) capable of accessing word data by position designation in bit units.

FIG. 15 is a configuration diagram of a column selection circuit for realizing a pixel alignment access function. As the column address signal 16, an address having a bit width necessary for specifying a position in bit units is input.

Reference numeral 8 denotes a column decoder for generating a column selection signal in bit units in accordance with the column address input 16, and reference numeral 10 denotes a column predecoder for generating an address given from the column address input 16 to the column decoder 8. 1 is a memory cell array for storing data, and 4
Reference numeral 1 denotes a column selection gate for selectively connecting bit line data of the memory cell array 1 to a column data bus 18 according to a selection signal from the column decoder 8.

In FIG. 15, a column selection gate 41 is
Each of the bit lines of the memory cell array 1 is provided with two transfer gates, each of which is connected to a different column data bus, so that the column decoder 8 can simultaneously select transfer gates connected to adjacent bit lines. Are supplied.

According to the selection signal from the column decoder 8,
Since two consecutive bits are always selected, FIG. 14 (2)
The access by specifying the position in bit units as shown in FIG.

13 to 15, the column data bus 18 and the SAM data bus 20 have 2 bits,
Although a configuration in which 2-bit word data access is performed on the memory cell array 1 is shown, a column data bus 18 and a SAM data bus 20 may have a required bit width in order to access the memory cell array 1 with word data of 3 bits or more. , Column decoder 28 and SAM in FIG.
The decoder 9 is configured to generate a selection signal in a required bit width unit, and the column selection gate 4 shown in FIG.
In 1, the number of transfer gates connected to each bit line is set to the required bit width, and the connection according to the required bit width is performed, whereby the same operation as in the case of 2 bits can be realized.

[0021]

As described above,
When a semiconductor memory is applied to an image memory, a configuration for realizing a pixel alignment access function has been proposed for the purpose of speeding up image processing. However, the conventional configuration has the following problems. (A) A configuration in which a plurality of transfer gates are connected to bit lines of a memory cell array, respectively, and the circuit scale becomes enormous, and it is difficult to lay out the transfer gates at the pitch of the memory cells. (B) Since the number of transfer gates connected to the column data bus is increased by the above configuration, the capacity of the column data bus is increased, which causes a reduction in operation speed. (C) Means for accessing continuous memory cell data and means for selecting columns for realizing a pixel-aligned access function have been proposed, but the conventional redundancy relief means cannot be applied. (D) In an image memory provided with a SAM, data reading from a redundant serial register is performed independently of the SAM data bus, and wiring for reading the data is parallel to the SAM data bus and the column data bus. Therefore, wiring for reading data from a column data bus, a SAM data bus, and a redundant serial register is required as a data bus area, which is a factor that increases the layout size. (E) When a semiconductor memory realizing a pixel alignment access function is applied to an image memory having a SAM, a SAM redundancy remedy has not been established.

[0022]

According to the present invention , as a first means for solving the above-mentioned problems, a memory cell array and a redundant
In a semiconductor memory comprising a long cell array and performing word data access by a data bus of a plurality of bits,
Corresponding to the address that follows the downward direction and the column decoder row cormorants column address location specified bits to output a selection signal in bits is entered in the column direction, to the column address and the column address input Signal synthesizing means for synthesizing a selection signal from a column decoder to be input, and a column address input corresponding to a defective memory cell.
And an address following the column address in the lower direction.
A column redundancy detection means for detecting less, and column selection gates respectively connected to the bit line output of the memory cell array is controlled independently, bits of said redundant cell array
Redundant columns that are connected to
The selection signal is output by the selection gate and the output of the column redundancy detection means.
Selection signal given from the signal synthesis means to the column selection gate
Signal control means for controlling the
In this configuration, a means for controlling a redundant column selection gate by an output is provided.

[0023]

As a second means, in a semiconductor memory having a memory cell array and a redundant cell array and performing data access through a data bus having a plurality of bits, a serial register for storing one row of data in the memory cell array; , Redundant data selecting means for selecting arbitrary data from one row of data, a redundant serial register for storing data selected by the redundant data selecting means, and a serial address input corresponding to a defective memory cell in the memory cell array. A serial redundant decoder for detecting, a position program circuit for designating a bit position in the word data of the defective memory cell, a means for controlling the redundant data selecting means by an output of the position program circuit, a serial redundant decoder and the position program Depending on the output of the circuit, It is an arrangement which includes a serial data selection circuit for data selected and output from Rurejisuta or redundant serial register.

As a third means, in a semiconductor memory having a memory cell array and a redundant cell array and performing word data access by a data bus having a plurality of bit widths,
Corresponding to the address that follows the downward direction and the column decoder row cormorants column address location specified bits to output a selection signal in bits is entered in the column direction, to the column address and the column address input Selection signal synthesizing means for synthesizing a selection signal from column data to be connected, a column selection gate connected to the bit line output of the memory cell array and independently controlled, and a column selection gate connected to the bit line of the redundant cell array and independently controlled A redundant column selection gate, a column address input corresponding to the defective memory cell and a column redundancy detection means for detecting an address following the column address in a lower direction, and a selection signal synthesizing means based on an output of the column redundancy detection means Signal control means for controlling a selection signal given to the column selection gate from the Means for controlling a redundant column selection gate by the output of the column redundancy detection means, a serial register for storing one row of data in the memory cell array, and redundant data selection for selecting arbitrary data from one row of data in the redundant cell array Means, a redundant serial register for storing data selected by the redundant data selecting means,
Means for controlling the redundant data selection means by the output of the column redundancy detection means, a serial redundancy decoder for detecting a serial address corresponding to a defective memory cell in the memory cell array, and the serial redundancy decoder and the column redundancy detection means for outputting the serial data. This configuration has a serial data selection circuit for selecting and outputting data from a register or a redundant serial register.

[0026]

With the configuration according to the first means, the pictorial
Semiconductor memory that realizes cell alignment access function
Thus, the redundancy relief function can be realized with a simple configuration .

[0027]

Further, by adopting the configuration of the second means, the number of redundant serial registers can be reduced in the image memory provided with the SAM.
Reduce the number of data read from redundant serial registers
Therefore, the data bus area in the layout can be reduced, and the chip size can be significantly reduced.

Further, with the configuration according to the third means, in the image memory having the pixel alignment access function having the SAM, a part of the column redundancy repair circuit and a part of the SAM redundancy repair circuit can be shared.
Thus, an image memory can be realized with a simple configuration.

[0030]

FIG. 1 shows an example of a circuit configuration of a semiconductor memory having a column selection circuit for realizing a pixel alignment access function according to the present invention. To the column address signal 16, an address having a bit width necessary for specifying a position in bit units is input. Reference numeral 8 denotes a column decoder that generates a column selection signal in bit units according to the column address input 16, and 10 denotes a column predecoder that generates an address to be given to the column decoder 8 from the column address input 16. Reference numeral 1 denotes a memory cell array for storing data, and reference numeral 5 denotes a column selection gate for selectively connecting bit line data of the memory cell array 1 to a column data bus 18 in response to a selection signal from a column decoder 8.

The column selection signal generated by the column decoder 8 is supplied to each transfer gate of the column selection gate 5 via the selection signal synthesis circuit 21. Here, the selection signal synthesizing circuit 21 is configured by an OR gate that performs an OR operation on the selection signal output of the corresponding bit of the column decoder 8 and the selection signal output of the bit following in the lower direction for each bit. .

FIG. 2 shows output signals of the column decoder 8 and the selection signal synthesizing circuit 21 with respect to the column address input 16. In the figure, a column address is an input address value given to a column address input 16, and a column bit position is shown in FIG.
In the column direction in the column direction, and the tables shown by the column decoder 8 and the selection signal synthesizing circuit 21 respectively show the column decoder 8 corresponding to the column address
3 shows an output signal of the selection signal synthesis circuit 21.

The column decoder 8 outputs a signal that sets only the signal at the column bit position corresponding to the column address to "1". The selection signal synthesizing circuit 21 performs an OR operation on the output of the column decoder 8 corresponding to the column address and the output of one bit following in the lower direction by the OR gate. Can be output to the column selection gate 5. This selection signal synthesis circuit 2
By driving the column selection gate 5 with the output signal of the column address 1, the column address input 1 to the column data bus 18
6, continuous 2-bit data can be connected.

By adopting the configuration shown in FIG. 1, a column selection circuit having a pixel alignment access function can be realized with a configuration in which one transfer gate is connected to each bit line of the memory cell array 1, and the memory cell pitch In addition to simplifying the layout design of the column selection gates for laying out, the capacity of the column data bus 18 is reduced to half that of the conventional example shown in FIG. 15, so that high-speed operation can be realized.

In the column selection circuit for implementing the pixel alignment function, each bit in the column direction of the memory cell array 1 is accessed not only by an address input corresponding to a bit position in the column direction but also by an address following in a lower direction. Therefore, the conventional redundancy remedy cannot be applied.

FIG. 3 shows an example of a memory configuration for realizing a redundancy repair function in a semiconductor memory having a column selection circuit for realizing the pixel alignment access function in FIG.

1 is a memory cell array for storing data,
2 is a redundant cell array for redundancy relief, 8 is a column decoder for generating a selection signal for selecting arbitrary row data of the memory cell array 1, and 5 is a bit line of the memory cell array 1 according to a selection signal from the column decoder 8. A column selection gate for selectively outputting data to the column data bus 18.

Reference numeral 6 denotes a redundant column selection gate for selectively outputting bit line data of the redundant cell array 2 to a column data bus 18 in response to a signal from the redundancy detection circuit 70. Reference numeral 10 denotes an address supplied from a column address input 16 to a column decoder 8. , A selection signal synthesis circuit for receiving a signal of the column decoder 8 and generating a selection signal to the column selection gate 5, and a selection signal 22 based on an output of the redundancy detection circuit 70. A selection signal control circuit that controls a selection signal supplied from the synthesis circuit 21 to the column selection gate.

Here, the redundancy detection circuit 70 has the configuration shown in FIG. 82 and 81 are memory cell arrays 1
(N) Detects an input address n corresponding to a defective memory cell (n), and detects an input address n-1 following the address n corresponding to the defective memory cell in the lower direction by 1 bit (n- 1) It is a redundant decoder and can be realized with the same circuit configuration.
Shown in

Column addresses C0 to Cn and / C0
/ Cn is applied to n-channel transistor 92, respectively. A fuse 91 programs a detection address by cutting a fuse corresponding to the address of the defective memory cell.

Reference numerals 93 and 94 denote p-channel transistors, reference numeral 95 denotes an inverter, and reference numeral 96 denotes a precharge signal input. With such a configuration, when a column address n corresponding to a defective memory cell is input, (n)
When the output Rn of the redundant decoder 82 is "0" and the column address of the address n-1 that follows the address n corresponding to the defective memory cell by one bit in the lower direction is input, (n-1) the redundant decoder The output Rn-1 of 81 becomes "0".

Reference numeral 83 denotes a position program circuit for programming the position of a defective memory cell in word data. In FIG. 3, since the word data is 2 bits, the position program circuit 83 programs whether the defective memory cell is at an even or odd address.

FIG. 6 shows a specific circuit example, which comprises an n-channel transistor 102, a fuse 101, p-channel transistors 103 and 104, an inverter 105, and a precharge signal input 106. The gate of the n-channel transistor 102 has a high potential. Figure 5 except for connecting to
Has the same connection relationship as the redundant decoder shown in FIG.

Here, when the defective memory cell exists at the even address, the output RP becomes "11" by leaving the fuse 91 uncut, and when the defective memory cell exists at the odd address, the fuse 101 is output. And the output RP is set to “0”.

The outputs of (n-1) redundant decoder 71, (n) redundant decoder 82 and position program circuit 83 are set to N
By performing a logical operation by AND gates 84 to 86 and inverter 87, outputs RE and RO of redundancy detection circuit 70 become as shown in FIG.

In FIG. 7, the column address indicates the position of the memory cell in the memory cell array 1 in the column direction. If the memory cell corresponding to the address 2 is defective, (n) detection by the redundant decoder 82 is performed. The fuse is programmed so that the address is set to 2 and the detection address in the (n-1) redundancy decoder 81 is set to 1.

By keeping the fuse of the position program circuit 83 conductive, RE becomes "0" in the case of an address input corresponding to the column addresses 1 and 2 as indicated by α. If the memory cell corresponding to the address 3 is defective, the fuse is programmed so that (n) the detection address of the redundancy decoder 82 is 3 and the detection address of the (n-1) redundancy decoder 81 is 2. Further, by blowing the fuse of the position program circuit 83, RO becomes “0” in the case of an address input corresponding to the column addresses 2 and 3 as indicated by β.

In FIG. 3, when a memory cell in memory cell array 1 has a defect and the defective cell is located at an even-bit position, the bit in which the defective memory cell exists is accessed as described above. When the column address is input, the fuse is programmed so that the RE output of the redundancy detection circuit 70 becomes "0". In this case, the selection signal control circuit 22 outputs the signal from the selection signal synthesis circuit 21 connected to the even-numbered bits. Are shut off.

Also, the redundant column selection gate 6 on the even-numbered side is driven by the RE output of the redundancy detecting circuit 70 via the inverter 23, and the memory cells in the redundant cell array 2 are accessed.

Similarly, when a defective cell in the memory cell array 1 is located at an odd-numbered bit position, if a column address at which a bit at which a defective memory cell exists is accessed is input as described above, there is no redundancy. Since the fuse is programmed so that the RO output of the detection circuit 70 becomes “0”, in this case, the control signal from the selection signal synthesis circuit 21 connected to the odd bit is cut off by the selection signal control circuit 22.

In addition, the redundant column selection gate 6 on the odd-numbered side is driven by the RO output of the redundancy detection circuit 11 via the inverter 23, and the memory cell in the redundancy cell array 2 is accessed.

As described above, the redundancy relieving function can be realized with a simple configuration even in the semiconductor memory having the column selection circuit realizing the pixel alignment access function by the configuration shown in FIG.

FIG. 8 shows a configuration of a semiconductor memory capable of realizing SAM redundancy relief with a simple circuit and layout configuration. 1 is a memory cell array for storing data, 2 is a redundant cell array for redundancy relief, and 3 is an arbitrary one of a memory cell array 1 having a plurality of registers R.
This is a serial register that stores row data.

Reference numeral 4 denotes redundant data selecting means including transfer gates 4-1 and 4-2 for selecting data of bit lines of the redundant cell array 2, and stores data selected by the transfer gates 4-1 and 4-2. A SAM select gate 7 selectively outputs a signal stored in the serial register 3 to the SAM data bus 20 in accordance with a select signal from the SAM decoder 9.

30 is a position program circuit, 13 is a SAM
A pre-decoder for generating an address to be given to the SAM decoder 9 from the address input signal 17, a SAM redundancy decoder 13, and a SAM data selection circuit 15.

As described above, the column redundancy repair in the semiconductor memory having the pixel alignment access function when the word data is 2 bits is to replace either the even address or the odd address with a redundant cell. Therefore, the redundant cell array 2 includes memory cells for two columns, but the redundant serial register 4 includes only one serial register R.

A specific circuit example of the position program circuit 30 is shown in FIG.
It is shown in FIG. Those having the same numbers as those of the circuit shown in FIG. 6 are components having the same functions. The circuit excluding the inverter 106 is the same as that shown in FIG. 6, and similarly to the fuse program in the circuit shown in FIG. 6, when the rescue address is an even number, the fuse is not cut off and the rescue address is an odd number. In the case of (1), the fuse is cut off. When the rescue address is an even number, RSE becomes "1" and RSO becomes "0". When data is transferred from the redundant cell array 2 to the redundant serial register 4, the data on the even side is read. Is transferred to the register R.

When the rescue address is an odd number, the RSE is "0" and the RSO is "1", and the data on the odd side is transferred to the register R when data is transferred from the redundant cell array 2 to the redundant serial register 4.

FIG. 10 shows a specific circuit example of the SAM redundancy decoder 14. Those having the same numbers as those of the column redundancy decoder shown in FIG. 5 have the same functions. It has the same configuration as the column redundancy decoder shown in FIG.
7 (S0 to Sm, / S0 to / Sm) are configured by an n-channel transistor 92, a fuse 91, p-channel transistors 93 and 94, and an inverter 95.

When the SAM address input 17 corresponds to the rescue address by programming the fuse 91, the output RS is set to "0". At the time of SAM access, a SAM address input signal 17 is given to the SAM decoder 9 via the predecoder 13, and the SAM selection gate 7 is controlled by a selection signal from the SAM decoder to thereby generate a serial signal corresponding to the SAM address input signal 17. When the data in the register 3 is selected, the SAM data bus 20
Connected to.

The SAM data selection circuit 15 selects the SAM data bus 20 and outputs it to the SAM data 19. SAM
When the address input signal 17 corresponds to the relief address, the output RS of the SAM redundancy decoder 14 becomes “0”,
The SAM data selection circuit 15 is connected to the SAM data bus 2 by the outputs RSE and RSO of the position program circuit 30.
0 and the data from the redundant serial register 4 are selected and output to the SAM data 19.

That is, when the rescue address is an even number, the output RSE of the position program circuit 30 is "1" and the RSO is "0". At the time of rescue, the data from the odd side of the SAM data bus 20 and the data from the redundant serial register 4 are transmitted. When the rescue address is odd, the output RSE of the position program circuit 30 is "0" and the RSO is "1" when the rescue address is an odd number. At the time of rescue, data from the even-numbered side of the SAM data bus 20 and the redundant serial register 4 are selected. As a result, SAM redundancy relief can be realized.

As described above, with the configuration shown in FIG. 8, the number of redundant serial registers can be reduced and the number of data output lines from redundant serial register 4 can be reduced. The layout area in the register and data wiring regions can be significantly reduced.

FIG. 11 shows a configuration example of a column selection circuit and a redundancy repair circuit having a pixel align access function, and a semiconductor memory having a SAM selection circuit and a redundancy repair circuit.
Shown in

1 is a memory cell array for storing data,
2 is a redundant cell array for redundancy relief, and 3 is a register R
, A serial register for storing data of an arbitrary row of the memory cell array 1 provided with a plurality of memory cells, and a redundant data selecting means 4 comprising transfer gates 4-1 and 4-2 for selecting bit line data of the redundant cell array 2. And a redundant serial register consisting of a register R for storing data selected by the transfer gates 4-1 and 4-2.

8 is a column decoder for generating a selection signal for selecting arbitrary row data of the memory cell array 1;
Reference numeral 21 denotes a selection signal synthesizing circuit for generating a selection signal for performing pixel alignment access from the selection signal from the column decoder 8, and reference numeral 22 controls the selection signal from the selection signal synthesizing circuit 21 by a signal from the redundancy detection circuit 11. The selection signal control circuit 5 is a column selection gate for selectively connecting the data of the bit line of the memory cell array 1 to the column data bus 18 in accordance with the selection signal from the selection signal control circuit 22, and 6 is the redundancy detection circuit 11 to the inverter 23. Is a redundant column selection gate which is driven by a signal through the redundant cell array 2 and selectively outputs bit line data of the redundant cell array 2 to the column data bus 18.

Reference numeral 9 denotes a SAM decoder for generating a selection signal for selecting arbitrary data in the serial register 3;
Selects a signal stored in the serial register 3 in response to a selection signal from the SAM decoder 9 and selectively outputs the signal to the SAM data bus 2.
This is a SAM selection gate that outputs 0.

Reference numeral 10 denotes a column pre-decoder for generating an address to be given to the column decoder 8 from the column address input signal 16, and reference numeral 11 detects a column redundancy and controls a redundant data selecting means composed of 4-1 and 4-2. This is a column redundancy detection circuit that generates a signal to be output.

Reference numeral 13 denotes S from the SAM address input signal 17
An SAM predecoder that generates an address to be given to the AM decoder 9, a SAM redundant decoder 14, and a SAM data selection circuit 15 that selects data from the SAM data bus 20 or the redundant serial register 4 and outputs the selected data to SAM data 19.

In the figure, the column data bus 18 and the SAM data 19 and the S
The bit width of the AM data bus 20 is 2 bits, and the size of the redundant cell array 2 is 2 columns (the rescue address is 1 column). Components having the same numbers as those shown in FIGS. 1, 3 and 8 are the same components and perform the same operations.

The circuit and operation of the redundancy detection circuit 11 different from those shown in FIGS. 1, 3 and 8 will be described below. The specific circuit example of the redundancy detection circuit 11 is as shown in FIG. 12, and the (n-1) redundancy decoder 81, the (n) redundancy decoder 82 and the position program circuit 83 are the same as those shown in FIGS. is there.

R similar to FIG. 4 performs the operation shown in FIG. 7 by NAND gates 84 to 86 and inverter 87.
E and RO can be output.
By providing O to the selection signal control circuit 22 and the inverter, a column selection circuit and a redundancy repair circuit having a pixel alignment access function shown in FIG. 3 can be realized.

The same RSE and RS as those in the circuit shown in FIG.
O can be output, and S in the simple configuration shown in FIG.
An AM redundancy repair circuit can be realized.

As described above, with the configuration shown in FIGS. 11 and 12, column redundancy relief and SA
A control signal for M redundancy rescue can be generated by the same circuit. Using this signal, a column selection circuit and a redundancy rescue circuit having a pixel alignment access function with a simple configuration, and a SAM selection circuit and a redundancy rescue circuit A semiconductor memory having a relief circuit can be realized.

In the embodiment, as in the prior art, the case where the word data width is 2 bits and the internal data bus width is 2 bits has been described. However, the present invention does not depend on the word data width. Needless to say, the same function can be realized even when the word width is further increased.

[0076]

As described above, according to the present invention, a column selecting circuit having a pixel align access function can realize a high speed operation with a simple circuit configuration and has a pixel align access function having a redundancy repair circuit. A semiconductor memory can be realized with a simple configuration.

Also, an image memory having a pixel alignment access function provided with a SAM can be realized with a simple circuit configuration, and the layout area can be greatly reduced. Therefore, a semiconductor memory having a pixel alignment access function can be realized with a small chip size, so that an inexpensive memory can be provided.

Further, according to the present invention, only one column select gate is connected to each bit line of the memory cell array, and the number of redundant serial registers can be reduced according to the word data width. With the configuration, a high-performance semiconductor memory can be realized, and the effect of the present invention is further exerted as the semiconductor memory has a configuration in which the word data width is wider.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a column selection unit in one embodiment of a semiconductor memory of the present invention.

FIG. 2 is a functional explanatory diagram of a column decoder and a column selection signal synthesis circuit in FIG. 1;

FIG. 3 is a configuration diagram of a column selection unit and a column redundancy repair unit in the embodiment.

FIG. 4 is a circuit diagram showing a specific example of a column redundancy detection circuit in FIG. 3;

FIG. 5 is a circuit diagram showing a specific example of a column redundancy decoder in FIG. 4;

FIG. 6 is a circuit diagram showing a specific example of a position program circuit in FIG. 4;

FIG. 7 is an explanatory diagram of the operation of the column redundancy decoder in FIG. 4;

FIG. 8 is a configuration diagram showing a specific example of a SAM selection unit and a SAM redundancy repair unit in the semiconductor memory of the present invention;

9 is a configuration diagram showing a specific example of a position program circuit in FIG.

FIG. 10 is a configuration diagram showing a specific example of a SAM redundancy decoder in FIG. 8;

FIG. 11 is a configuration diagram showing a specific example of a column and SAM selection unit and a redundancy relief unit in the semiconductor memory of the present invention;

12 is a circuit diagram showing a specific example of a column redundancy detection circuit in FIG.

FIG. 13 is a circuit diagram showing a configuration of a column, a SAM selection unit, and a redundancy repair unit in the related art.

FIG. 14 is a data array diagram on a screen in an image memory.

FIG. 15 is a circuit diagram showing a configuration of a conventional column selection unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Redundant cell array 3 Serial register 4 Redundant serial register 5 Column selection gate 6 Redundant column selection gate 7 SAM selection gate 8 Column decoder 9 SAM decoder 10 Column predecoder 11 Column redundancy detection circuit 13 SAM predecoder 14 SAM redundancy decoder 15 SAM data selection circuit 16 column address signal 17 SAM address signal 18 column data bus 19 SAM data 20 SAM data bus 21 column selection signal synthesis circuit 22 column selection signal control circuit 23 inverter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-47589 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/409

Claims (11)

(57) [Claims] 1. A and a memory cell array and the redundant cell array in a semiconductor memory which performs word data access by a data bus of a plurality of bits wide, in bits is input row cormorants column address location specified bits in the column direction A column decoder which outputs a selection signal of the following; a selection signal synthesizing means for synthesizing a selection signal from the column decoder corresponding to the input column address and an address following the column address in a lower direction; A column redundancy detection means for detecting a column address input corresponding to the cell and an address following in the lower direction with respect to the column address; and a column selection gate connected to the bit line output of the memory cell array and independently controlled. Respectively connected to the bit lines of the redundant cell array. A redundant column selection gate, which is independently controlled, a selection signal control means for controlling a selection signal given from the selection signal synthesizing means to the column selection gate by an output of the column redundancy detection means, and an output of the column redundancy detection means A means for controlling the redundant column selection gate according to claim 1. 2. The semiconductor memory according to claim 1 , wherein said selection signal synthesizing means comprises a logical sum operation means. 3. A column redundancy detecting means for detecting a column address input corresponding to a defective memory cell and a column address following the column address corresponding to the defective memory cell in a lower direction. one or more follow-up address redundancy decoder and a semiconductor memory according to claim 1, characterized in that it comprises an location program circuit for designating a bit position in the word data of the defective memory cell. 4. The method of claim 1, characterized in that the selection signal controlling means consists of means for controlling the conduction or blocking of the selection signal
The semiconductor memory according to any one of the preceding claims. 5. A semiconductor memory comprising a memory cell array and a redundant cell array and performing data access through a data bus having a plurality of bits, wherein: a serial register for storing one row of data in the memory cell array; Redundant data selecting means for selecting arbitrary data from one row of data; a redundant serial register for storing data selected by the redundant data selecting means; and a serial address input corresponding to a defective memory cell in the memory cell array. A serial redundancy decoder for detecting, a position program circuit for specifying a bit position in the word data of the defective memory cell, a means for controlling the redundant data selection means by an output of the position program circuit, Output of position program circuit And a serial data selection circuit for selecting and outputting data from the serial register or the redundant serial register. 6. The redundant data selecting means comprises a plurality of transfer gates connected between a plurality of bit lines of a redundant cell array and a redundant serial register.
6. The semiconductor memory according to 5 . 7. a memory cell array and the redundant cell array in a semiconductor memory which performs word data access by a data bus of a plurality of bits wide, in bits is input row cormorants column address location specified bits in the column direction a column decoder for outputting a selection signal, a selection signal combining means for combining the selected signal from the column data corresponding to the address that follows the lower direction with respect to the column address and the column address input, the memory and column selection gates respectively connected to the cell array bit line output is controlled independently, the redundant cell array redundant and column selection gates, each controlled independently connected to the bit line of the column address corresponding to the defective memory cell Follow the input and the column address in the lower direction A column redundancy detection unit for detecting a dress; a selection signal control unit for controlling a selection signal given from the selection signal synthesis unit to the column selection gate based on an output of the column redundancy detection unit; Means for controlling a redundant column selection gate; a serial register for storing one row of data in the memory cell array; redundant data selecting means for selecting arbitrary data from one row of data in the redundant cell array; A redundant serial register for storing data selected by the data selection unit; a unit for controlling the redundant data selection unit based on an output of the column redundancy detection unit; and detecting a serial address corresponding to a defective memory cell in the memory cell array. Serial redundancy decoder, and the serial redundancy decoder The semiconductor memory characterized in that it comprises a serial data selection circuit by the output of the spare the column redundancy detection means for data selected and output from the serial register or the redundant serial register. 8. The semiconductor memory according to claim 7 , wherein said selection signal synthesizing means comprises an OR operation means. 9. A column redundancy detecting means for detecting a column address input corresponding to a defective memory cell, and a column address following the column address corresponding to the defective memory cell in a lower direction. 8. The semiconductor memory according to claim 7, further comprising one or a plurality of following address redundancy decoders, and a position program circuit for specifying a bit position in word data of the defective memory cell. 10. The selection signal control means comprises means for controlling conduction or interruption of a selection signal.
8. The semiconductor memory according to 7 . 11. The semiconductor memory according to claim 7 , wherein the redundant data selecting means comprises a plurality of transfer gates connected between the plurality of bit lines of the redundant cell array and the redundant serial register.