JPH0785665A - Semiconductor memory - Google Patents

Abstract

(57) [Abstract] [Purpose] A semiconductor memory that is accessed with multiple bits of word data has a simple structure and a high-speed column selection circuit that can specify the position in bit units. Realize the relief function. [Structure] Memory cell array 1 and redundant cell array 2
And a column decoder 8 for inputting a column address for specifying a bit-wise position in the column direction and outputting a selection signal in a bit unit, an input column address and an address following the column address in the lower direction. The selection signal synthesizing circuit 21 for synthesizing the selection signals from the column decoder corresponding to the above, the column selection gate 5 connected to the bit line output of the memory cell array 1 and independently controlled, and the output of the selection signal synthesizing circuit 21 The structure is provided with means for driving the column selection gate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a column and a SAM which are equipped with a random access memory and a serial access memory (hereinafter referred to as SAM) and which are effective when an image memory for storing image information is used. The present invention relates to a semiconductor memory including a selection circuit and a redundancy repair circuit.

[0002]

2. Description of the Related Art A semiconductor memory is a multi-bit data I / I.
It has an O terminal, and the wider the I / O data width, the larger the number of bits that can be read / written in one access, and the faster data access becomes possible. Therefore, I
A / O data width of about 8 to 19 bits has been put into practical use, and it is expected that it will become wider. Therefore, in the semiconductor memory, the memory cell array is accessed by data having a plurality of bit widths (hereinafter referred to as words).

Columns and S in conventional image memory
FIG. 13 shows the configuration of the AM selection circuit. Reference numeral 1 is a memory cell array for storing data, 2 is a redundant cell array for redundancy relief, 3 is a serial register for storing data of any one row of the memory cell array 1 including a plurality of registers R, and 32 is a register R. It is a redundant serial register that stores data of any one row of the redundant cell array 2 including a plurality of cells.

28 is a column decoder for generating a selection signal for selecting any row data of the memory cell array 1, 25 is a column decoder for selectively selecting the bit line data of the memory cell array 1 by the selection signal from the column decoder 28. The column selection gate 26 connected to the bus 18 is
The data from the bit line of the redundant cell array 2 is selectively supplied to the column data bus 1 by the signal from the column redundancy decoder 27.
8 is a redundant column selection gate for outputting to 8.

Reference numeral 9 is a SAM decoder for generating a selection signal for selecting arbitrary data of the serial register 3, and 7
Is a signal selectively stored in the serial register 3 according to a selection signal from the SAM decoder 9
This is a SAM selection gate that outputs 0.

Reference numeral 30 is a column predecoder for generating an address given to the column decoder 28 from the column address input signal 31, 27 is a column redundancy decoder for detecting a column address input 31 corresponding to a defective memory cell in the memory cell array 1, and 12 is a column redundancy decoder. An address control circuit that controls the address supply to the column decoder 28 by the output of the column redundancy decoder 27.

Reference numeral 13 is a SAM address input signal 17 to S
A SAM predecoder for generating an address to be given to the AM decoder 9, and a SAM for detecting a SAM address input 17 corresponding to a defective memory cell in the memory cell array 1.
A redundancy decoder 29 selects data from the SAM data bus 20 or the redundancy serial register 32 to select the SAM.
This is a SAM data selection circuit for outputting to the data 19.

In the figure, the bit width of the column data bus 18, the SAM data 19 and the SAM data bus 20 is 2 bits, and the size of the redundant cell array 2 is 2 columns (the relief address is 1 column).

To describe the column system data access, the column address signal 31 is the column predecoder 3
It is supplied to the column redundancy decoder 27 together with 0. The output of the column predecoder 30 is given to the column decoder 28 via the address control circuit 12, and the column decoder 2
The column select gate 5 is driven by the output of the select signal 8 to select any data in the memory cell array 1 and connect it to the column data bus 18.

If there is a defective memory cell in the memory cell array 1 and the column address signal 31 corresponding to this defective memory cell is input, the column redundancy decoder 2
The redundant address is detected by 7, and the output of the column redundant decoder 27 becomes "1". Address control circuit 12
Shuts off the address signal to the column decoder 28 by the output signal of the redundant decoder 27, selects the redundant memory cell by the redundant column selection gate 26 connected to the redundant cell array 2, and connects it to the column data bus 18.

Since high speed is required for SAM data access, the redundant serial register 32 is generally accessed at all times. The SAM address signal 17 is given to the SAM redundant decoder 14 together with the SAM predecoder 13. The output of the SAM predecoder 13 is given to the SAM decoder 9, and the SAM selection gate 7 is driven by the selection output signal of the SAM decoder 9 to select an arbitrary bit of the serial register 3 and connect it to the SAM data bus 20.

When the SAM address 17 corresponding to the defective column address is input, the SAM redundant decoder 1
The redundant address is detected by 4 and the output of the redundant decoder 14 becomes "1". With this signal, the SAM data selection circuit 15 selects the data of the redundant serial register 32 and outputs it to the SAM data 19. With such a configuration, the critical path at the time of SAM access is shortened, and high-speed SAM access is realized.

In the figure, the column data bus 18 and the SAM data bus 20 are set to 2 bits, and the access is made in units of 2 bits.
The M decoder 9 generates a selection signal in units of 2 bits, and the column address 31 and the SAM address 17 are supplied with addresses for accessing in units of 2 bits.

FIG. 14 shows an arrangement of image data when the semiconductor memory shown in FIG. 13 is applied to an image memory for storing image data. In the configuration shown in FIG. 13, since the unit of word data is 2 bits, the image data accessed by the input address is designated with a 2-pixel pitch, as indicated by the symbol a.
In the image processing in the image processing system, the code b
Image data access on a pixel-by-pixel basis is frequently used as shown in FIG.

Therefore, it has been proposed to provide a semiconductor memory with a function (hereinafter referred to as a pixel align access function) capable of accessing word data by specifying a position in bit units.

FIG. 15 is a block diagram of a column selection circuit for realizing the pixel align access function. The column address signal 16 is input with an address having a bit width necessary for specifying the position in bit units.

Reference numeral 8 is a column decoder which generates a column selection signal in bit units according to the column address input 16, and 10 is a column predecoder which generates an address to be supplied to the column decoder 8 from the column address input 16. 1 is a memory cell array for storing data, and 4
A column selection gate 1 selectively connects the data of the bit line of the memory cell array 1 to the column data bus 18 in response to a selection signal from the column decoder 8.

In FIG. 15, the column selection gate 41 is
The column decoder 8 includes two transfer gates for each bit line of the memory cell array 1, each of which is connected to a different column data bus, and transfer gates connected to adjacent bit lines are simultaneously selected. Selection signal is supplied.

By a selection signal from the column decoder 8,
Since two consecutive bits are always selected, FIG. 14 (2)
It is possible to access by specifying the position in bit units as shown in.

13 to 15, the column data bus 18 and the SAM data bus 20 have 2 bits,
Although the configuration in which the 2-bit word data is accessed to the memory cell array 1 is shown, the column data bus 18 and the SAM data bus 20 have the required bit widths in order to access the 3-bit or more word data. , Column decoder 28 and SAM in FIG.
The decoder 9 is configured to generate a selection signal in a required bit width unit, and the column selection gate 4 shown in FIG.
In No. 1, by setting the number of transfer gates connected to each bit line to the required number of bit widths and connecting them according to the required bit width, the same operation as in the case of 2 bits can be realized.

[0021]

As described above,
When a semiconductor memory is applied to an image memory, a configuration that realizes a pixel align access function has been proposed for the purpose of speeding up image processing, but the conventional configuration has the following problems. (A) Since a plurality of transfer gates are connected to each bit line of the memory cell array, the circuit scale becomes huge, and it is difficult to lay out the transfer gates at the pitch of the memory cells. (B) With the above configuration, the number of transfer gates connected to the column data bus increases, so that the capacity of the column data bus increases, which is a factor of slowing down the operation speed. (C) A continuous means for accessing memory cell data and a column selection means for realizing the pixel-aligned access function have been proposed, but the conventional redundancy repair means cannot be applied. (D) In the image memory equipped with SAM, the data reading from the redundant serial register is performed independently of the SAM data bus, and the wiring for this data reading is parallel to the SAM data bus and the column data bus. Therefore, wiring for reading data from the column data bus, the SAM data bus, and the redundant serial register is required as a data bus area, which is a factor of increasing the layout size. (E) In the case of applying the semiconductor memory that realizes the pixel-aligned access function to the image memory including the SAM, the SAM redundant remedy means has not been established.

[0022]

As a first means for solving the above-mentioned problems, the present invention provides, as a first means for solving the above-mentioned problems, a bit-wise position designation in a column direction in a semiconductor memory for word data access by a data bus having a plurality of bit widths. A column decoder that inputs a column address that outputs a column signal that outputs a selection signal in bit units, and a selection signal from a column decoder that corresponds to an input column address and an address that follows the column address in the lower direction are combined. The configuration includes a selection signal synthesizing means, a column selection gate connected to the bit line output of the memory cell array and independently controlled, and a means for driving the column selection gate by the output of the selection signal synthesizing means. .

As a second means, in a semiconductor memory having a memory cell array and a redundant cell array and performing word data access by a data bus having a plurality of bit widths,
Corresponds to a column decoder that inputs a column address that specifies a bit unit position in the column direction and outputs a selection signal in a bit unit, and an input column address and an address that follows the column address in the lower direction. A selection signal synthesizing means for synthesizing a selection signal from a column decoder, a column redundancy detecting means for detecting a column address input corresponding to a defective memory cell and an address following the column address in a lower direction, and a bit of a memory cell array. A column selection gate connected to the line output and controlled independently of each other, a redundant column selection gate connected to the bit line of the redundant cell array and controlled independently of each other, and a selection signal synthesizing means by the output of the column redundancy detecting means. Selection signal for controlling selection signal applied to the column selection gate And control means, is intended to a structure having means for controlling the redundant column selection gate by the output of the column redundancy detection means.

As a third means, in a semiconductor memory having a memory cell array and a redundant cell array and accessing data through a data bus having a plurality of bit widths, a serial register for storing one row of data in the memory cell array and a redundant cell array. A redundant data selecting means for selecting arbitrary data from one row of data, a redundant serial register for storing the data selected by the redundant data selecting means, and a serial address input corresponding to a defective memory cell in the memory cell array. A serial redundancy decoder for detecting, a position program circuit for designating a bit position in word data of a defective memory cell, a means for controlling the redundant data selecting means by the output of the position program circuit, a serial redundancy decoder and the position program. Siri by the output of the circuit It is an arrangement which includes a serial data selection circuit for data selected and output from Rurejisuta or redundant serial register.

As a fourth means, in a semiconductor memory having a memory cell array and a redundant cell array and performing word data access by a data bus having a plurality of bit widths,
Corresponds to a column decoder that inputs a column address that specifies a bit unit position in the column direction and outputs a selection signal in a bit unit, and an input column address and an address that follows the column address in the lower direction. A selection signal synthesizing means for synthesizing a selection signal from column data, a column selection gate connected to the bit line output of the memory cell array and independently controlled, and a column selection gate connected to the bit line of the redundant cell array and independently controlled. A redundant column selection gate, a column redundancy input means for detecting a column address input corresponding to a defective memory cell and an address following the column address in the lower direction, and a selection signal synthesizing means by the output of the column redundancy detection means. Selection signal controller for controlling the selection signal applied to the column selection gate A means for controlling the redundant column selection gate by the output of the column redundancy detecting means, a serial register for storing one row of data in the memory cell array, and a redundancy for selecting arbitrary data from one row of data in the redundant cell array. A data selecting means, a redundant serial register for storing the data selected by the redundant data selecting means, a means for controlling the redundant data selecting means by the output of the column redundancy detecting means, and a serial corresponding to a defective memory cell in the memory cell array. The configuration is provided with a serial redundancy decoder for detecting an address and a serial data selection circuit for selecting and outputting data from the serial register or the redundant serial register by the outputs of the serial redundancy decoder and the column redundancy detecting means.

[0026]

According to the first means, in a semiconductor memory for accessing word data of a plurality of bit widths with a simple structure in which one transfer gate is connected to each bit line of the memory cell array and the redundant cell array. Since the pixel-aligned access function can be realized, the transfer gates can be easily laid out at the memory cell pitch, and the number of transfer gates connected to the column data bus can be reduced, resulting in high-speed operation. Is possible.

Further, by adopting the structure of the second means, the redundancy repair function can be realized with a simple structure in the semiconductor memory which realizes the pixel align access function.

Further, by adopting the configuration of the third means, it is possible to reduce the number of redundant serial registers in the image memory provided with the SAM and also reduce the number of data read from the redundant serial registers. Therefore, the data bus area in the layout can be reduced, and the chip size can be significantly reduced.

Further, by adopting the configuration of the fourth means, in the image memory having the pixel align access function having the SAM, the column redundancy repair circuit and the S
Since a part of the AM redundancy repair circuit can be shared,
The image memory can be realized with a simple configuration.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit configuration example of a semiconductor memory having a column selection circuit for realizing the pixel align access function in the present invention. The column address signal 16 is input with an address having a bit width required to specify the position in bit units. Reference numeral 8 is a column decoder that generates a column selection signal in bit units according to the column address input 16, and 10 is a column predecoder that generates an address to be supplied to the column decoder 8 from the column address input 16. Reference numeral 1 is a memory cell array for storing data, and 5 is a column selection gate for selectively connecting the data of the bit line of the memory cell array 1 to the column data bus 18 in response to a selection signal from the column decoder 8.

The column selection signal generated by the column decoder 8 is applied to each transfer gate of the column selection gate 5 via the selection signal synthesis circuit 21. Here, the selection signal synthesizing circuit 21 is composed of an OR gate for performing an OR operation of the selection signal output of the corresponding bit of the column decoder 8 and the selection signal output of the bit following in the lower direction for each bit. .

The output signals of the column decoder 8 and the selection signal synthesis circuit 21 for the column address input 16 are shown in FIG. In the figure, the column address is the input address value given to the column address input 16, and the column bit position is shown in FIG.
The bit positions in the column direction in the column decoder 8 and the table indicated by the column decoder 8 and the selection signal combining circuit 21 are respectively shown in the column decoder 8 corresponding to the column address.
And the output signal of the selection signal synthesis circuit 21.

The column decoder 8 outputs a signal which sets only the signal at the column bit position corresponding to the column address to "1". The selection signal synthesizing circuit 21 uses a logical sum gate to perform the logical sum of the output of the column decoder 8 corresponding to the column address and the output of 1 bit that follows in the lower direction, so that two consecutive bits depending on the column address input signal 16 are generated. It is possible to output to the column selection gate 5 a selection signal for performing the selection. This selection signal synthesis circuit 2
By driving the column select gate 5 with the output signal of 1, the column address input 1 to the column data bus 18
Depending on 6, it is possible to connect continuous 2 bits of data.

With the configuration shown in FIG. 1, a column selection circuit having a pixel align access function can be realized with a configuration in which one transfer gate is connected to each bit line of the memory cell array 1, and the memory cell pitch is obtained. The layout design of the column select gate for layout is simplified, and the capacity of the column data bus 18 is halved as compared with the conventional example shown in FIG. 15, so that high speed operation can be realized.

In the column selection circuit for realizing the pixel align function, each bit in the column direction of the memory cell array 1 is accessed not only by the address input corresponding to the bit position in the column direction but also by the address following in the lower direction. Therefore, the conventional redundancy remedy cannot be applied.

FIG. 3 shows an example of a memory configuration for realizing a redundancy repair function in a semiconductor memory having a column selection circuit for realizing the pixel align access function in FIG.

1 is a memory cell array for storing data,
Reference numeral 2 is a redundant cell array for redundancy relief, 8 is a column decoder for generating a selection signal for selecting any row data of the memory cell array 1, and 5 is a bit line of the memory cell array 1 according to a selection signal from the column decoder 8. A column selection gate that selectively outputs data to the column data bus 18.

Reference numeral 6 is a redundant column select gate for selectively outputting the data of the bit line of the redundant cell array 2 to the column data bus 18 in response to a signal from the redundancy detection circuit 70, and 10 is an address given from the column address input 16 to the column decoder 8. A column pre-decoder 70 for generating a redundancy detection circuit, 21 a selection signal synthesis circuit for receiving a signal from the column decoder 8 and generating a selection signal to the column selection gate 5, and 22 a selection signal generated by the output of the redundancy detection circuit 70. A selection signal control circuit for controlling a selection signal given from the synthesis circuit 21 to the column selection gate.

Here, the redundancy detecting circuit 70 has the structure shown in FIG. 82 and 81 are memory cell arrays 1
(N) a redundant decoder that detects an input address n corresponding to a defective memory cell in the memory cell and an input address n-1 that follows the address n corresponding to the defective memory cell in the lower direction by 1 bit (n- 1) A redundant decoder, which can be realized with the same circuit configuration, and its specific circuit example is shown in FIG.
Shown in.

Column addresses C0 to Cn and / C0
/ Cn is applied to the n-channel transistor 92, respectively. Reference numeral 91 denotes a fuse, which programs a detection address by cutting a fuse corresponding to the address of the defective memory cell.

Reference numerals 93 and 94 are p-channel transistors, 95 is an inverter, and 96 is a precharge signal input. With such a configuration, when a column address n corresponding to a defective memory cell is input (n).
When the output Rn of the redundancy decoder 82 is "0" and the column address of the address n-1 that follows the address n corresponding to the defective memory cell in the lower direction by 1 bit is input (n-1) redundancy decoder The output Rn-1 of 81 becomes "0".

Reference numeral 83 is a position program circuit for programming the position of the defective memory cell in the word data. In FIG. 3, since the word data is 2 bits, the position program circuit 83 programs whether the defective memory cell is at an even or odd address.

A specific circuit example is shown in FIG. 6, which is composed of an n-channel transistor 102, a fuse 101, p-channel transistors 103 and 104, an inverter 105, and a precharge signal input 106. The gate of the n-channel transistor 102 is set to a high potential. 5 except for connecting to
It has the same connection relationship as the redundant decoder shown in.

If the defective memory cell exists at an even address, the fuse 91 is left uncut, and the output RP becomes "11". If the defective memory cell exists at an odd address, the fuse 101 is provided. Is disconnected and the output RP is set to "0".

The outputs of the (n-1) redundant decoder 71, the (n) redundant decoder 82 and the position program circuit 83 are set to N.
The logical operations of AND gates 84 to 86 and inverter 87 result in outputs RE and RO of redundancy detecting circuit 70 as shown in FIG.

In FIG. 7, the column address indicates the position of the memory cell in the memory cell array 1 in the column direction. When the memory cell corresponding to the address 2 is defective, the (n) redundancy decoder 82 detects it. The fuse is programmed so that the address is set to 2 and the detection address in the (n-1) redundant decoder 81 is set to 1.

Further, by keeping the fuse of the position program circuit 83 conductive, RE becomes "0" in the case of address input corresponding to the column addresses 1 and 2 as indicated by α. If the memory cell corresponding to the address 3 is defective, the fuse is programmed so that the detection address in the (n) redundant decoder 82 is set to 3 and the detection address in the (n-1) redundant decoder 81 is set to 2. Further, by blowing the fuse of the position program circuit 83, RO becomes “0” when the address corresponding to the column addresses 2 and 3 is input as shown by β.

In FIG. 3, when a memory cell of the memory cell array 1 has a defect and the defective cell exists at an even bit position, the bit in which the defective memory cell exists is accessed as described above. When the column address is input, the fuse is programmed so that the RE output of the redundancy detection circuit 70 becomes “0”. In this case, therefore, the selection signal control circuit 22 causes the selection signal synthesizing circuit 21 connected to the even-numbered bits. The control signal of is cut off.

Further, the RE output of the redundancy detecting circuit 70 drives the even-numbered side redundant column select gate 6 through the inverter 23 to access the memory cell in the redundant cell array 2.

Similarly, when a defective cell in the memory cell array 1 exists at an odd bit position, redundancy occurs when the column address for accessing the bit in which the defective memory cell exists is input as described above. Since the fuse is programmed so that the RO output of the detection circuit 70 becomes "0", in this case, the control signal from the selection signal synthesizing circuit 21 connected to the odd bits is cut off by the selection signal control circuit 22.

The RO output of the redundancy detection circuit 11 drives the odd-numbered redundant column selection gate 6 via the inverter 23 to access the memory cells in the redundant cell array 2.

As described above, even in the semiconductor memory provided with the column selection circuit for realizing the pixel align access function by the structure shown in FIG. 3, the redundant relief function can be realized by a simple structure.

FIG. 8 shows the structure of a semiconductor memory capable of realizing the redundancy repair of the SAM with a simple circuit and layout structure. Reference numeral 1 is a memory cell array for storing data, 2 is a redundant cell array for redundancy relief, and 3 is any one of the memory cell arrays 1 including a plurality of registers R.
It is a serial register that stores row data.

Reference numeral 4 denotes redundant data selecting means composed of transfer gates 4-1 and 4-2 for selecting data on the bit line of the redundant cell array 2, and data stored by the transfer gates 4-1 and 4-2. A redundant serial register composed of a register R, and a SAM selection gate 7 which selectively outputs the signal stored in the serial register 3 to the SAM data bus 20 in response to a selection signal from the SAM decoder 9.

30 is a position program circuit, 13 is a SAM
A predecoder for generating an address given to the SAM decoder 9 from the address input signal 17, 13 is a SAM redundant decoder, and 15 is a SAM data selection circuit.

As described above, column redundancy repair in a semiconductor memory having a pixel align access function when word data is 2 bits is to replace either an even address or an odd address with a redundant cell. Therefore, the redundant cell array 2 includes memory cells for two columns, but the redundant serial register 4 has only one serial register R.

A specific circuit example of the position program circuit 30 is shown in FIG. The components having the same numbers as those of the circuit shown in FIG. 6 are components having the same function. The circuit excluding the inverter 106 is the same as that shown in FIG. 6, and like the fuse program in the circuit shown in FIG. 6, when the repair address is an even number, the fuse is left uncut and the repair address is an odd number. In this case, by blowing the fuse, RSE becomes "1" and RSO becomes "0" when the relief address is an even number, and when the data is transferred from the redundant cell array 2 to the redundant serial register 4, the even side data is registered. Forwarded to R.

When the relief address is odd, RSE is "0" and RSO is "1", and when the data is transferred from the redundant cell array 2 to the redundant serial register 4, the odd data is transferred to the register R.

A specific circuit example of the SAM redundant decoder 14 is shown in FIG. Those having the same numbers as the column redundancy decoder shown in FIG. 5 are components having the same function. The SAM address input 1 has the same configuration as the column redundancy decoder shown in FIG.
7 (S0 to Sm, / S0 to / Sm) is input, and is composed of an n-channel transistor 92, a fuse 91, p-channel transistors 93 and 94, and an inverter 95.

By programming the fuse 91, the output RS is set to "0" when the SAM address input 17 corresponds to the relief address. At the time of SAM access, the SAM address input signal 17 is applied to the SAM decoder 9 via the predecoder 13, and the SAM selection gate 7 is controlled by the selection signal from the SAM decoder to correspond to the SAM address input signal 17. The data of the register 3 is selected, and the SAM data bus 20
Connected to.

The SAM data selection circuit 15 selects the SAM data bus 20 and outputs it as the SAM data 19. SAM
When the address input signal 17 corresponds to the relief address, the output RS of the SAM redundant decoder 14 becomes "0",
Depending on the outputs RSE and RSO of the position program circuit 30, the SAM data selection circuit 15 is operated by the SAM data bus 2
Either one of the data 0 and the data from the redundant serial register 4 is selected and output as the SAM data 19.

That is, when the relief address is an even number, the output RSE of the position program circuit 30 becomes "1" and RSO becomes "0", and at the time of relief, the data from the odd side of the SAM data bus 20 and the redundant serial register 4 is stored. If the relief address is an odd number, the output RSE of the position program circuit 30 is "0" and RSO is "1", and at the time of relief, the even side of the SAM data bus 20 and the data from the redundant serial register 4 are selected. As a result, SAM redundant relief can be realized.

As described above, with the configuration shown in FIG. 8, the number of redundant serial registers can be reduced, and the data output line from the redundant serial register 4 can be reduced. The layout area in the register and data wiring area can be significantly reduced.

FIG. 11 shows a configuration example of a semiconductor memory having a column selection circuit and a redundancy repair circuit having a pixel align access function, and a SAM selection circuit and a redundancy repair circuit.
Shown in.

1 is a memory cell array for storing data,
2 is a redundant cell array for redundancy relief, 3 is a register R
A redundant register selecting means composed of transfer gates 4-1 and 4-2 for selecting data of a bit line of the redundant cell array 2 and a serial register for storing data of any one row of the memory cell array 1 including a plurality of And a register R for storing the data selected by the transfer gates 4-1 and 4-2.

A column decoder 8 generates a selection signal for selecting any row data of the memory cell array 1.
Reference numeral 21 denotes a selection signal synthesizing circuit for generating a selection signal for performing pixel-aligned access from the selection signal from the column decoder 8, 22 denotes a selection signal from the selection signal synthesizing circuit 21 controlled by a signal from the redundancy detecting circuit 11. The selection signal control circuit 5 is a column selection gate for selectively connecting the data of the bit line of the memory cell array 1 to the column data bus 18 in response to a selection signal from the selection signal control circuit 22, and 6 is the redundancy detection circuit 11 to the inverter 23. Is a redundant column select gate which is driven by a signal through the column cell and selectively outputs the data of the bit line of the redundant cell array 2 to the column data bus 18.

Reference numeral 9 is a SAM decoder for generating a selection signal for selecting arbitrary data in the serial register 3, and 7
Is a signal selectively stored in the serial register 3 according to a selection signal from the SAM decoder 9
This is a SAM selection gate that outputs 0.

Reference numeral 10 is a column predecoder for generating an address given to the column decoder 8 from the column address input signal 16, and 11 is for detecting redundancy of the column and controlling redundant data selecting means constituted by 4-1 and 4-2. This is a column redundancy detection circuit for generating a signal for

Reference numeral 13 is a SAM address input signal 17 to S
A SAM predecoder that generates an address to be given to the AM decoder 9, a SAM redundant decoder 14, and a SAM data selection circuit 15 that selects data from the SAM data bus 20 or the redundant serial register 4 and outputs it to the SAM data 19.

In the figure, the column data bus 18 and the SAM data 19 and S are the same as in FIGS. 1, 3 and 8.
The bit width of the AM data bus 20 is 2 bits, and the size of the redundant cell array 2 is 2 columns (the relief address is 1 column). Elements having the same numbers as those shown in FIGS. 1, 3 and 8 are the same elements and perform the same operations.

The circuit and operation of the redundancy detecting circuit 11 different from those of FIGS. 1, 3 and 8 will be described below. A concrete circuit example of the redundancy detection circuit 11 is as shown in FIG. 12, and the (n-1) redundancy decoder 81, the (n) redundancy decoder 82 and the position program circuit 83 are the same as those shown in FIGS. 5 and 6. is there.

The NAND gates 84 to 86 and the inverter 87 perform the operation shown in FIG. 7 similarly to FIG.
E and RO can be output, and RE and R
By applying O to the selection signal control circuit 22 and the inverter, the column selection circuit and the redundancy repair circuit having the pixel align access function shown in FIG. 3 can be realized.

Further, the position program circuit 83 and the inverter 87 allow the same RSE and RS as the circuit shown in FIG.
O can be output and S in the simple configuration shown in FIG.
An AM redundancy repair circuit can be realized.

As described above, with the configuration shown in FIGS. 11 and 12, column redundancy repair and SA
A control signal for M redundancy repair can be generated in the same circuit, and by using this signal, a column selection circuit and a redundancy repair circuit having a pixel align access function with a simple configuration, a SAM selection circuit and a redundancy A semiconductor memory including a relief circuit can be realized.

In the embodiment, the word data width is 2 bits and the internal data bus width is 2 bits as in the conventional example, but the present invention does not depend on the word data width. Needless to say, the same function can be realized even when the word width becomes wider.

[0076]

As described above, according to the present invention, a column select circuit having a pixel align access function can realize a high-speed operation with a simple circuit configuration and also has a pixel align access function having a redundancy repair circuit. A semiconductor memory can be realized with a simple configuration.

Further, also in the image memory having the pixel align access function having the SAM, it can be realized with a simple circuit configuration, and the layout area can be greatly reduced. Therefore, a semiconductor memory having a pixel align access function can be realized with a small chip size, and an inexpensive memory can be provided.

Further, according to the present invention, only one column selection gate is connected to each bit line of the memory cell array, and the number of redundant serial registers can be reduced according to the word data width. The higher the function of the semiconductor memory can be realized with the configuration, and the larger the word data width of the semiconductor memory is, the more the effect of the present invention is exerted.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a column selection unit in an embodiment of a semiconductor memory of the present invention.

FIG. 2 is a functional explanatory diagram of a column decoder and a column selection signal combining circuit in FIG.

FIG. 3 is a configuration diagram of a column selection unit and a column redundancy repair unit in the embodiment.

FIG. 4 is a circuit diagram showing a specific example of a column redundancy detection circuit in FIG.

5 is a circuit diagram showing a specific example of a column redundancy decoder in FIG.

6 is a circuit diagram showing a specific example of a position program circuit in FIG.

FIG. 7 is an operation explanatory diagram of the column redundancy decoder in FIG.

FIG. 8 is a configuration diagram showing a specific example of a SAM selection unit and a SAM redundancy repair unit in the semiconductor memory of the present invention.

9 is a configuration diagram showing a specific example of the position program circuit in FIG.

10 is a configuration diagram showing a specific example of a SAM redundant decoder in FIG.

FIG. 11 is a configuration diagram showing a specific example of a column and SAM selection unit and a redundancy repair unit in the semiconductor memory of the present invention.

12 is a circuit diagram showing a specific example of a column redundancy detection circuit in FIG.

FIG. 13 is a circuit diagram showing a configuration of a conventional column, a SAM selection unit, and a redundancy repair unit.

FIG. 14 is a data array diagram on the screen in the image memory.

FIG. 15 is a circuit diagram showing a configuration of a conventional column selection unit.

[Explanation of symbols]

 1 memory cell array 2 redundant cell array 3 serial register 4 redundant serial register 5 column selection gate 6 redundant column selection gate 7 SAM selection gate 8 column decoder 9 SAM decoder 10 column predecoder 11 column redundancy detection circuit 13 SAM predecoder 14 SAM redundant decoder 15 SAM data selection circuit 16 column address signal 17 SAM address signal 18 column data bus 19 SAM data 20 SAM data bus 21 column selection signal synthesis circuit 22 column selection signal control circuit 23 inverter

Claims (13)

[Claims] 1. A semiconductor memory which performs word data access by a data bus having a plurality of bit widths, and a column decoder which receives a column address for specifying a bit unit position in a column direction and outputs a bit selection signal. Selection signal synthesizing means for synthesizing the input column address and a selection signal from the column decoder corresponding to an address following the column address in the lower direction, and a bit line output of the memory cell array, each of which is independent of each other. 2. A semiconductor memory comprising: a column selection gate controlled by the control circuit and a means for driving the column selection gate by the output of the selection signal synthesizing means. 2. The semiconductor memory according to claim 1, wherein the selection signal synthesizing means comprises an OR operation means. 3. A semiconductor memory comprising a memory cell array and a redundant cell array, wherein word data is accessed by a data bus having a plurality of bit widths, and a column address for designating a bit unit position in the column direction is input to the semiconductor memory unit. A column decoder that outputs a selection signal,
Select signal synthesizing means for synthesizing the input column address and a selection signal from the column decoder corresponding to an address following the column address in the lower direction, and inputting a column address corresponding to a defective memory cell and the column A column redundancy detecting means for detecting an address that follows the address in the lower direction, a column select gate connected to the bit line output of the memory cell array and independently controlled, and connected to the bit line of the redundant cell array. A redundant column selection gate that is independently controlled; a selection signal control unit that controls a selection signal given from the selection signal synthesis unit to the column selection gate by the output of the column redundancy detection unit; and a column redundancy detection unit. A means for controlling the redundant column select gate by the output is provided. Semiconductor memory according to claim. 4. The semiconductor memory according to claim 3, wherein the selection signal synthesizing means comprises an OR operation means. 5. A defective address column redundancy decoder for detecting a column address input corresponding to a defective memory cell by column redundancy detecting means, and a column address following a column address corresponding to the defective memory cell in a lower direction. 4. The semiconductor memory according to claim 3, further comprising one or a plurality of follow-up address redundancy decoders and a position program circuit for designating a bit position in the word data of the defective memory cell. 6. The selection signal control means comprises means for controlling conduction or interruption of the selection signal.
The semiconductor memory described. 7. A semiconductor memory comprising a memory cell array and a redundant cell array, wherein data is accessed by a data bus having a plurality of bit widths, a serial register for storing one row of data in the memory cell array, and a memory cell in the redundant cell array. A redundant data selection means for selecting arbitrary data from one row of data, a redundant serial register for storing the data selected by the redundant data selection means, and a serial address input corresponding to a defective memory cell in the memory cell array are provided. A serial redundancy decoder for detecting, a position program circuit for designating a bit position in word data of a defective memory cell, a means for controlling the redundant data selecting means by an output of the position program circuit, the serial redundancy decoder and the The position program circuit output The serial register or a semiconductor memory, characterized by comprising a serial data selection circuit for selecting and outputting data from the redundant serial register. 8. The semiconductor memory according to claim 6, wherein the redundant data selecting means comprises a plurality of transfer gates connected between a plurality of bit lines of the redundant cell array and the redundant serial register. 9. A semiconductor memory comprising a memory cell array and a redundant cell array, wherein word data is accessed by a data bus having a plurality of bit widths, and a column address for designating a bit-wise position in the column direction is inputted to the semiconductor memory. A column decoder that outputs a selection signal,
Selection signal synthesizing means for synthesizing the input column address and a selection signal from the column data corresponding to an address following the column address in a lower direction,
A column select gate connected to the bit line output of the memory cell array and independently controlled, a redundant column select gate connected to the bit line of the redundant cell array and independently controlled, and a column corresponding to a defective memory cell A column redundancy detecting means for detecting an address input and an address following the column address in the lower direction, and a selection for controlling a selection signal given from the selection signal synthesizing means to the column selection gate by the output of the column redundancy detecting means. From a signal control means, a means for controlling the redundant column selection gate by the output of the column redundancy detection means, a serial register for storing one row of data in the memory cell array, and one row of data in the redundant cell array. Redundant data selecting means for selecting arbitrary data, and the redundant data A redundant serial register for storing the data selected by the selecting means, a means for controlling the redundant data selecting means by the output of the column redundancy detecting means, and a serial address corresponding to a defective memory cell in the memory cell array. A semiconductor memory comprising: a serial redundancy decoder; and a serial data selection circuit for selecting and outputting data from the serial register or the redundant serial register according to the outputs of the serial redundancy decoder and the column redundancy detecting means. . 10. The semiconductor memory according to claim 9, wherein the selection signal synthesizing means comprises an OR operation means. 11. A defective address column redundancy decoder for detecting a column address input corresponding to a defective memory cell by a column redundancy detecting means, and a column address following a column address corresponding to the defective memory cell in a lower direction. 10. The semiconductor memory according to claim 9, further comprising one or a plurality of following address redundancy decoders and a position program circuit for designating a bit position in word data of a defective memory cell. 12. A semiconductor memory according to claim 9, wherein the selection signal control means comprises means for controlling conduction or interruption of the selection signal. 13. The semiconductor memory according to claim 9, wherein the redundant data selecting means comprises a plurality of transfer gates connected between a plurality of bit lines of the redundant cell array and the redundant serial register.