JP3095003B2 - DC-DC converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a switching power supply technology, and more particularly, to a DC-DC converter using synchronous rectification.

[0002]

2. Description of the Related Art Conventionally, a synchronous rectifier has been generally used to increase the power efficiency of a DC-DC converter. As such a conventional technique, for example, Japanese Patent No.
There is a technique described in Japanese Patent No. 43869. That is, a conventional synchronous rectification type DC-DC converter includes a transformer having a primary winding and a secondary winding, and switching means for periodically turning on / off electric power supplied to the primary winding of the transformer. Clamp means for limiting the voltage across the secondary winding of the transformer for a specified period while the switching means is off, rectifying means for rectifying the output of the secondary winding of the transformer, A smoothing means for smoothing a rectified output, wherein the rectifying means includes a field-effect transistor for reflux in which a channel is connected in parallel between secondary windings of the transformer, and a channel in series with a secondary winding of the transformer. A synchronous rectification field-effect transistor, and a gate and a transformer of the synchronous rectification field-effect transistor.
A first capacitor is provided as first waveform shaping means between one end of the next winding and a second capacitor between the gate of the field effect transistor for reflux and the other end of the secondary winding of the transformer. Are provided as second waveform shaping means.

[0003]

However, the synchronous rectifier has a problem that since the turn-off of the freewheeling FET is slow, a large surge voltage is generated between the drain and the source to destroy the FET.

As a conventional technique for solving this problem, for example, there is a technique in which a surge and a spike voltage between the drain and the source of the FET are all consumed by a resistor and a capacitor by a snubber circuit, but the loss increases. Also,
If an FET with a high withstand voltage is used, the FET with a high withstand voltage has a large on-resistance, so that the loss increases. For this reason, a surge protection circuit with as little loss as possible has been demanded.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a low power consumption DC-D which can protect a freewheeling FET (synchronous rectifying FET).
The point is to provide a C converter.

[0006]

The gist of the present invention is to provide a transformer having a primary winding and a secondary winding and an electric power supplied to the primary winding of the transformer. A recirculation FET having a main switch that is periodically turned on and off, and a smoothing means for smoothing a rectified output, wherein a channel is connected in parallel between secondary windings of the transformer; A synchronous rectification FET having a channel connected in series to the winding, a synchronous rectification means for rectifying an output of the secondary winding of the transformer, and a surge voltage between a drain and a source of the freewheeling side FET clamped. And the recirculation side F
A surge clamp circuit that protects the ET from surge voltage,
A primary main switch including an n-channel enhancement MOS transistor having a source grounded, a drain terminal connected in series to the transformer, and a gate terminal connected to a gate control signal source, wherein the surge clamp circuit includes a clamp diode and A reference voltage source, wherein the clamping diode has a cathode connected to a positive terminal of the reference voltage source, an anode connected to a drain terminal of the freewheeling FET and a positive terminal on the secondary side of the transformer, and The source has a plus end connected to the cathode of the clamping diode, a minus end connected to the source terminal of the freewheeling FET and the minus terminal on the secondary side of the transformer, and a secondary winding voltage of the transformer. The reference voltage is generated by rectification and smoothing, and the reference voltage of the freewheeling FET of the synchronous rectification means is adjusted. A rectangular wave VQ4 having a voltage amplitude Vo / D obtained by dividing the output voltage Vo by a predetermined constant D is applied between the in-source and the reference voltage Vr of the reference voltage source is calculated from the value of the amplitude Vo / D of the rectangular wave VQ4. Largely the FE for reflux
T is set to the absolute maximum rated voltage VDSS or less and the amplitude V
A DC-DC converter is characterized in that the relationship of Vo / D <Vr <VDSS is maintained at o / D, reference voltage Vr, and absolute maximum rated voltage VDSS. Also,
The gist of the invention described in claim 2 of the present invention is that the reference voltage source is based on the voltage doubler rectifier circuit that generates a voltage doubler by voltage doubler rectifying the secondary winding voltage of the transformer. 2. A DC-DC converter according to claim 1, further comprising a series dropper for generating a desired reference voltage.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) The configuration of the first embodiment will be described. FIG. 1 is a circuit diagram for explaining a basic configuration of a synchronous rectification type DC-DC converter 100 of the present invention. FIG. 2 is a main waveform in each section of the DC-DC converter 100 of FIG. Synchronous rectification type D of this embodiment
The C-DC converter 100 is a synchronous rectification type forward converter, and includes a surge clamp circuit 10 connected in parallel between the drain and source terminals of the freewheeling FET 6 provided in the synchronous rectification unit 50.

The primary side main switch 4 (n-channel enhancement MOS transistor Q1) has a source grounded, a transformer 3 connected in series to a drain terminal, and a gate control signal source 2 connected to a gate terminal.

The surge clamp circuit 10 includes a clamping diode 11 and a reference voltage source 12. The clamping diode 11 has a cathode connected to the positive terminal of the reference voltage source 12, and an anode connected to the drain terminal (transformer 3) of the n-channel enhancement MOS transistor Q4.
Is connected to the positive terminal on the secondary side. The reference voltage source 12 has a positive terminal connected to the cathode of the clamping diode 11, a negative terminal connected to the source terminal of the n-channel enhancement MOS transistor Q4 (the negative terminal on the secondary side of the transformer 3), and
Is rectified and smoothed to generate a reference voltage Vr.

The synchronous rectification means 50 # 5, 6 #
ET6 (n-channel enhancement MOS transistor Q4) and synchronous rectification FET 5 (n-channel enhancement MOS transistor Q3) are provided.

The freewheeling FET 6 (n-channel enhancement MOS transistor Q4) is grounded at its source, has its drain terminal connected to the anode of the clamping diode 11 (secondary positive terminal of the transformer 3), and has its source terminal connected to a reference voltage source. 12 is connected to the negative terminal (secondary output terminal of the transformer 3), and the gate terminal is a synchronous rectification FET.
5 (n-channel enhancement MOS transistor Q
3) is connected to the drain terminal (minus terminal on the secondary side of the transformer 3).

Synchronous rectification FET 5 (n-channel enhancer)
The source terminal of the MOS transistor Q3) is a ring.
Diverted FET 6 (n-channel enhancement MOS transistor
Source of the transistor Q4) and the minor of the reference voltage source 12.
And the gate terminal is connected to the secondary side
Las terminal and freewheeling FET 6 (n-channel enhancement
Connected to the drain terminal of the MOS transistor Q4).
Have been .

The smoothing means {7, 8} is connected in parallel with the clamping diode 11, and includes a smoothing coil 7 and a smoothing capacitor 8. One end of the smoothing coil 7 is connected to the anode of the clamping diode 11 (the positive terminal on the secondary side of the transformer 3), and the other end is connected to one end of the smoothing capacitor 8. The other end of the smoothing capacitor 8 is connected to the secondary minus side of the transformer 3 (the minus end of the reference voltage source 12).

Next, the operation of the first embodiment will be described. A main switch 4 (n-channel enhancement MOS transistor Q) for switching the current on the primary side of the transformer 3
1) is driven by the gate voltage waveform VG1 generated by the gate control signal source 2. Main switch 4 at this time
(N-channel enhancement MOS transistor Q
The switching cycle of 1) is T, and the ON time of the main switch 4 (the n-channel enhancement MOS transistor Q1) is Ton. The duty ratio D is represented by Ton / T.

Power is transmitted from the primary side to the secondary side of the transformer 3 when the main switch 4 (the n-channel enhancement MOS transistor Q1) is on (on time).
The power transmitted to the secondary side is rectified by the synchronous rectifier 50,
Further, it is converted into direct current by the smoothing means {7, 8} and output to the load 9.

A rectangular wave VQ4 having a voltage amplitude Vo / D obtained by dividing the output voltage Vo by its own ratio D is applied between the drain and source of the freewheeling FET 6 (n-channel enhancement MOS transistor Q4) of the synchronous rectifier 50. Further, a surge voltage VQ4 (peak) is generated in the rectangular wave VQ4, which causes the n-channel enhancement MOS transistor Q4 (main switch 4) to be destroyed.

The surge voltage VQ4 (peak) is applied to the main switch 4 (n-channel enhancement MO) at time t1.
At the moment the S transistor Q1) is turned on,
Since T6 (the n-channel enhancement MOS transistor Q4) and the synchronous rectification FET 5 (the n-channel enhancement MOS transistor Q3) are momentarily turned on at the same time, the reflux FET 6 (the n-channel enhancement MO transistor) is turned on.
A short-circuit current flows through the secondary side of the transformer 3 through the S transistor Q4) and the synchronous rectification FET 5 (n-channel enhancement MOS transistor Q3), and the energy appears as a surge voltage VQ4 (peak). Normally, VQ4 (peak) is a voltage value approximately twice or more as high as VQ4.

In order to suppress this VQ4 (peak),
A surge clamp circuit 10 having a clamping diode 11 and a reference voltage source 12 is connected to a synchronous rectifier 50 in parallel. The reference voltage Vr of the reference voltage source 12 is a rectangular wave VQ.
4 is larger than the value of the amplitude Vo / D, and the freewheeling FET 6 (n
The voltage is set to be equal to or lower than the absolute maximum rated voltage VDSS of the channel enhancement MOS transistor Q4). Amplitude Vo /
D, the reference voltage Vr, and the absolute maximum rated voltage VDSS have the following relationship.

Vo / D <Vr <VDSS (Equation 1)

According to the first embodiment, since the freewheeling FET 6 (synchronous rectification FET) is protected by the surge clamp circuit 10, a conventional surge absorbing circuit using a snubber circuit and a high withstand voltage FET can be omitted. Power consumption can be reduced, and power supply efficiency can be increased.

(Second Embodiment) DC- of the second embodiment
The DC converter 100 will be described. FIG. 3 is a specific circuit of the reference voltage source 12 configured by combining the voltage doubler rectifier circuit and the series dropper 17. DC- shown in FIG.
In the DC converter 100, the secondary winding voltage of the transformer 3 is double-voltage rectified by using a voltage doubler rectifier circuit in the reference voltage source 12 so as to make the amplitude Vo / D of the rectangular wave VQ 4 shown in FIG. 2Vo / D is generated, and a double voltage 2Vo / D is applied to the series dropper 17 in the reference voltage source 12 to generate a desired reference voltage Vr.

According to the second embodiment, since the surge FET 6 (synchronous rectification FET) is protected by the surge clamp circuit 10, the conventional surge absorbing circuit using a snubber circuit and the FET having a high withstand voltage can be omitted. Power consumption can be reduced, and power supply efficiency can be increased.

(Third Embodiment) DC- of the third embodiment
The DC converter 100 will be described. FIG. 4 shows a specific circuit of the reference voltage source 12 configured by combining a voltage doubler rectifier circuit and a resistance dividing circuit. In the reference voltage source 12 shown in FIG. 4, in order to make the amplitude Vo / D of the rectangular wave VQ4 shown in FIG. Double voltage rectification and 2Vo /
D is generated, and a double voltage 2Vo / D is applied to the dividing resistors 18 and 19 in the reference voltage source 12 to generate a desired reference voltage Vr.

As described above, according to the third embodiment,
For example, in the surge clamp circuit 10, the recirculation FET 6 (synchronous
To protect the diverted FET), the conventional snubber circuit
Circuit can eliminate surge absorbers and high withstand voltage FETs.
As a result, power consumption can be reduced,
The efficiency can be improved .

(Fourth Embodiment) DC-
The DC converter 100 will be described. FIG. 5 is a specific circuit of the reference voltage source 12 configured using the auxiliary winding. FIG.
The DC-DC converter 100 is characterized in that a separate winding is provided in the transformer 3 and a voltage taken out through the separate winding is applied to the reference voltage source 12 to generate a desired reference voltage Vr. I have.

As described above, according to the fourth embodiment, if the number of turns of the other winding is optimized, the voltage doubling rectifier circuit becomes unnecessary, and the reference voltage source circuit can be simplified. Also,
Since the freewheeling FET 6 (synchronous rectifying FET) is protected by the surge clamp circuit 10, a conventional surge absorbing circuit using a snubber circuit and a high withstand voltage FET can be omitted, so that power consumption can be reduced and the power supply can be reduced. Efficiency can be improved.

(Fifth Embodiment) DC-Fifth Embodiment
The DC converter 100 will be described. FIG. 6 is a circuit diagram for explaining a basic configuration of the DC-DC converter 100 using the active surge clamp circuit on the primary side.
The DC-DC converter 100 shown in FIG.
The feature is that a stone switching circuit is provided.
The active surge clamp circuit includes an active clamp capacitor 21, an active clamp switch 22
(N-channel enhancement MOS transistor Q
2) A gate control signal source 20 is provided.

One end of the active clamp capacitor 21 is connected to the drain terminal of the active clamp switch 22 (n-channel enhancement MOS transistor Q2), and the other end is the primary positive side of the transformer 3 (the positive side of the input power supply 1). )It is connected to the. The source terminal of the active clamp switch 22 (n-channel enhancement MOS transistor Q2) is connected to the drain terminal of the main switch 4 (n-channel enhancement MOS transistor Q1), and the drain terminal is connected to one end of the active clamp capacitor 21. The gate-source terminal is connected to the output terminal of the gate control signal source 20.

According to the fifth embodiment, the surge clamp circuit
Protect the freewheeling FET 6 (synchronous rectifying FET) on the road 10
As a result, the surge absorption circuit
Circuit and high withstand voltage FET can be omitted, reducing power consumption
Power efficiency can be improved.
You .

In the present embodiment, the present invention is not limited to a DC-DC converter, but can be applied to a switching power supply suitable for applying the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and are suitable numbers for implementing the present invention.
Position, shape, etc. In each drawing, the same components are denoted by the same reference numerals.

[0032]

According to the present invention, since a free-wheeling FET (synchronous rectifying FET) is protected by using a surge clamp circuit, a conventional surge absorbing circuit using a snubber circuit and a FET having a high withstand voltage can be omitted. And the power supply can be made more efficient.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining a basic configuration of a synchronous rectification type DC-DC converter of the present invention.

FIG. 2 is a main waveform in each section of the DC-DC converter of FIG.

FIG. 3 is a specific circuit of a reference voltage source configured by combining a voltage doubler rectifier circuit and a series dropper.

FIG. 4 is a specific circuit of a reference voltage source configured by combining a voltage doubler rectifier circuit and a resistance dividing circuit.

FIG. 5 is a specific circuit of a reference voltage source configured using an auxiliary winding.

FIG. 6 is a circuit diagram for describing a basic configuration of a DC-DC converter using an active surge clamp circuit on a primary side.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input power supply 2 ... Gate control signal source 3 ... Transformer 4 ... Main switch (n-channel enhancement MOS transistor Q1) 5 ... Synchronous rectification FET (synchronous rectification means) (n-channel enhancement MOS transistor Q3) 6 ... Reflux FET ( Synchronous rectification means) (n-channel enhancement MOS transistor Q4) 7 ... Smoothing coil (smoothing means) 8 ... Smoothing capacitor (smoothing means) 9 ... Load 10 ... Surge clamp circuit 11 ... Clamp diode 12 ... Reference voltage source 13 ... DC cut Capacitors 14, 15 Diode 16 Smoothing capacitor 17 Series dropper 18, 19 Dividing resistor 20 Gate control signal source 21 Active clamp capacitor 22 Active clamp switch 50 Synchronous rectifier 100 DC-DC connector Inverter Q2 ... n-channel enhancement MOS transistor (switch active clamp) Q3 ... n-channel enhancement MOS transistor (synchronous rectification FET) Q4 ... n-channel enhancement MOS transistor (ring diverted FET)

Claims (2)

(57) [Claims] 1. A transformer having a primary winding and a secondary winding, a main switch for periodically turning on / off electric power supplied to the primary winding of the transformer, and a smoothing unit for smoothing a rectified output. And a synchronous rectification FET having a channel connected in series to the secondary winding of the transformer, and a rectifying FET having a channel connected in parallel between the secondary windings of the transformer. Synchronous rectification means for rectifying the output of the secondary winding of the transformer, a surge clamp circuit for clamping a surge voltage between the drain and the source of the recirculation side FET to protect the recirculation side FET from a surge voltage, and a source ground. And a primary side main switch including an n-channel enhancement MOS transistor having a drain terminal connected in series to the transformer and a gate terminal connected to a gate control signal source. The surge clamp circuit includes a clamping diode and a reference voltage source. The clamping diode has a cathode connected to a positive terminal of the reference voltage source, and an anode connected to the drain terminal of the freewheeling FET and the transformer. The reference voltage source is connected to the next positive terminal, the positive terminal of the reference voltage source is connected to the cathode of the clamping diode, and the negative terminal is the ring terminal.
The reference terminal is connected to the source terminal of the diversion FET and the negative terminal on the secondary side of the transformer and rectifies and smoothes the secondary winding voltage of the transformer to generate a reference voltage. Voltage amplitude Vo obtained by dividing output voltage Vo between drain and source by predetermined constant D
/ D square wave VQ4 is applied, and the reference voltage Vr of the reference voltage source is larger than the value of the amplitude Vo / D of the square wave VQ4, and the absolute maximum rated voltage VDSS of the freewheeling FET is applied.
Vo / D <Vr <VDSS at the amplitude Vo / D, the reference voltage Vr, and the absolute maximum rated voltage VDSS.
A DC-DC converter characterized by the following relationship: 2. A voltage doubler rectifier circuit that generates a doubled voltage by voltage doubler rectifying a secondary winding voltage of the transformer, and a series that generates a desired reference voltage based on the doubled voltage. The DC-DC converter according to claim 1, further comprising a dropper.