JP3098146B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a DRAM [Dynamic Ran
dom Access Memory] and EEPROM [Electrically Eras]
and a non-volatile semiconductor memory device using a ferroelectric material.

[0002]

2. Description of the Related Art Nonvolatile semiconductor memory devices (NVDRAM)
[Non-Volatile Dynamic Random Access Memory]) mainly includes two types: a combination of a DRAM and an EEPROM, and a type using a ferroelectric.

A nonvolatile semiconductor memory device combining a DRAM and an EEPROM is disclosed in "A 256k-bit
Non-Volatile PSRAM with Page Recall and Chip Stor
e ", 1991 Sym. VLSI circuit Dig. Tech. papers, M
ay, paragraphs 91-92, provide further explanation. During normal operation, this nonvolatile semiconductor memory device accesses a DRAM provided with volatile memory cells in a DRAM mode, and immediately before power-off, stores data in the DRAM in a nonvolatile mode in a store mode. It is evacuated to an EEPROM having memory cells. Therefore,
During normal operation, volatile DRAM can be accessed at high speed, and when power is turned off, this data can be stored and held in a nonvolatile EEPROM. The data stored in the nonvolatile EEPROM can be read out to the DRAM again in the recall mode.

On the other hand, the following non-volatile semiconductor memory device using a ferroelectric substance is described in the following document.

(1) "An Experimental 512-bit Non-Volat"
ile Memory with Ferroelectric Storage Cell "IEEE J
ournal of Solid State Circuits, vol.23, pp.1171-11
75, October, 1988. (2) "A Ferroelectric DRAM Cell for High-Density NV
RAM's ", IEEE ElectronDevice Lett., Vol. 11, pp. 454-4
56, October, 1990. The nonvolatile semiconductor memory device using this ferroelectric is Y1
(It is a common name for ferroelectric ceramics that have been developed in recent years and have little rewrite deterioration, and their components are not disclosed.), PZT
(PbZrTiO ₃ [lead zirconate titanate]), PL
A memory element is used for a memory cell with a ferroelectric thin film having a perovskite type crystal structure such as ZT (PbLaZrTiO ₃ ) or PbTiO ₃ interposed therebetween. When an AC voltage is applied to this capacitive element, the polarization state of the ferroelectric material interposed between the capacitive elements exhibits a hysteresis characteristic as shown in FIG. That is, when a positive electric field is applied to the ferroelectric in the state of point A, which is not initially polarized, the polarization state moves to the point B, but when this electric field is removed, it returns only to the point C and positive remanent polarization occurs . This remanent polarization disappears when a negative coercive electric field is applied, and when the negative electric field is further increased, the polarization state is reversed and moves to the point D. However, when the electric field is removed again, only up to the point E. Negative remanent polarization occurs without returning. Thus, by inverting the polarization of the ferroelectric to generate a positive or negative remanent polarization, data can be stored in a non-volatile manner. Further, when only an operation of applying or removing a positive or negative electric field is performed, the polarization state of the ferroelectric moves only between the points B and C or between the points D and E. Therefore, no polarization reversal occurs, and data can be stored as volatile like a normal DRAM.

[0006] Such a nonvolatile semiconductor memory device has a D
Since the number of elements constituting a memory cell can be reduced as compared with a combination of a RAM and an EEPROM, there is an advantage that a cell area can be reduced and high integration can be achieved.

The structure and operation of a nonvolatile semiconductor memory device combining a DRAM and an EEPROM are widely known and described in the above-mentioned literature. The structure and operation of a non-volatile semiconductor memory device using one ferroelectric material will be specifically described below, taking as an example the case of a two-transistor / cell system which is resistant to process variations .

As shown in FIG. 10, this nonvolatile semiconductor memory device has a number of word lines WL and corresponding plate lines PT, and is connected to a word line decoder 31 and a plate line decoder 32, respectively. I have. Further, it has a number of bit line pairs, bit bars, and is connected to the sense amplifier 33 for each pair. However, in the figure, this bit line pair bit, bit bar and the sense amplifier 33 are connected by one.
Only pairs are shown.

A memory cell 34 is arranged at each intersection where the word line WL and the corresponding plate line PT intersect the bit line pair bit, bit bar. However, in the figure, only one memory cell 34 is shown. This memory cell 34 has two capacitive elements C1, C2.
And two select transistors Q1 and Q2. One terminal of each of the capacitance elements C1 and C2 is connected to a bit line pair bit and bi via selection transistors Q1 and Q2, respectively.
t bar, and the other terminal is connected to the plate line P
Connected to T. Also, the selection transistors Q1, Q2
Are connected to the word line WL.

In the nonvolatile semiconductor memory device having the above structure, the word line decoder 31 and the plate line decoder 32 select one word line WL and one plate line PT based on the address input to the address buffer 35, and control signal Access to the memory cell 34 is performed in a mode based on the control signal input to the input buffer 36. That is, in the DRAM mode for accessing data stored as volatile, the DRAM mode timing control circuit 37 controls the timing. In the recall mode for reading and rewriting data stored as nonvolatile, the recall mode timing control is performed. In the store mode controlled by the circuit 38 to perform writing for storing data in a non-volatile manner, the access operation is performed under the control of the store mode timing control circuit 39. The data to be accessed is input / output to / from the outside via the data I / O interface 40.

The store mode timing control circuit 39
11 shows the data write operation in the store mode in FIG.
This will be described in detail with reference to FIG. For example, when writing data “0”, as shown in FIG. 11, 0 V is applied to the bit line bit and 5 V is applied to the bit line bit bar.
(Power supply voltage VCC) and the word line WL
Is activated, and 0V → 5
A voltage pulse that changes from V to 0 V is applied. Then, the ferroelectric of one capacitive element C1 changes the polarization state from point C or E in FIG. 9 to point B → C, and the ferroelectric of the other capacitive element C2 changes the polarization state. D point → E point → D
Change it to a point. Therefore, even if the voltage is subsequently removed, remanent polarization occurs at the points C and E in the ferroelectrics of these capacitive elements C1 and C2, and the data "0" is stored as non-volatile.

When writing "1" data, as shown in FIG. 12, a bit line pair bit, bi
A voltage of 5 V and 0 V opposite to the above is applied to t-bar. Thereafter, when the word line WL is activated and a voltage pulse is applied to the plate line PT in the same procedure, the capacitance element C
In the ferroelectrics 1 and C2, remnant polarization occurs at points E and C, which are opposite to the above, whereby data "1" is stored as non-volatile. Next, the data read operation in the recall mode in the recall mode timing control circuit 38 will be described in detail with reference to FIG. In this case, the bit line pair bit, bit bar is pre-charged to a potential of 0 V, and then opened. Then, the word line WL is activated, and the voltage of the plate line PT is set to 0V.
When the voltage is changed to 5 V, for example, when data of "0" is stored, the polarization state of the ferroelectric of one capacitor C1 changes from point C to point B in FIG.
The polarization state of the ferroelectric material changes from point E to point B. Then, in the case of the ferroelectric material of the other capacitive element C2, the polarization state is inverted, so that the potential of the bit line bit bar connected thereto becomes several hundred mV higher than the potential of the bit line bit. Therefore, if the potential difference between the bit line pair bit and bit bar is sensed by the sense amplifier 33,
Data stored as non-volatile can be read. However, in this case, the polarization states of the ferroelectrics of the capacitors C1 and C2 are both moved to the point B, and the data stored as non-volatile is lost, so that destructive reading is performed. Therefore, in this recall mode, the sense amplifier 33 sets the bit line pair bit, bit bar to 0V.
After the potential is determined to be 5 V and 5 V, the read data is stored as non-volatile by applying a voltage pulse that changes from 0 V to 5 V to 0 V to the plate line PT in the same procedure as in the store mode. Rewriting can also be performed. After this, the plate line PT is set to 0, for example.
If the voltage is maintained at V, the determined potential of the bit line pair bit, bit bar is accumulated as a charge in the memory cell 34, and storage in a DRAM mode described later is also performed. In this recall mode, the potential difference generated between the bit line pair bit and the bit bar is proportional to the remanent polarization and inversely proportional to the bit line capacitance. Therefore, the larger the remanent polarization and the smaller the bit line capacitance, the larger the potential difference is obtained. It can be understood that the detection by the method becomes easy. The access in the DRAM mode by the DRAM mode timing control circuit 37 is performed in the same procedure as that of a normal DRAM with 0 V or 5 V applied to the plate line PT. Then, the polarization state of the ferroelectric in the capacitors C1 and C2 moves only between the points D and E or between the points B and C in FIG. 9 and does not involve polarization inversion. Similarly, data stored as volatile can be read and written only by the charges accumulated in the capacitors C1 and C2, and a refresh operation can be performed.

Although only a nonvolatile semiconductor memory device using a ferroelectric substance of the two-transistor / cell system has been described here, it is suitable for high integration as described in Japanese Patent Application No. 4-324506. The same applies to a non-volatile semiconductor memory device using a ferroelectric material of the one-transistor / cell system.

[0014]

By the way, both types of nonvolatile semiconductor memory devices can be operated only in a store mode in which data is stored as nonvolatile and a recall mode in which the data is read.

However, in the case of a nonvolatile semiconductor memory device combining a DRAM and an EEPROM, the EEPROM
Since the number of times of rewriting of the PROM is limited to about 100,000 times, frequent rewriting immediately ends its life.
On the other hand, also in the case of a nonvolatile semiconductor memory device using a ferroelectric material, the number of times that the ferroelectric material used for the capacitance elements C1 and C2 of the memory cell 34 can perform polarization inversion is limited, and the recall / store operation is not performed. Since it is limited to about 10 ⁸ to 10 ¹² times, if continuous access is performed at a cycle period of about 10 MHz, the life of the memory cell 34 will be exhausted in several days. As a result, remanent polarization is large and polarization reversal is possible.
Research on materials with a large number of times has been conducted.

Therefore, in the case of a nonvolatile semiconductor memory device combining a DRAM and an EEPROM, as described above, the DRAM operates in the DRAM mode during normal operation.
Only when the power is turned off, the data in the DRAM is saved in the EEPROM in the store mode only before the power is turned off, and the data is read out to the DRAM again in the recall mode when the power is turned on the next time. Is not increasing. On the other hand, in the case of a nonvolatile semiconductor memory device using a ferroelectric material, access is performed without polarization inversion in the DRAM mode during normal operation, and data in the memory cell 34 is stored as nonvolatile in the store mode only when the power is off. At the same time, this data is called up in the recall mode only at the time of the first reading after the next power-on, so that the number of accesses involving polarization reversal is minimized.

These nonvolatile semiconductor memory devices are provided with control signals (non-volatile enable signal NE, chip enable signal CE,
By changing the combination of the output enable signal OE bar, the write enable WE bar, the refresh signal RFSH bar, etc.), the store mode,
The access in the recall mode and the access in the DRAM mode are respectively switched, and the refresh operation in the DRAM mode is performed. However, for the refresh operation, the pseudo SRA used for a normal DRAM is used.
By providing a self-refresh function of M [Static RAM], a refresh operation can be automatically performed in the DRAM mode. In this self-refresh function, for example, by activating an output enable signal OE bar or a refresh signal RFSH bar, an internal address counter automatically generates an address based on a clock signal and sequentially performs a refresh operation of each memory cell. Thus, the peripheral circuit configuration of the memory device can be simplified, and the control of the refresh operation can be simplified.

However, a relatively large current of about 200 μA is required for the refresh operation in the DRAM mode, and especially for a nonvolatile semiconductor memory device expected to be used in IC cards and portable electronic devices. There is a strong demand to reduce this power consumption. However, there is a limit to reducing the power consumption in this refresh operation by complicating the internal circuit or improving the semiconductor manufacturing process, and when the specifications of the data retention current are set strictly, Although the power consumption can be reduced by reducing the margin, a new problem arises in that the yield of the product is deteriorated accordingly.

This problem occurs when the nonvolatile semiconductor memory device is configured as a single memory device,
This is common to all cases such as the case where it is configured as a memory module of a chip microcomputer.

The present invention has been made to solve such a problem of the prior art, and when a refresh operation by a self-refresh function continues for a predetermined time or longer, data is automatically stored in a nonvolatile memory cell. It is an object of the present invention to provide a nonvolatile semiconductor memory device which can be made to stand by or store data in a nonvolatile manner and prevent an increase in power consumption due to a refresh operation. So
RAS bar with self-refresh function
The present invention can also be applied to a CAS bar type DRAM.

[0021]

A nonvolatile semiconductor memory device according to the present invention comprises a volatile memory cell requiring a refresh operation to maintain the stored content and a nonvolatile memory cell capable of rewriting the stored content. Address generation means for automatically generating an address of each memory cell sequentially based on a clock signal in a nonvolatile semiconductor memory device having memory cells having both volatile and nonvolatile storage functions. Self-refresh means for performing a refresh operation by sequentially rewriting the storage contents of volatile memory cells or memory cells storing the storage contents as volatile based on the address generated by the address generation means; Refresh timing means for timing the time during which the refresh operation is continuously performed; A self-store start means for determining whether or not the time of the refresh operation measured by the fresh timer has exceeded a predetermined time; and a refresh operation by the self-refresh means when the self-store start means determines that the predetermined time has elapsed. A store operation of stopping and sequentially transferring the stored contents of the volatile memory cells to the nonvolatile memory cells based on the address generated by the address generating means, or storing each of the memory cells stored as volatile. Since the self-store means for performing a store operation for sequentially storing the stored contents in the same memory cell in a nonvolatile manner is provided, the above object is achieved.

In such a nonvolatile semiconductor memory device,
Clock signal supply means for inputting or generating and supplying two types of clock signals having different periods for automatically generating the address; and when the self-refresh means performs a refresh operation, the clock signal supply means A clock signal switching means for supplying a longer clock signal and for supplying a clock signal with a shorter cycle from the clock signal supply means when the self-store means performs a store operation may be provided.

The nonvolatile semiconductor memory device of the present invention includes a volatile memory cell that requires a refresh operation to maintain the stored content and a nonvolatile memory cell whose stored content can be rewritten, or Generating means for automatically generating an address of each memory cell sequentially based on a clock signal in a nonvolatile semiconductor memory device including a memory cell having both a volatile and a nonvolatile storage function;
Based on the address generated by the address generating means, a refresh operation is performed by sequentially rewriting the storage contents of the memory cells stored as volatile, and a store operation for sequentially storing volatile data as nonvolatile is performed. and self store means for performing, to measure a period of time the self-store unit is continuously performed store operation,該Se
If the store unit does not perform the store operation continuously
Is a self-store timer for resetting the time, means for determining whether or not the time of the store operation measured by the self-store timer has exceeded a predetermined time, and means for determining whether the self-timer has exceeded the predetermined time. Since the refresh operation by the storing means and the means for stopping the storing operation are provided, the above-mentioned object is achieved.

In this nonvolatile semiconductor memory device and the above-described nonvolatile semiconductor memory device, when the self-store means performs a store operation, the memory contents of the nonvolatile memory cell or the memory cell stored as nonvolatile are stored. And a recall request signal generating means for generating a recall request signal for requesting a recall operation for reading the data.

[0025]

A device having a volatile memory cell and a nonvolatile memory cell includes, for example, a DRAM and an EEPROM.
There is a nonvolatile semiconductor memory device that combines the above. As a device having a memory cell having both volatile and nonvolatile storage functions, for example, there is a nonvolatile semiconductor memory device using a ferroelectric material.

The address generating means sequentially and automatically generates addresses of the respective memory cells based on a clock signal input from the outside or a clock signal generated internally. Then, the self-refresh means and the self-store means perform a refresh operation and a store operation based on the address.

The self-refresh means automatically performs a refresh operation in order to maintain volatile storage contents in the DRAM mode of the nonvolatile semiconductor memory device, and is usually external (or another module in the chip).
This refresh operation is performed when the control signal input from the device matches a predetermined condition. The refresh timer measures the time during which the self-refresh unit continuously performs the refresh operation. The refresh operation by the self-refresh means may be of any type, such as one that is performed during an idle time of access or one that stops access during refresh of all rows, as long as an address is automatically generated internally. However, in any of the methods, if there is an access by reading or writing even once, the refresh operation is temporarily interrupted at that time and is not continued. The continuity of the refresh operation can be determined for all the memory cells at once, or can be determined for each block by dividing all the memory cells into a plurality of blocks. The refresh timer means not only measures the time independently, but also counts the refresh operation time by counting a clock signal, counting the number of address changes generated by the address generating means, and the like. Can be.

The self-store start means determines whether or not the refresh operation time measured by the refresh timer means has exceeded a predetermined time. Here, the fact that the time of the refresh operation has exceeded the predetermined time indicates that the nonvolatile semiconductor memory device or the corresponding block in the nonvolatile semiconductor memory device has not been accessed at all for the predetermined time, and in this case, Is likely not to be accessed for the time being. Therefore, when the self-store start means determines that the time of the refresh operation has exceeded the predetermined time, the self-store means stops the refresh operation by the self-refresh means, and based on the address generated by the address generation means. The store operation of the memory cell is performed. Then, the stored contents of the volatile memory cells are sequentially transferred to and stored in the nonvolatile memory cells, or the stored contents of the memory cells stored as volatile are sequentially stored again as nonvolatile in the same memory cell. Thus, the stored contents can be held without performing the refresh operation.

As a result, according to the nonvolatile semiconductor memory device of the present invention, when the storage contents of the volatile memory cells or the memory cells stored as volatile are not accessed for a certain time or more, the self-store means Thus, the data is automatically transferred to a non-volatile memory cell or stored in a non-volatile memory cell, so that the refresh operation by the self-refresh means can be made unnecessary. Therefore, it is possible to automatically shift the storage content that is unlikely to be directly accessed thereafter to the nonvolatile storage, and prevent the refresh operation with large power consumption from continuing for a long time. Note that the number of rewrites of the EEPROM or the ferroelectric is increased by the store operation of the self-store means. For example, if the limit of the number of rewrites is 10 8 times or more, the predetermined time set in the self-store start means is reduced. Even for one second, operation for about 10 years can be guaranteed.

In the refresh operation by the self-refresh means, the power consumption decreases as the cycle becomes longer.
The refresh operation should be performed in a cycle as long as possible within a prescribed refresh cycle. However, during the store operation by the self-store means, access from the outside cannot be performed, so that it is necessary to complete the operation quickly.

Therefore, according to the second aspect of the present invention, when the clock signal switching means switches the clock signal from the clock signal supply means and the self-refresh means performs the refresh operation, the clock signal having the longer cycle is generated by the address generation. When the self-store means performs a store operation, a clock signal having a shorter cycle is supplied to the address generation means to change the address generation speed, thereby realizing the above-mentioned request.

Once the self-store means has performed a store operation, it enters a standby state after completing the store operation and does not perform a refresh operation for holding volatile data. Since the data has been destroyed, writing in the DRAM mode is possible thereafter, but reading in the DRAM mode cannot be performed. Therefore, reading must be performed in the recall mode for nonvolatile storage. Accordingly, if the recall request signal generating means generates a recall request signal when the self-store means performs a store operation, the external device or another internal module may generate the recall request signal. Access control can be facilitated.
Also, other than recall operation is prohibited by the recall request signal.
The storage contents can be protected by a configuration in which the storage is stopped.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 8 show an embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a control section of a nonvolatile semiconductor memory device, and FIG. 2 shows a specific configuration of an address counter. FIG. 3 is a partial circuit block diagram showing a specific configuration of an address selection circuit, FIG. 4 is an address map of a memory unit, FIG. 5 is a block diagram showing a specific configuration of a write control circuit, and FIG. FIG. 7 is a block diagram showing a specific configuration of the signal generation circuit, FIG. 7 is a block diagram showing a specific configuration of the comparison circuit, and FIG. 8 is a time chart showing an operation of the nonvolatile semiconductor memory device.

In the present embodiment, a nonvolatile semiconductor memory device using a ferroelectric will be described. The nonvolatile semiconductor memory device may be configured as a single memory device or as a memory module of a one-chip microcomputer.

The memory section 1 of the nonvolatile semiconductor memory device shown in FIG. 1 comprises a memory cell array, a sense amplifier, a data I / O interface and the like. It is assumed that the memory cell array includes a large number of memory cells 34 of, for example, the two-transistor / cell type shown in FIG. However,
This memory cell array may be of the one-transistor / cell type or the like. Also, if the memory unit 1
Even in a nonvolatile semiconductor memory device or the like in which a RAM and an EEPROM are combined, the present invention can be implemented in substantially the same manner.

External addresses AEX0-
AEXn is sent to the driver / decoder circuit 4 via the external address transition detection circuit 2 and the address selection circuit 3. This nonvolatile semiconductor memory device has an address counter 5. As shown in FIG. 2, the address counter 5 is composed of n D-type flip-flops 5a. The address counter 5 sends a clock signal input from the outside to the clock input of the first-stage D-type flip-flop 5a. The output Q of the flip-flop 5a is sequentially connected to the clock input of the next stage. The reset signal input from the outside corresponds to the reset terminal RESET of the D-type flip-flop 5a of each stage.
It is sent to the bar. Although not shown, the inverted output Q of the D-type flip-flop 5a at each stage is connected to the data input D of the same D-type flip-flop 5a. Therefore, this address counter 5
When a clock signal is input from the outside, the output Q of the D-type flip-flop 5a at each stage becomes a signal obtained by dividing the frequency of the clock signal by two, and the value is sequentially incremented by the output Q and the clock signal. Internal address A0
~ An can be generated. As shown in FIG. 1, an initialization pulse signal PON which becomes H level when the power is turned on is input to the address counter 5 through an inverter circuit 9 as a reset signal. To An are reset to an initial value (all bits are at L level). The internal addresses A0 to An output from the address counter 5 are input to the address selection circuit 3 via the internal address transition detection circuit 6. The external address transition detection circuit 2 sends the external addresses AEX0 to AEXn to the address selection circuit 3 when the external address activation signal φEXA is active, detects that the external addresses AEX0 to AEXn have changed, and controls the word line control. This is a circuit that sends an address transition signal indicating this to the circuit 7 and the plate line control circuit 8. When the internal address activation signal φINA is active, the internal address transition detection circuit 6 sends the internal addresses A0 to An to the address selection circuit 3 and detects that these internal addresses A0 to An have changed, and detects the change in the word. This is a circuit that sends an address transition signal indicating this to the line control circuit 7 and the plate line control circuit 8. Word line control circuit 7
Receives the address transition signal from the external address transition detection circuit 2 or the internal address transition detection circuit 6 and controls the driver / decoder circuit 4 to control the word line W of the memory unit 1.
L, and a plate line control circuit 8
When this address transition signal is received during the store operation,
This is a circuit that controls the driver / decoder circuit 4 to drive the plate line PT of the memory unit 1.

FIG. 3 shows a specific configuration of an input / output circuit for one bit of an address in the address selection circuit 3.
The one-bit external address AEXi is input to the buffer circuit 3b via the external address selection circuit 3a, and the one-bit internal address Ai is input to the same buffer circuit 3b via the internal address selection circuit 3c. ing. When the external address activation signal φEXA is active (H level), the external address selection circuit 3a turns on the P-channel and N-channel FETs and sends the external address AEXi to the buffer circuit 3b. When the internal address activation signal φINA is active, the internal address selection circuit 3c turns on the P-channel and N-channel FETs, and
i is sent to the buffer circuit 3b. Therefore, when either the external address activating signal φEXA or the internal address activating signal φINA is active, the address selecting circuit 3 uses one of the external addresses AEX0 to AEXn and the internal addresses A0 to An as a selected address to select a driver. / Decoder circuit 4.

The driver / decoder circuit 4 shown in FIG.
This is a circuit that decodes the address sent from the address selection circuit 3 and drives the corresponding word line WL and plate line PT in the memory unit 1 under the control of the word line control circuit 7 and the plate line control circuit 8. Here, the internal address activating signal φINA is a signal generated by a control signal generating circuit 10 which receives an external refresh signal RFSH bar.
When FSH bar becomes active (L level), internal address activation signal φINA also becomes active (H level).
It is said. Further, the control signal generating circuit 10 also generates an internal refresh signal REF obtained by inverting the refresh signal RFSH bar. The refresh signal RFSH bar is input from an external terminal when the nonvolatile semiconductor memory device is configured as a single memory device, and is applied to a pad on the chip when configured as a memory module such as a one-chip microcomputer. Can be entered from The external address activation signal φEXA is a signal that becomes active when there is an external access, and is generated by a control circuit (not shown).

With the above configuration, when the external address activation signal φEXA is active, the external addresses AEX0 to AEX0
EXn is sent to the driver / decoder circuit 4 via the external address transition detection circuit 2 and the address selection circuit 3, and the memory cells in the memory unit 1 corresponding to the external addresses AEX0 to AEXn are accessed. At this time, based on the address transition signal generated by the external address transition detection circuit 2, the word line control circuit 7 and the plate line control circuit 8 connect the word line WL of the memory unit 1 with a mode corresponding to a control signal (not shown). The plate line PT is driven. When the internal address activation signal φINA is active, the internal addresses A0 to An are sent to the driver / decoder circuit 4 via the internal address transition detection circuit 6 and the address selection circuit 3, and the internal addresses A0 to An Are accessed in the memory unit 1 corresponding to the. At this time, based on the address transition signal generated by the internal address transition detection circuit 6, the word line control circuit 7 and the plate line control circuit 8 connect the word line WL of the memory unit 1 with a mode corresponding to a control signal (not shown). The plate line PT is driven. Therefore, in the case of a normal external access, the external address activation signal φEXA becomes active, and the memory cells of the memory unit 1 are accessed in various modes based on the external addresses AEX0 to AEXn sent from the outside. Is performed. When the refresh signal RFSH becomes active, the internal address activation signal φINA becomes active, and the internal address A sequentially generated by the address counter 5 is generated.
The refresh operation is performed on the DRAM mode memory cells of the memory unit 1 based on 0 to An.

The internal address A of the most significant bit among the internal addresses A0 to An generated by the address counter 5
n is the second through the first counter 11 and the AND circuit 12
The data is input to the counter 13. And
The other input of the AND circuit 12 includes the first counter 1
1 output is connected. These counters 11, 1
3 counts each time the input pulse falls,
The circuit changes the output from the L level to the H level when the predetermined number of times set for each is completed.
These counters 11 and 13 are refreshed when the internal refresh signal REF generated by the control signal generation circuit 10 becomes inactive (L level), that is, the refresh signal RFSH becomes inactive (H level). When the operation is not performed, the internal count number is reset, and the output is returned to the L level.
Therefore, the first counter 11 counts once each time the internal address An falls, that is, every time the internal addresses A0 to An cycle and all the addresses are output once, and the refresh signal RFSH bar becomes active. During this period, the number of times a series of refresh operations are continuously performed is counted. In addition, the second counter 13 has a function of the first counter.
When the counter 11 finishes counting the predetermined number of times and outputs the H level, it starts counting, and the internal address A
Count the number of times n falls.

The output of the first counter 11 is
4 and when this output goes high, the latch circuit 1
4 is set to H level. Further, the output of the second counter 13 is connected to the inverter circuit 15 and the AND circuit which receives the internal refresh signal REF on one side.
Sent to the latch circuit 14 via the
When the output of the D circuit 16 becomes L level, the output of the latch circuit 14 is reset to L level. Therefore, the latch circuit 14 outputs the H level when the first counter 11 counts the refresh operation a predetermined number of times, and thereafter until the second counter 13 finishes counting the predetermined number of times, or when the internal refresh signal REF is output. This H level output is maintained until it becomes inactive (L level).

The output of the latch circuit 14 is sent to the plate line control circuit 8. The plate line control circuit 8 is set when the output of the latch circuit 14 goes to the H level, and sets the plate line PT to, for example, 0
V was fixed to V and the refresh operation was performed.
The driving is switched to a store operation by driving a voltage pulse that changes from V → 5V → 0V. Therefore, by driving the plate line PT of the plate line control circuit 8, the storage contents of each memory cell where the refresh operation has been repeatedly performed up to that time are sequentially switched to nonvolatile storage based on the internal addresses A0 to An. This series of store operations is repeated until the second counter 13 finishes counting. This store operation may be performed only once for all of the internal addresses A0 to An. However, as long as the number of times of rewriting of the memory cell permits, the store operation is repeated a plurality of times to perform more reliable storage. Therefore, the store operation is repeated the number of times set in the second counter 13. At the time of the store operation, if the output of the data I / O interface in the memory unit 1 is set to a high impedance state, the data outputs from the plurality of memory units 1 can be connected by a wired OR. become.

The output of the second counter 13 is also sent to a timer stop latch circuit 17, and when this output goes high, the output of the timer stop latch circuit 17 is set to high level. Further, the timer stop latch circuit 17 outputs the internal refresh signal RE.
When F becomes inactive (L level), it is reset and the output returns to L level. The output of the timer stop latch circuit 17 is sent to the recall request latch circuit 19 via the OR circuit 18 to which the initialization pulse signal PON is input. The recall request latch circuit 19 sets the initialization signal PON to H level when the output of the timer stop
When the level becomes high, it is set in response to the H level output of the OR circuit 18 and outputs an L level recall request signal RC bar via the output buffer 20.
Further, this recall request latch circuit 19
Is reset by a recall completion signal output when a control circuit (not shown) corresponding to the recall mode timing control circuit 38 shown in (1) has completed the recall operation, and outputs an H level refresh request signal RF via the output buffer 20. It has become. If the output of the output buffer 20 is configured to have an open drain configuration, current can be hardly consumed unless an external device or the like accesses it.

The output of the timer stop latch circuit 17 is also sent to a timer circuit 23 via an inverter circuit 21 and an AND circuit 22. When the output of the AND circuit 22 is at the H level,
This is a circuit that generates a first clock signal T1 having a long cycle (for example, a 16 μsec cycle) and a second clock signal T2 having a short cycle (for example, a 1 μsec cycle). AND circuit 2
2, the internal refresh signal REF generated by the control signal generation circuit 10 and the signal A always at the H level are input to the output of the inverter circuit 21. Therefore, the timer circuit 23 generates the clock signals T1 and T2 only while the internal refresh signal REF is active (H level) and the timer stop latch circuit 17 is reset and outputs L level. become. That is, when the second counter 13 finishes counting the predetermined number of times and the output of the timer stop latch circuit 17 becomes H level, the timer circuit 23 stops generating the clock signals T1 and T2.

Clock signal T generated by timer circuit 23
1 and T2 are sent to the address counter 5 via the selection circuit 24. The selection circuit 24 is a multiplexer that selects one of the clock signals T1 and T2 and supplies it to the address counter 5, and the output of the latch circuit 14 is connected to a control input. When the output of the latch circuit 14 is at L level, a clock signal T1 having a long cycle is sent out, and when the output of the latch circuit 14 is at H level, a clock signal T2 having a short cycle is sent out. Accordingly, during the refresh operation, the address counter 5 generates the internal addresses A0 to An at a low speed based on the clock signal T1 having a long cycle, so that waste of power consumption due to excessive refresh operation can be eliminated, and At the time of the store operation when the counter 11 has finished counting the refresh operation a predetermined number of times, the internal addresses A0 to An are generated at high speed based on the clock signal T2 having a short cycle, so that the store operation can be completed quickly. In some circumstances, the clock signal T1 may be changed to the clock signal T2.
It is also possible to make the cycle the same as or shorter than this.

As shown in FIG. 4, the memory section 1 has a writable area RW for treating an address space like a RAM.
And a write-protected area RO handled like a PROM, the write-protected area RO is used during normal use.
If the data is erroneously written into the program, there is a danger of the program going out of control. Therefore, in the present embodiment, as shown in FIG. 1, a write control circuit 25 is provided to prevent erroneous writing into the write-inhibited area RO.

The write control circuit 25 receives the external addresses AEX0 to AEXn and the write signal φWE, generates a write inhibit signal, and sends it to the control input of the memory unit 1. ing. That is, as shown in FIG. 5, the write control circuit 25 includes an address buffer 25a and a write inhibit signal generation circuit 25b, and the external addresses AEX0 to AEXn receive the write inhibit signal generation circuit 25 via the address buffer 25a.
b, and the write signal φWE is input to the write inhibit signal generation circuit 25b.
As shown in FIG. 6, the write inhibit signal generation circuit 25b includes a comparator 25b and a write inhibit address storage unit 2.
5b. Write-protected address storage unit 25b
B indicates that the external addresses AEX0 to AEXn
Information indicating an address range that allows the comparison circuit 25b to detect whether the address is within O is stored. When the write signal φWE is active and indicates that writing is to be performed, the comparison circuit 25b stores the external addresses AEX0 to AEXn in the write-inhibited area RO based on the information in the write-inhibited address storage unit 25b. It is determined whether or not there is any data, and when it is detected that the data is within the write-inhibited area RO, the write-inhibit signal is activated and output. For example, the comparison circuit 25b is composed of one AND circuit as shown in FIG.
The AND circuit stores the external address AEXn of the most significant bit of the external addresses AEX0 to AEXn, the power supply voltage VCC (H level) indicating the write-inhibited address from the write-inhibited address storage unit 25b, and the write signal φWE. When input, the write signal φWE is active (H
Level), and the write inhibit signal becomes active (H level) when the external address AEXn is also at H level. In this case, the upper half address of all addresses in the memory unit 1 is set as the write-protected area RO.

The write inhibit signal output from the comparison circuit 25b in this way becomes the output of the write inhibit signal generation circuit 25b and the write control circuit 25 as it is, and as shown in FIG. The signal is sent to the generating circuit 1a. The write timing generation circuit 1a is a circuit that sends a timing signal for writing to the column decoder / sense amplifier 1c in response to a control signal input via the control signal input buffer 1b. When the write inhibit signal becomes active, the generation of the timing signal can be stopped and the write to the memory cell can be inhibited. The write inhibit signal is output to the outside of the nonvolatile semiconductor memory device so that an external device or the like can be notified that there is a write access to the write inhibit area RO.

However, it is necessary to write data in the write-protected area RO of the memory unit 1 at least once at first. Therefore, it is necessary to provide the write control circuit 25 with means for preventing the write inhibit signal from being activated even when the external addresses AEX0 to AEXn are in the write inhibit area RO. For example, write signal φ
WE is substantially the external write enable signal WE.
Although the bar is inverted, even when the write enable signal WE is active (L level) only in such a forced write, it can be separately made inactive (L level). By doing so, it is possible to suppress the write inhibit signal from becoming active. Such a write signal φWE is input from an external terminal when the nonvolatile semiconductor memory device is configured as a single memory device, and is input to a pad on the chip when configured as a memory module such as a one-chip microcomputer. Can be entered from

The specific operation of the control unit of the nonvolatile semiconductor memory device having the above configuration will be described with reference to the time chart of FIG.

As described above with reference to FIG. 1, when the power is turned on, the initialization pulse signal PON goes high, so that the internal addresses A0 to An generated by the address counter 5 are reset to the initial values, and a recall request is issued. The latch circuit 19 is set and an L level recall request signal RC is output via the output buffer 20. When the power is turned on, since the volatile storage contents of the DRAM mode are destroyed, such a recall request signal RC is output to an external device or another internal module.
Since the refresh signal RFSH bar is inactive at the beginning of the power ON, the internal refresh signal REF generated by the control signal generation circuit 10 is also inactive (L
Level), whereby the counters 11 and 13 and the timer stop latch circuit 17 are reset, and the timer circuit 23 does not generate the clock signals T1 and T2.

Here, assuming that refresh signal RFSH goes active (L level) at time t0 shown in FIG. 8, internal refresh signal REF goes active (H level) and internal address activation signal φ.
INA becomes active (H level). Since external access is not described in FIG. 8, external address activation signal φEXA remains inactive (L level).

As described above, the internal refresh signal REF
Becomes active (H level), the timer stop latch circuit 17 remains reset, so that the timer circuit 23 starts generating the long-period clock signal T1 and the short-period clock signal T2. Although the period of the clock signal T2 is not clear in the figure, in the case of the above example,
The period is 1/16 of the clock signal T1. Here, since the latch circuit 14 is still reset, the selection circuit 24 supplies the clock signal T1 having the longer cycle to the address counter 5. Accordingly, the internal address A0 of the least significant bit among the internal addresses A0 to An generated by the address counter 5 changes at the same cycle as the clock signal T1. And these internal addresses A0 to An
The internal addresses A0 to An which are sent to the driver / decoder circuit 4 via the internal address transition detection circuit 6 and the address selection circuit 3 and change in the clock signal T1.
Is detected by the internal address transition detection circuit 6 and the word line control circuit 7 and the plate line control circuit 8 are driven, so that the refresh operation is sequentially performed on each memory cell of the memory unit 1 in the cycle of the clock signal T1. Will be done.

The internal address An of the most significant bit of the internal addresses A0 to An changes in an extremely long cycle obtained by dividing the internal address A0 of the least significant bit by n times twice. Note that, here, for convenience of illustration of the time scale, the internal address A0 divided by 4 (n = 2) is shown as the internal address An, but the actual period of the internal address An is usually longer. Become something. The internal address An is equivalent to one cycle of the internal address A0 to An each time the pulse falls, thereby completing a series of refresh operations. Then, the first counter 11 counts the number of refresh operations by counting each time the internal address An falls.

When the first counter 11 finishes counting a predetermined number of times at time t1, the output of the first counter 11 changes to H level. Then, since the latch circuit 14 is set, the selecting circuit 24 supplies the clock signal T2 having a short cycle to the address counter 5 instead of the clock signal T1, and the internal address A0 of the least significant bit is provided.
Also starts to change at the same cycle as the clock signal T2.
Further, when the latch circuit 14 is set, the plate line control circuit 8 is also set, and the driving of the store operation is started. Therefore, the data is stored as volatile in each memory cell of the memory unit 1 and maintained by the refresh operation until then. The stored contents are re-stored as non-volatile. Moreover, in this case, since the store operation is performed at the cycle of the clock signal T2 shorter than the cycle of the clock signal T1, a series of store operations for all the memory cells are completed in a short time.
Then, the cycle of the change of the internal address An also becomes short, and a series of store operations is completed each time this pulse falls. The second counter 13 counts the number of times of the store operation by performing a count every time the internal address An falls.

When the second counter 13 finishes counting the predetermined number of times at time t2, the output of the second counter 13 changes to the H level. Then, since the latch circuit 14 is reset, the plate line control circuit 8 stops the store operation. Since the timer stop latch circuit 17 is also set, the timer circuit 23 stops generating the clock signals T1 and T2, and the internal addresses A0 to An are not generated. Accordingly, thereafter, the standby state is established until the refresh signal RFSH bar returns to the inactive state, and the standby operation can be performed with extremely low power consumption because the refresh operation is not performed. In this case, the recall request latch circuit 19 is set and the L-level recall request signal RC is output via the output buffer 20. It can be seen that it is necessary to access in the recall mode when reading is performed, and control becomes easy.

When the refresh signal RFSH returns to inactive, the refresh operation or the store operation is stopped. Then, the internal refresh signal RE
When F becomes inactive, the counters 11, 1
3 and the timer stop latch circuit 17 are reset,
The timer circuit 23 also stops generating the clock signals T1 and T2. Then, when the refresh signal RFSH becomes active again thereafter, the operation from the time t0 is repeated again, and the refresh operation is started.

As a result, according to the nonvolatile semiconductor memory device of this embodiment, when the refresh operation has been continued for a predetermined number of times or more, the contents stored as volatile in the memory cells of the memory section 1 are stored. As a result, the data can be automatically stored again in a non-volatile manner, so that a refresh operation of data or the like which is not accessed for a long time becomes unnecessary, and power consumption can be reduced. In the store operation, the internal addresses A0 to An are supplied by a clock signal having a shorter cycle than that in the refresh operation.
Is generated, it is possible to quickly switch the storage as nonvolatile. Further, when the store operation is automatically performed as described above, the recall request signal RC is output to the outside, so that the external device or the like needs to access in the recall mode when reading the stored contents next time. You can easily know that there is.

If the nonvolatile semiconductor memory device of this embodiment is used instead of the RAM and PROM built in the one-chip microcomputer and the RAM and PROM used in other control microcomputers, the RAM and PROM can be used.
Since a decoder circuit and a sense amplifier circuit required for each of the ROMs can be shared, a chip area and a circuit area on a substrate can be reduced. Moreover, by setting an address area originally used as a PROM in the write-inhibited address storage section 25b of the write control circuit 25 to provide a write-inhibited area RO in the memory section 1, programs and data can be protected from erroneous writing. can do. Furthermore, if the information in the write-inhibited address storage unit 25b is made programmable, the writable area RW (RAM
) And the write-protected area RO (corresponding to PROM) can be freely changed, so that a system with less waste in the address space can be configured.

Here, in the nonvolatile semiconductor memory device using a ferroelectric material, the number of times of rewriting the storage contents as nonvolatile is limited, but if the number of times of rewriting is 10 8, the first counter 11 Even if the predetermined number is set to a number corresponding to one second, operation for about 10 years can be guaranteed. If the number of times of rewriting is equal to or more than 10 times, even if the predetermined number of times of the first counter 11 is set to a number corresponding to 10 ms, the operation for about 10 years is guaranteed. It is also possible to perform control so that storage is switched to nonvolatile as soon as it becomes active (L level). That is, if the number of word lines is 1000 and the clock signal T1 is, for example, 16 microseconds, the time for selecting each word line is once every 16 milliseconds.
If it is more than 10 times, operation for about 10 years is guaranteed.
Therefore, as shown in FIG. 14 and FIG.
Is set to set the plate line control circuit 8, the output REF of the AND circuit 22 becomes active when the refresh signal RFSH goes active (L level).
Since 1 changes to the H level and the plate line control circuit 8 is also set, the store operation is performed in the same cycle as the volatile data refresh operation. When the second counter 13 finishes counting the predetermined number of times after time t2, the output of the second counter 13 changes to the H level. Then
Since the timer stop latch circuit 17 is set, the timer circuit 23 stops generating the clock signals T1 and T2, and enters a standby state with low power consumption. In another embodiment, the refresh operation and the store operation of the volatile data are performed in the same cycle between the time t0 and the time t1, so the store operation period by the clock signal T2 is omitted in FIG. (The predetermined time of the counter 13 is set to 0
Seconds).

Although the present embodiment has shown an example of controlling a nonvolatile semiconductor memory device using a ferroelectric substance, the present invention is not limited to this configuration. Also, DRA
The present invention can be similarly applied to a nonvolatile semiconductor memory device combining M and EEPROM.

[0063]

As is apparent from the above description, according to the nonvolatile semiconductor memory device of the present invention, when the refresh operation continues for a predetermined time or more, the storage contents are automatically switched to nonvolatile storage. Therefore, a refresh operation for data or the like that is not accessed for a long time is not required, and power consumption can be reduced. Also,
At this time, when the cycle of the clock signal is switched, the refresh operation is performed with low power consumption, and the switching to the nonvolatile storage can be quickly performed. Furthermore, if a recall request signal is output when the storage is automatically switched to the nonvolatile storage, control from an external device or the like can be facilitated. In addition, during store operation, N
Since the E-bar signal is not used, external control becomes easy.
You.

[Brief description of the drawings]

FIG. 1, showing one embodiment of the present invention, is a block diagram illustrating a configuration of a control unit of a nonvolatile semiconductor memory device.

FIG. 2, showing an embodiment of the present invention, is a block diagram illustrating a specific configuration of an address counter.

FIG. 3, showing an embodiment of the present invention, is a partial circuit block diagram illustrating a specific configuration of an address selection circuit.

FIG. 4 illustrates an embodiment of the present invention and is an address map of a memory unit.

FIG. 5, showing an embodiment of the present invention, is a block diagram illustrating a specific configuration of a write control circuit.

FIG. 6, showing an embodiment of the present invention, is a block diagram illustrating a specific configuration of a write inhibit signal generation circuit.

FIG. 7 is a block diagram showing one embodiment of the present invention and showing a specific configuration of a comparison circuit.

FIG. 8, showing an embodiment of the present invention, is a time chart illustrating an operation of the nonvolatile semiconductor memory device.

FIG. 9 is a diagram showing a hysteresis characteristic of a ferroelectric.

FIG. 10 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device.

FIG. 11 is a diagram illustrating an operation when data “0” is written in a memory cell using a ferroelectric substance in a store mode.

FIG. 12 is a diagram illustrating an operation when data “1” is written to a memory cell using a ferroelectric substance in a store mode.

FIG. 13 is a diagram illustrating an operation when data is read from a memory cell using a ferroelectric substance in a recall mode.

FIG. 14 illustrates another embodiment of the present invention, and is a block diagram illustrating a configuration of a control unit of a nonvolatile semiconductor memory device.

FIG. 15, showing another embodiment of the present invention, is a time chart illustrating an operation of the nonvolatile semiconductor memory device.

FIG. 16 illustrates another embodiment of the present invention, and is a block diagram illustrating a configuration of a control unit of a nonvolatile semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 1 memory section 5 address counter 6 internal address transition detection circuit 8 plate line control circuit 11 first counter 13 second counter 19 recall request latch circuit 23 timer circuit 24 selection circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/788 29/792

Claims (4)

(57) [Claims] 1. A nonvolatile memory cell comprising a volatile memory cell requiring a refresh operation to maintain stored contents and a nonvolatile memory cell capable of rewriting stored contents, or both volatile and nonvolatile storage cells In a nonvolatile semiconductor memory device having a memory cell having a function, an address generating means for automatically generating an address of each memory cell sequentially based on a clock signal; and a volatile memory based on the address generated by the address generating means. Self-refresh means for performing a refresh operation by sequentially rewriting the stored contents of the cells or the memory cells in which the stored contents are stored as volatile; and measuring the time during which the self-refresh means continuously performs the refresh operation. Refresh timing means, and refresh operation timed by the refresh timing means Self-store start means for determining whether the time has exceeded a predetermined time; and when the self-store start means determines that the predetermined time has passed, the refresh operation by the self-refresh means is stopped, and A store operation of sequentially transferring and storing each memory content of a volatile memory cell to a nonvolatile memory cell based on the generated address, or a nonvolatile memory cell sequentially storing each memory content of a memory cell stored as volatile A non-volatile semiconductor storage device comprising: a self-store means for performing a store operation for storing data as a memory. 2. A clock signal supply unit for inputting or generating and supplying two types of clock signals having different periods for automatically generating the address, and a clock signal when the self-refresh unit performs a refresh operation. A clock signal switching means for supplying a clock signal having a longer cycle from a supply means, and for supplying a clock signal having a shorter cycle from the clock signal supply means when the self-store means performs a store operation. 2. The nonvolatile semiconductor memory device according to 1. 3. A nonvolatile memory cell comprising a volatile memory cell requiring a refresh operation to maintain stored contents and a nonvolatile memory cell capable of rewriting stored contents, or both volatile and nonvolatile storage. In a nonvolatile semiconductor memory device having a memory cell having a function, an address generating means for automatically generating an address of each memory cell sequentially based on a clock signal; and a volatile memory based on the address generated by the address generating means. A self-store means for performing a refresh operation by sequentially rewriting the stored contents of the stored memory cells and simultaneously performing a store operation for storing volatile data in a non-volatile manner; And the self-store means continues the store operation.
Self-storage, which resets the clock if not performed
A timer means, a means for determining whether or not the time of the store operation timed by the self-store timekeeping means has exceeded a predetermined time; and a refresh operation and a store operation by the self-store means when it is determined that the time has exceeded the predetermined time. A non-volatile semiconductor storage device having means for stopping operation. 4. A recall request signal for requesting a recall operation for reading a storage content of a nonvolatile memory cell or a memory cell stored as nonvolatile when the self-store means performs a store operation. 4. The non-volatile semiconductor memory device according to claim 1, further comprising a recall request signal generating means for performing the operation.