JP3110605B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a built-in capacitive element using a ferroelectric film or a dielectric film having a high dielectric constant as a capacitive insulating film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, unnecessary radiation, which is electromagnetic wave noise generated from electronic equipment, has become a major problem with the increase in the density of consumer electronic equipment. 2. Description of the Related Art A technique of embedding a large-capacity capacitive element in a semiconductor integrated circuit device using a dielectric film having a high dielectric constant (hereinafter collectively referred to as a dielectric film) as a capacitive insulating film has been receiving attention.

Further, with the aim of putting a non-volatile RAM capable of low operating voltage, high-speed writing, and high-speed reading, which has never existed heretofore, to a semiconductor integrated circuit device using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film Technical development for forming on top is being actively carried out.

A conventional semiconductor device having a built-in capacitance element will be described below with reference to a sectional view of a main part of FIG.

[0005] As shown in FIG. 5, an isolation oxide film 2 is formed on a silicon substrate 1, and a diffusion layer 3, a gate insulating film 4 and a gate electrode 5 are formed in a region surrounded by the isolation oxide film 2.
Is formed. A first insulating film 6 is formed so as to cover these transistors. On the first insulating film 6, a lower electrode 7, a capacitive insulating film 8 made of a dielectric film, and a capacitive element 10 made of an upper electrode 9 are formed. Are formed. A second layer, such as a silicon oxide film (hereinafter referred to as a PSG film) doped with phosphorus, covering these capacitive elements 10.
Of the insulating film 15 is formed. In the first insulating film 6 and the second insulating film 15, a contact hole 12a reaching each of the diffusion layers 3 of the transistor and a capacitor 10
A contact hole 12b reaching each of lower electrode 7 and upper electrode 9 is formed. Through these contact holes 12a, 12b, the electrode wirings 13a, 13
b is formed. Further, a protective film 14 is formed on the silicon substrate 1 so as to cover these elements.

Next, a method of manufacturing a conventional semiconductor device having a built-in capacitive element will be described with reference to the flowchart of FIG.

First, in the step of FIG. 6A, an isolation oxide film 2, a diffusion layer 3, a gate insulating film 4, and a gate electrode 5 are formed on a silicon substrate 1, and further, FIG. )
In this step, the first insulating film 6 is formed. Next, in the step of FIG. 6C, the lower electrode 7 and the capacitor insulating film 8 are formed on the first insulating film 6.
Then, a capacitive element 10 including the upper electrode 9 is formed. Generally, the heat treatment of the capacitive insulating film 8 is performed immediately after the capacitive insulating film 8 is formed or after the pattern of the capacitive element is formed.
The capacitance insulating film 8 is formed of a dielectric film, and the lower electrode 7 and the upper electrode 9 are formed of a platinum film,
It is composed of a titanium film. Next, in the step of FIG.
A second insulating film 15 such as PSG is formed on the entire surface by the D method or the like. Next, in the step of FIG. 6E, a contact hole 12a communicating with each of the diffusion layers 3 of the transistor,
A contact hole 12b reaching each of the lower electrode 7 and the upper electrode 9 of the capacitive element 10 is formed. Next, FIG.
In the step (f), an electrode wiring 13a connected to the diffusion layer 3 via the contact holes 12a and 12b and an electrode wiring 13b connected to the capacitor 10 are formed. Next, in the step of FIG. 6G, the protective film 14 is formed. Protective film 14
For example, a silicon nitride film or a silicon nitride oxide film with high moisture resistance formed by a plasma CVD method to prevent water from entering the silicon substrate 1, the capacitor element 10, and the electrode wirings 13a and 13b is used.

[0008]

However, in the above-mentioned conventional structure, the PSG film is used as the second insulating film 15 in the CV mode.
The PSG film absorbs moisture generated when forming by the method D,
This moisture diffuses into the dielectric film forming the capacitive insulating film 8 and lowers the electric resistance, causing an increase in the leakage current of the capacitive element 10 and a decrease in the withstand voltage, thereby causing a problem of causing dielectric breakdown. Was.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and prevents an increase in leakage current and a decrease in dielectric strength of a capacitive element using a dielectric film as a capacitive insulating film, thereby preventing a failure due to dielectric breakdown from occurring. It is an object to provide an apparatus and a method for manufacturing the same.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a lower electrode on a first insulating film of a support substrate on which a semiconductor integrated circuit is formed; A capacitive insulating film composed of a body film or a dielectric film having a high dielectric constant, a capacitive element composed of an upper electrode, a second insulating film covering the capacitive element, and a contact provided on the second insulating film An electrode wiring electrically connected to the semiconductor integrated circuit portion and the capacitor via a hole; and a protective film covering the electrode wiring, wherein the second insulating film has a water content of the second insulating film. It does not exceed 0.5 g in terms of 1 cm ^{3 of the} insulating film. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the second insulating film is a silicon oxide film to which phosphorus is added. According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
Forming a lower electrode, a capacitor insulating film made of a ferroelectric film or a dielectric film having a high dielectric constant, and an upper electrode in a predetermined region on the first insulating film. Forming a capacitive element; and forming a second
Forming a second insulating film, heat-treating the second insulating film such that the moisture content of the second insulating film does not exceed 0.5 g per 1 cm ³ , Forming a contact hole reaching the semiconductor integrated circuit portion or the upper electrode or the lower electrode of the capacitive element through the insulating film and the second insulating film; and a semiconductor integrated circuit portion through the contact hole. Alternatively, the method includes a step of forming a wiring electrically connected to the capacitor element and a step of forming a third insulating film covering the electrode wiring. According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the third aspect, wherein the heat treatment temperature of the second insulating film is 350 ° C. or more. .

[0011]

With this structure, the amount of water diffused into the capacitor insulating film made of a dielectric film is suppressed to a certain value or less, so that the dielectric strength of the capacitor insulating film is prevented from lowering, and the reliability and life are improved. .

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a main part of a semiconductor device having a built-in capacitive element according to an embodiment of the present invention. FIG.
The same reference numerals are given to the same portions as those in the cross-sectional view of the main part of the conventional semiconductor device having a built-in capacitive element shown in FIG.

The difference between the semiconductor device of the present embodiment and the conventional semiconductor device shown in FIG. 5 is that the moisture content of the second insulating film 16 such as a PSG film formed covering the capacitive element 10 shown in FIG. It is in. In a conventional semiconductor device, the second semiconductor device shown in FIG.
The moisture content of the insulating film 15 is not controlled at all,
Although the moisture content was 0.9 g or more per 1 cm ³ of the second insulating film, in the semiconductor device of this embodiment, 0.5 g was converted into 1 cm ³ of the second insulating film. It is controlled within the range not exceeding.

Next, a method of manufacturing a semiconductor device having a built-in capacitive element according to one embodiment of the present invention will be described with reference to FIGS. I do.

FIG. 2 is a flow chart of a manufacturing process of a semiconductor device having a built-in capacitive element according to one embodiment of the present invention. The difference from the flowchart of the conventional semiconductor device shown in FIG. 6 lies in the steps after FIG. That is, in the steps of FIGS. 2A to 2C, a transistor including the diffusion layer 3, the gate insulating film 4, and the gate electrode 5 is formed on the silicon substrate 1, and the first insulating film 6 covering the transistor is formed. A capacitive element 10 composed of a lower electrode 7, a capacitive insulating film 8, and an upper electrode 9 is formed thereon. Next, in the step of FIG.
A second insulating film 16 such as a PSG film is formed on the entire surface by a VD method or the like. Next, in the step of FIG. 2E, the moisture contained in the second insulating film 16 is removed by heat-treating the second insulating film 16 in a nitrogen atmosphere.

Next, as shown in FIG. 2F, a contact hole 12a leading to the diffusion layer 3 of the transistor and a contact hole 12b reaching the lower electrode 7 and the upper electrode 9 of the capacitive element 10, respectively, are formed. Next, in the step of FIG. 2G, an electrode wiring 13a connected to the diffusion layer 3 via the contact holes 12a and 12b and an electrode wiring 13b connected to the capacitor 10 are formed. Next, FIG.
In this step, the protective film 14 is formed. As the protective film 14, the silicon substrate 1, the capacitor 10 and the electrode wiring 13
a, 13b to prevent water from entering
A silicon nitride film or a silicon nitride oxide film with high moisture resistance formed by a VD method is suitable.

In the structure and the manufacturing method of this embodiment, an example in which a PSG film is formed as the second insulating film 16 by the CVD method and then moisture is removed from the PSG film by a heat treatment step has been described. The present invention is not limited to this. For example, a silicon oxide film may be formed under a high-temperature and reduced-pressure state, and the heat treatment may be omitted.

Further, in this embodiment, an example in which the heat treatment step of FIG. 2E is performed in a nitrogen gas has been described, but the heat treatment step may be performed in an inert gas such as helium or argon, or in a vacuum.

Next, the result of measuring the amount of water adsorbed on the PSG film formed by the CVD method will be described with reference to FIG.

In FIG. 3, the horizontal axis represents temperature, and the vertical axis represents the amount of water released at that temperature, and these relationships correspond to the strength of water adsorption. As shown in FIG.
The peak temperature at which the moisture adsorbed on the PSG film desorbs is the first temperature.
Peak at 300 ° C. to 350 ° C. and a second peak at 450 ° C.
C. to 530.degree. Of these, the water corresponding to the second peak is adsorbed on PSG with a sufficiently strong adsorption force,
It is considered that the reliability in normal use is hardly affected. On the other hand, the first peak has a bottom extending to the low temperature side, and there is a high risk that the adsorbed water is released under conditions relatively close to the use temperature.

The inventors have found that the heat treatment temperature is desirably 350 ° C. or higher in order to release the adsorbed water corresponding to the first peak in FIG. 3 immediately after the film is formed by the CVD method. Further, as the insulating film 16, 6
It has been found that heat treatment of a silicon oxide film containing not more than phosphorus by weight is preferable also in relieving the stress applied to the capacitor 10.

The capacitance element 10 manufactured according to this embodiment
FIG. 4 shows the result of examining the reliability of. here,
A barium / strontium titanate thin film was used for the capacitance insulating film 8. The horizontal axis represents the reciprocal of the electric field applied to the capacitor 10, and the vertical axis represents the time until the leakage current reaches a constant value. The straight line (a) is the result of observing the leakage current while applying a voltage to the capacitor 10 manufactured by the conventional method. The water content of the PSG film used as the second insulating film 16 is 0.93 g / cm ³ . The straight line (b) is the result of the capacitive element 10 manufactured according to the present embodiment,
The moisture content of the PSG film which is the insulating film 16 is 0.45.
g / cm ³ . From these comparisons, the second insulating film 1
6 demonstrated that the capacitance element 10 according to the present example having a small water content was much superior.

In this embodiment, as shown in FIG. 2, an example in which the contact holes 12a and 12b are formed after the second insulating film 16 is formed and the heat treatment is performed has been described. Then, heat treatment may be performed after forming the second insulating film 16 and forming the contact hole 12b. In this case, the contact hole 12b serves as a ventilation hole, and moisture already adsorbed to the capacitance element 10 is easily removed.

In this embodiment, an example in which the heat treatment step shown in FIG. 2E is performed once has been described. However, it is also effective to perform the heat treatment step a plurality of times. For example, the second
The first heat treatment is performed after the formation of the insulating film 16 and the contact holes 12a and 12b are formed.
A second heat treatment may be performed. In this case, the heat treatment conditions may be changed in the first and second heat treatment steps.

[0026]

The present invention covers a capacitor having a capacitor insulating film made of a ferroelectric film or a dielectric film having a high dielectric constant formed on an insulating film of a support substrate on which a semiconductor integrated circuit is formed. A structure in which an insulating film whose moisture content does not exceed 0.5 g in terms of 1 cm ³ is prevented, thereby preventing an increase in leakage current and a decrease in withstand voltage of a capacitive element using a dielectric film as a capacitive insulating film. In addition, it is possible to realize an excellent semiconductor device in which a failure due to dielectric breakdown does not easily occur and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device having a built-in capacitive element according to an embodiment of the present invention;

FIG. 2 is a flowchart of a manufacturing process of a semiconductor device having a built-in capacitive element according to one embodiment of the present invention;

FIG. 3 is a graph showing a temperature-dependent desorption amount of water from a silicon oxide film containing phosphorus.

FIG. 4 is a diagram showing a reliability test result of a silicon oxide film containing phosphorus.

FIG. 5 is a sectional view of a main part of a conventional semiconductor device having a built-in capacitive element;

FIG. 6 is a flowchart of a manufacturing process of a conventional semiconductor device having a built-in capacitive element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Isolation oxide film 3 Diffusion layer 4 Gate insulating film 5 Gate electrode 6 First insulating film 7 Lower electrode 8 Capacitive insulating film 9 Upper electrode 10 Capacitance element 12a, 12b Contact hole 13a, 13b Electrode wiring 14 Protective film 16 Second insulating film

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Nasu 1-1, Kochi-cho, Takatsuki-shi, Osaka Prefecture Inside Matsushita Electronics Corporation (72) Inventor Akihiro Matsuda 1-1-1, Kochi-cho, Takatsuki-shi, Osaka Matsushita Electronics (56) References JP-A-4-85878 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 27/10 451

Claims (4)

(57) [Claims] A first insulating film on a support substrate on which a semiconductor integrated circuit is formed; a lower electrode; a capacitive insulating film comprising a ferroelectric film or a dielectric film having a high dielectric constant; and an upper electrode. A capacitor, a second insulating film covering the capacitor, a semiconductor integrated circuit portion via a contact hole provided in the second insulating film, and an electrode wiring electrically connected to the capacitor. And a protective film covering the electrode wiring, wherein the moisture content of the second insulating film does not exceed 0.5 g per 1 cm ^{3 of} the second insulating film. 2. The method according to claim 1, wherein the second insulating film is made of a silicon doped with phosphorus.
2. The semiconductor according to claim 1, wherein the semiconductor is a silicon oxide film.
Body device. 3. A step of forming a first insulating film on a semiconductor substrate on which a semiconductor integrated circuit is formed, and a step of forming a lower electrode, a ferroelectric film or a high dielectric material in a predetermined region on the first insulating film. Forming a capacitive insulating film composed of a dielectric film having a volume and a capacitive element composed of an upper electrode; forming a second insulating film covering the capacitive element ; Water content is converted per 1cm ³
And heat-treating the second insulating film so as not to exceed 0.5 g.
A step of management, and forming the first insulating film and the semiconductor integrated circuit section through a second insulating film or the upper electrode or a contact hole reaching the lower electrode of the capacitor, the contact A method of manufacturing a semiconductor device, comprising: a step of forming a wiring electrically connected to a semiconductor integrated circuit portion or the capacitor via a hole; and a step of forming a third insulating film covering the electrode wiring. . 4. The method according to claim 3 , wherein the heat treatment temperature of the second insulating film is 350 ° C. or higher.