JP3072293B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a built-in capacitive element using a dielectric film having a high dielectric constant or a ferroelectric film as a capacitive insulating film.

[0002]

2. Description of the Related Art In recent years, with the advancement of consumer electronic equipment, unnecessary radiation, which is electromagnetic wave noise generated from electronic equipment, has become a major problem. As a measure to reduce this unnecessary radiation, a dielectric film having a high dielectric constant has been proposed. 2. Description of the Related Art A technique for incorporating a large-capacitance element in a semiconductor integrated circuit using a high-dielectric film (hereinafter, referred to as a high-dielectric film) as a capacitance insulating film has attracted attention. In addition, with the aim of commercializing a non-volatile RAM capable of unprecedented low operating voltage, high-speed writing and high-speed reading, a capacitive element using a ferroelectric film having spontaneous polarization characteristics as a capacitive insulating film is formed on a semiconductor integrated circuit. Technology development is being actively carried out.

A conventional semiconductor device will be described together with a method of manufacturing the same with reference to the drawings.

FIGS. 6A to 6C are cross-sectional views showing a conventional semiconductor device manufacturing process. First, as shown in FIG. 6A, an isolation oxide film 2, a high concentration region 3, a gate insulating film 4, a gate electrode 5, and an interlayer insulating film 6 are formed on a silicon substrate 1. On this interlayer insulating film 6, a capacitive element 10 including a lower electrode 7, a capacitive insulating film 8 and an upper electrode 9 is formed. Generally, the heat treatment of the capacitor insulating film 8 is performed immediately after the capacitor insulating film 8 is formed or after the pattern is formed. The capacitance insulating film 8 is made of a ferroelectric film or a high dielectric film, and the lower electrode 7 and the upper electrode 9 are made of a platinum film and a titanium film in order from the side in contact with the capacitance insulating film 8. Next, FIG.
As shown in (b), after forming a first protective film 11 such as a silicon oxide film on the entire surface, the high concentration region 3 of the semiconductor integrated circuit is formed.
And a contact hole 12b communicating with the lower electrode 7 and the upper electrode 9 of the capacitive element 10, respectively. Next, as shown in FIG. 6C, after forming the metal wirings 13a and 13b, a second protective film 14 is formed. As the second protective film 14, a highly moisture-resistant silicon nitride film or a silicon nitride oxide film formed by a plasma CVD method in order to prevent moisture from entering the silicon substrate 1, the capacitor 10, and the metal wirings 13a and 13b. A membrane is used.

[0005]

However, in the above-mentioned conventional configuration, the capacitance which is an oxide due to active hydrogen atoms, radicals or ions generated when a silicon nitride film or a silicon nitride oxide film is formed by a plasma CVD method. Since the ferroelectric film or the high-dielectric film constituting the insulating film is reduced and their electric resistance is rapidly reduced, there is a problem that the leakage current of the capacitor increases and the withstand voltage decreases. Was.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and it is possible to prevent an increase in leakage current of a capacitive element using a ferroelectric film and a high dielectric film as a capacitive insulating film, and to prevent a decrease in withstand voltage. It is an object to provide an apparatus and a method for manufacturing the same.

[0007]

In order to achieve this object, a semiconductor device according to a first aspect of the present invention is a semiconductor device , comprising: a lower electrode, a ferroelectric film on an insulating film of a support substrate on which a semiconductor integrated circuit is formed;
Element consisting of body film or high dielectric film and upper electrode
Through the lower electrode and the upper electrode on the capacitive element.
A first protective film in which a slip contact hole is formed;
Metal wiring formed in the contact hole of
Formed on the protective film and in a region excluding the capacitive element
A second protective film, on the capacitive element and the second protective film;
And a third protective film formed on the film .
The semiconductor device according to claim 2 of the present invention, according to claim 1
2. The semiconductor device according to claim 1, wherein the first protective film is
A second protective film formed in a region excluding the capacitive element,
Characterized in that it is arranged outside the capacitive element
Things. A semiconductor device according to claim 2 of the present invention.
2. The semiconductor device according to claim 1, wherein
The protective film is a silicon nitride film or a silicon nitride oxide film.
It is a sign.

In a semiconductor device according to a third aspect of the present invention, a ferroelectric film or a capacitor having a high dielectric constant is provided on an insulating film of a support substrate on which a semiconductor integrated circuit is formed. A metal wiring having a titanium nitride film is provided so as to cover the capacitor via a first protective film provided thereon. Further, the semiconductor device according to claim 5 of the present invention is the semiconductor device according to claim 3 or 4.
The semiconductor device described above has a configuration in which a second protective film, which is a silicon nitride film or a silicon nitride oxide film, is provided on the metal wiring.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a lower electrode and a ferroelectric film or a high dielectric constant on an insulating film of a support substrate in which a semiconductor integrated circuit is formed. Forming a capacitive element comprising a capacitive insulating film such as a dielectric film and an upper electrode, forming a first protective film on the capacitive element, and forming a contact formed on the first protective film Forming a metal wiring having a titanium nitride film connected to the upper electrode and the lower electrode through the hole so as to cover the capacitance element; and forming a second protective film on the metal wiring. . According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the second protective film is formed by a plasma CVD method.

With this configuration, it is possible to reduce the leak current and improve the dielectric strength without impairing the water resistance and moisture resistance of the capacitive element. In addition, since a silicon oxide film to which phosphorus is added is formed on the capacitor, stress is not applied to the capacitor and high reliability can be realized.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, FIG.
The same parts as those in the conventional example shown in FIGS. Reference numeral 15 denotes a silicon oxide film to which phosphorus is added, and 16 denotes a silicon oxide film to which phosphorus is not added. The first embodiment shown in FIG. 1 is different from the conventional semiconductor device in that a silicon oxide film 11 is formed on a capacitor 10 formed on an interlayer insulating film 6 in the first embodiment. A silicon oxide film 15 to which phosphorus is added and a silicon oxide film 16 to which phosphorus is not added are formed by laminating the metal wirings 13a and 13b on the metal oxide films 13a and 13b. The silicon oxide film 15 to which phosphorus is added relieves stress applied to the capacitor 10 and prevents the intrusion of impurities, and the silicon oxide film 16 to which phosphorus is not added ensures moisture resistance and water resistance.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIG.

FIG. 2 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention. In FIG. 2, FIG.
The same parts as those in the conventional example shown in (a) to (c) are denoted by the same reference numerals, and description thereof will be omitted. The difference between the second embodiment and the first embodiment is that in the second embodiment,
A second protective film 14 such as a silicon nitride film or a silicon nitride oxide film is formed in a region other than the capacitor 10. With such a configuration, even if the capacitive insulating film 8 is heat-treated after the capacitive element 10 is formed, the semiconductor is formed by hydrogen or a hydrogen compound generated from the ferroelectric film or the high dielectric film forming the capacitive insulating film 8. Deterioration of a part of the integrated circuit can be prevented. Finally, as in the first embodiment, the silicon oxide film 15 doped with phosphorus is
And a silicon oxide film 16 to which phosphorus is not added. Therefore, the silicon oxide film 15 to which phosphorus is added is used to alleviate the stress applied to the capacitor 10 and prevent intrusion of impurities, and do not add phosphorus. The silicon oxide film 16 can ensure moisture resistance and water resistance.

Next, a third embodiment of the present invention will be described.
This will be described with reference to FIG.

FIG. 3 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention. In FIG. 3, FIG.
The same parts as those in the conventional example shown in (a) to (c) are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 17 denotes a lower electrode in which a platinum film is laminated on a titanium film, and reference numeral 18 denotes a titanium nitride film.
The third embodiment is different from the conventional one in that the metal wiring 13a
Film 17 and a titanium nitride film 18 at the connection between the semiconductor device and the semiconductor integrated circuit and between the metal wiring 13b and the capacitor 10.
And the upper portion of the capacitive element 10 is covered with the titanium film 17, the titanium nitride film 18 and the metal wiring 13b. The titanium nitride film 18 is a dense film that does not allow passage of hydrogen. With such a structure, even if a silicon nitride film or a silicon nitride oxide film is formed as the second protective film 14 by a plasma CVD method, Can be prevented from being reduced by the hydrogen atoms, radicals or ions.

In FIG. 3, the upper portion of the capacitance element 10 is covered with a titanium film 17, a titanium nitride film 18, and a metal wiring 13
Although the example covered with the three-layer film b has been described, the film may be covered with the titanium nitride film 18 alone or with a laminated film of the titanium nitride film 18 and the titanium film 17.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a process sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 4 shows FIG.
1 shows a method of manufacturing a semiconductor device according to the first embodiment, in which the same portions are denoted by the same reference numerals and description thereof is omitted.

First, as shown in FIG. 4A, an isolation oxide film 2, a high concentration region 3, a gate insulating film 4, a gate electrode 5, and an interlayer insulating film 6 are formed on a silicon substrate 1. On this interlayer insulating film 6, a lower electrode 7, a capacitor insulating film 8 and an upper electrode 9
Is formed. The capacitance insulating film 8 is made of a ferroelectric film or a high dielectric film, and the lower electrode 7 and the upper electrode 9 are made of only a platinum film or a film in which a platinum film and a titanium film are laminated in this order from the side of the capacitance insulating film 8. . Next, after a first protective film 11 such as a silicon oxide film is formed on the entire surface, a contact hole 12a leading to the high concentration region 3 of the semiconductor integrated circuit, a contact leading to the lower electrode 7 and the upper electrode 9 of the capacitor 10 respectively. A hole 12b is formed. Next, as shown in FIG. 4B, metal wirings 13a and 13b are formed. Next, as shown in FIG. 4C, a stacked film of a silicon oxide film 15 to which phosphorus is added and a silicon oxide film 16 to which phosphorus is not added is formed on the entire surface. Finally, an opening is formed in the laminated film on an electrode pad (not shown) for wire bonding of the integrated circuit.

Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a process sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention, and shows only points different from the embodiment shown in FIG. That is, in the step of FIG. 4C, a second protective film made of a silicon nitride film or a silicon nitride oxide film is used instead of the stacked film of the silicon oxide film 15 to which phosphorus is added and the silicon oxide film 16 to which phosphorus is not added. 14 is formed. Next, as shown in FIG. 5A, the opening 17 is formed by removing the second protective film 14 on the capacitor 10. At this point, heat treatment of the capacitor element 10 reduces the leakage current and improves the withstand voltage. Next, as shown in FIG. 5B, a laminated film of a silicon oxide film 15 to which phosphorus is added and a silicon oxide film 16 to which phosphorus is not added is formed on the entire surface. Finally, an opening is formed in the laminated film on an electrode pad (not shown) for wire bonding of the integrated circuit.

[0022]

As described above, according to the present invention, a silicon oxide film doped with phosphorus and a silicon oxide film not doped with phosphorus are laminated to cover a capacitor, or a titanium film and a titanium nitride film are used to form a capacitor. An excellent semiconductor device capable of preventing an increase in leakage current of a capacitive element using a ferroelectric film and a high dielectric film as a capacitive insulating film and preventing a decrease in withstand voltage, and a method of manufacturing the same by adopting a structure that covers the upper part Can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is an essential part cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

FIGS. 4A to 4C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIGS. 5A and 5B are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention;

FIGS. 6A to 6C are process cross-sectional views illustrating a structure and a manufacturing method of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate (support substrate) 2 interlayer insulating film (insulating film) 7 lower electrode 8 capacitive insulating film 9 upper electrode 10 capacitive element 11 first protective film 13 a, 13 b metal wiring 15 silicon oxide film with phosphorus added 16 phosphorus Silicon oxide film not added

Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/06 H01L 27/10 651 27/10 451 27/108 29/788 29/792 (72) Inventor Yasuhiro Uemoto Sachiyuki Takatsuki, Osaka Prefecture No. 1-1, Matsushita Electronic Industry Co., Ltd. (72) Inventor Eiji Fujii 1-1, Yukicho, Takatsuki-shi, Osaka Prefecture Inside of Matsushita Electronic Industry Co., Ltd. (72) Tatsuo Otsuki 1, Yukicho, Takatsuki-shi, Osaka Prefecture No. 1 Matsushita Electronics Corporation (56) References JP-A-5-21710 (JP, A) JP-A-61-219140 (JP, A) JP-A-63-45849 (JP, A) Hei 1-265524 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/04 H01L 21/822 H01L 21/8234 H01L 21/8242 H01L 21/8247 H01L 27/06 H01L 27/10 451 H01L 27/108 H01L 29/788 H01L 29/792

Claims (9)

(57) [Claims] A lower electrode, a ferroelectric film or a high-dielectric film on the insulating film of the support substrate on which the semiconductor integrated circuit is formed ;
And a capacitor comprising an upper electrode and the lower
A contact hole leading to the electrode and the upper electrode is formed
Formed first protective film and the contact hole
Metal wiring, on the first protective film and the capacitor element.
A second protective film formed in a region excluding the capacitor;
Third protection formed on the element and on the second protection film
Semiconductor device having a film . 2. The method according to claim 1, wherein the second protective film is a silicon nitride film or a nitride film.
2. The half of claim 1, which is a silicon nitride oxide film.
Conductor device. 3. A ferroelectric film or a capacitor having a high dielectric constant is provided on an insulating film of a support substrate on which a semiconductor integrated circuit is formed, and via a first protective film provided on the capacitor. A metal wiring having a titanium nitride film provided so as to cover the capacitor. 4. The semiconductor device according to claim 3, wherein said metal wiring comprises a laminated film having a titanium film and a titanium nitride film. 5. A silicon nitride film or a nitride film on the metal wiring.
4. The semiconductor device according to claim 3, wherein a second protective film, which is a silicon oxide film, is provided. 6. A capacitor comprising a lower electrode and a capacitor insulating film such as a ferroelectric film or a dielectric film having a high dielectric constant and an upper electrode on an insulating film of a support substrate in which a semiconductor integrated circuit is formed. Forming an element, forming a first protective film on the capacitive element, and forming a titanium nitride film connected to an upper electrode and a lower electrode through contact holes formed in the first protective film. A method for manufacturing a semiconductor device, comprising: forming a metal wiring having a thickness so as to cover the capacitor; and forming a second protective film on the metal wiring. 7. The method according to claim 6, wherein the second protective film is formed by a plasma CVD method. 8. The method according to claim 6, wherein the second protective film is a silicon nitride film or a silicon nitride oxide film. 9. The method according to claim 8, wherein the second protective film is a silicon oxide film doped with at least phosphorus.