JP3114687B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a field-effect transistor (F) having high output and low thermal resistance.
ET).

[0002]

2. Description of the Related Art In a field effect transistor (FET), there is a type in which a gate and a source / drain are composed of a large number of fingers, and a demand for higher output is increasing year by year. However, if the lateral size of the chip is excessively increased, the mechanical strength of the chip decreases, so there is a limit on the lateral size of the chip. Has become difficult. In addition, since the heat generated due to the increase in the output becomes large and the thermal stability decreases, it is necessary to widen the gate pitch and reduce the thermal resistance. However, even when the gate pitch is increased, the chip lateral size is limited, which makes it difficult to reduce the thermal resistance. Therefore, in order to increase the gate width or the gate pitch in a limited chip lateral size, it is necessary to increase the gate finger length.

[0003]

However, when the length of the gate finger is extended, the source finger is also extended at the same time. As a result, the RF characteristic is degraded due to an increase in the source inductance (Ls) (eg, a decrease in gain). The problem arises. For this reason, it has been difficult to extend the finger length without deteriorating the RF performance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and realizes an FET having a high output and a low thermal resistance by reducing a source inductance to extend a finger length while maintaining RF characteristics. It is an object of the present invention to provide a semiconductor device capable of performing the following.

[0005]

To achieve the above object, a semiconductor device according to the present invention comprises a source finger extending from a first source pad and a drain finger extending from a drain pad sandwiching each gate finger. A second source pad is provided in a non-operating region of the field-effect transistor at the tip of each of the source fingers , and via holes are provided in the first source pad and the second source pad, respectively. The second
Via holes provided in the source pad of
The source electrode is grounded through these via holes by being buried by the gold plating layer . Further, the present invention can also be applied to a so-called fishbone gate structure in which each of the gate fingers is divided into a plurality and the divided gate fingers are electrically connected by a plurality of gate bus bars.

In the semiconductor device of the present invention, since the source inductance is reduced by the via hole provided at the tip of the source finger, the source inductance does not increase even if the finger length is increased. Therefore, since the finger length can be increased, the lateral width of the chip can be increased, so that the number of fingers can be increased or the gate pitch can be increased, thereby realizing an FET with high output and low thermal resistance. .

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view illustrating a main part of the semiconductor device according to the first embodiment. The element shown in FIG.
Common-source high-output FE with a finger length of 600 μm, gate pitch of 30 μm, and gate-source distance of 10 μm
T1. A plurality of gate fingers 3 extend from the gate bus bar 2 in parallel with each other, and a gate pad 4 is connected to the gate bus bar 2. Further, a source finger 6 extending from the first source pad 5 and a drain finger 8 extending from the drain pad 7 are arranged with the respective gate fingers 3 interposed therebetween.

When the source is grounded, a via hole is formed. In this embodiment, the first and second source pads 5 and 9 for forming the via hole are located beside the gate pad 4 and the source finger 6 respectively. Located at the tip of. A wide source region is provided beside the gate pad 4, and a via hole 10 having a diameter of 70 μmφ is formed in the first source pad 5 on the source region. At the tip of the source finger 6, a 36 μm square second source pad 9 is provided in the non-operating region of the FET, and the second source pad 9 has a diameter of 20 μm.
A via hole 11 of φ is formed.

A process for forming a via hole having the above structure will be described below. First, after the formation of the operation region of the FET is completed, the semiconductor substrate is thinned to 30 μm. A photoresist for forming a via hole is applied to the back surface of the substrate, and source pads 5 on the surface of the substrate are aligned by double-sided alignment.
9 and the photoresist for via hole formation on the back surface of the substrate are aligned. At this time, the accuracy of both-side registration is 3 μm.
It is. The second source pad 9 at the tip of the source finger 6 is 36 μm square and has a via hole 11 of 20 μmφ.
On the other hand, since a margin of 8 μm is provided on one side, alignment can be performed without problems such as misalignment. After patterning the via hole forming photoresist, the semiconductor substrate is opened from the back surface by dry etching. Thereafter, a via hole is formed by forming a gold plating layer with a thickness of 20 μm.

Source finger 6 after via hole formation
FIG. 2 shows a sectional view of the tip. FIG. 2 is a sectional view taken along line AA of FIG. Via hole 11 at the tip of source finger 6
Has a diameter of 20 μmφ, it can be almost completely buried by the gold plating layer 12 having a thickness of 20 μm. The above-described via hole forming process is the same as the process of forming the back surface of a normal FET having via holes.
A via hole can be formed without any change or addition in the process other than the position where the via hole is formed. The drain finger 8 has an air bridge structure as shown in FIG. Reference numeral 13 denotes an insulating film.

FIG. 3 shows a conventional grounded-source high-output FET 15 having a finger length of 600 μm, a gate pitch of 30 μm, and a gate-source distance of 10 μm without a via hole at the tip of the source finger 6. The conventional FET 15 and the FET of the first embodiment are described.
FIG. 4 shows the result of measuring the RF characteristics of Sample No. 1. The source-drain voltage Vds is 10 V, and the frequency is 2 GHz. FIG. 4 shows that the output is almost the same, but the linear gain is improved by about 2 dB in the FET of the present invention.
As the linear gain increases, so does the efficiency.

FIG. 5 shows the finger length dependence of the linear gain in the FET of the present embodiment having a via hole at the tip of the source finger 6 and the conventional FET. In the case of the conventional FET in which the via hole is not provided at the tip of the source finger 6, the gain is greatly reduced as the finger length is increased. It is gradual, and is only about 1 dB lower than the conventional 300 μm FET.

FIG. 6 shows the dependence of the linear gain on the gate pitch in the FET of the present embodiment in which a via hole is provided at the tip of the source finger 6 and in the conventional FET. FIG. 6 shows data of FETs having finger lengths of 600 μm and 1000 μm. When the gate pitch is increased, the source pad at the tip of the source finger is also expanded in the horizontal direction, and the via hole is also expanded in the horizontal direction. In the case of the conventional FET, the gain hardly changes or slightly decreases even if the gate pitch is increased. However, in the FET of the present embodiment, the gain is improved when the gate pitch is increased, and when the gate pitch is 60 μm. It can be seen that the gain is improved by about 1 dB as compared with the 30 μm FET.

FIG. 7 shows MSG calculated from small signal S-parameter measured values of the FET of the present embodiment and the conventional FET.
5 shows the frequency characteristics of / MAG. The finger length was 600 μm and the gate pitch was 30 μm. For S-parameter measurement, an FET having a gate width of 4 mm was used. FIG. 7 also shows the result of fitting by simulation from the equivalent circuit extraction parameters. The FET of the present embodiment has a 2 G
The MAG at Hz is improved by about 2 dB, which is consistent with the improvement of the gain shown in FIG. Also, as a result of the simulation, of the equivalent circuit parameters extracted from the frequency characteristics of the conventional example, the source inductance was changed from 12 nH to 4 nH.
It has been found that by reducing to H, the frequency characteristics of the FET of the present embodiment can be fitted.

From this, it can be understood that the gain improvement effect of the FET 1 of the present embodiment is due to the source inductance being reduced by the via hole 11 at the tip of the source finger 6. In the dependence of the linear gain on the finger length shown in FIG. 5, in the conventional FET 15, even if the finger length is increased, the grounded source portion is located at 70 degrees beside the gate pad.
Since only the via hole 10 having a diameter of μmφ is used, as the finger length is increased, the source inductance of each finger increases, so that the linear gain decreases. On the other hand, in the case of the FET 1 of the present embodiment, since the via hole 11 is provided at the tip of each finger,
Even if the finger length is increased, an increase in the source inductance can be suppressed. In the gate pitch dependence of FIG. 6, it can be understood that, as the gate pitch is increased, the via hole area is also increased, so that the source inductance is correspondingly reduced.

As described above, by using the structure of this embodiment, the source inductance can be reduced and the linear gain can be improved. by this,
Since the finger length can be increased without deteriorating the RF performance, a margin can be provided for the chip width, and the gate pitch can be increased. Increasing the gate pitch not only has the effect of further reducing the source inductance, but also leads to an improvement in thermal stability by reducing the thermal resistance. Also, by extending the finger length,
The gate width can be increased, and the output of the FET can be further increased.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows the structure of the FET according to the second embodiment of the present invention. FET 17 of the present embodiment
Has a fishbone gate structure in which the gate fingers 3a and 3b are divided into two stages. The fishbone gate structure has a gate finger 3 to prevent an increase in gate resistance due to extension of the gate finger.
a and 3b, and the upper and lower gate fingers 3a are separated by the first gate bus bar 2a and the second gate bus bar 2b.
3b is connected.

FIG. 9 shows a conventional FET 19 having a fishbone gate structure. In the conventional fishbone gate structure, although the gate is divided, the source finger 6 and the drain finger 8 cannot be divided due to the structure, and a decrease in gain due to an increase in source inductance is inevitable. On the other hand, the FET 1 of the present embodiment shown in FIG.
By providing the source pad 9 at the tip of the source finger 6 and providing the via hole 11 as in 7, the source inductance can be reduced.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, specific numerical values such as a finger length, a gate-to-gate pitch, a gate-to-source distance, a dimension of a source pad, and a diameter of a via hole can be arbitrarily changed without being limited to the above embodiment. .

[0020]

As described in detail above, according to the semiconductor device of the present invention, the source inductance can be reduced, and the linear gain of the TFT can be improved. As a result, it is possible to increase the finger length without deteriorating the RF performance, so that it is possible to allow a margin in the chip lateral width and to increase the gate pitch. Increasing the gate pitch not only has the effect of further reducing the source inductance, but also leads to an improvement in thermal stability by reducing the thermal resistance. In addition, by increasing the finger length, the gate width can be increased, and a higher output of the FET can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of an FET in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a plan view showing an example of an FET in a conventional semiconductor device.

FIG. 4 is a graph showing results of measuring RF characteristics of the FET according to the first embodiment and a conventional FET.

FIG. 5 is a graph showing the finger length dependence of linear gain in the FET of the first embodiment and a conventional FET.

FIG. 6 is a graph showing gate pitch dependence of linear gain in the FET of the present embodiment and a conventional FET.

FIG. 7 is a graph showing frequency characteristics of MSG / MAG calculated from small signal parameter measurement values of the FET of the present embodiment and a conventional FET.

FIG. 8 is a plan view showing a structure of an FET in a semiconductor device according to a second embodiment of the present invention.

FIG. 9 shows a conventional FET having a fishbone gate structure.
It is a top view which shows an example.

[Explanation of symbols]

 1,17 FET (field effect transistor) 2,2a, 2b Gate bus bar 3,3a, 3b Gate finger 4 Gate pad 5 First source pad 6 Source finger 7 Drain pad 8 Drain finger 9 Second source pad 10,11 Via hole 12 Gold plating layer 13 Insulation film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 29/778 H01L 29/80-29/812

Claims (2)

(57) [Claims] 1. A semiconductor device comprising a field-effect transistor in which a gate electrode, a source electrode, and a drain electrode have a plurality of fingers, wherein a source finger and a drain extend from a first source pad with each gate finger interposed therebetween. A drain finger extending from the pad is provided, and a second source pad is provided in a non-operating region of the field-effect transistor at the tip of each of the source fingers. The first source pad and the second source pad A via hole is provided for each of the second sources;
Via holes provided in pads are gold plated from the back side
A semiconductor device characterized in that a source electrode is grounded through these via holes by being buried by a layer . 2. The semiconductor device according to claim 1, wherein each gate finger is divided into a plurality of gate fingers, and the divided gate fingers are electrically connected by a plurality of gate bus bars.