JP7683928B2 - Semiconductor Device - Google Patents

Description

The present disclosure relates to a semiconductor device, for example a semiconductor device having a field effect transistor.

In a field effect transistor (FET) having a source, gate, and drain, it is known to arrange multiple unit FETs having source fingers, gate fingers, and drain fingers in the direction in which the fingers extend (for example, Patent Document 1).

JP 2002-299351 A

In Patent Document 1, the gate fingers in a unit FET can be shortened by arranging multiple unit FETs in the extension direction of the fingers. However, connecting the gate fingers of unit FETs adjacent in the extension direction to the same gate wiring may degrade the high-frequency characteristics. If one gate finger of adjacent unit FETs is connected to the gate wiring and the other gate finger is not connected to the gate wiring, the distance between adjacent unit FETs cannot be reduced. This results in an increase in the size of the semiconductor device.

This disclosure was made in consideration of the above problems, and aims to provide a semiconductor device that can be miniaturized.

One embodiment of the present disclosure includes a substrate, a first source finger provided on the substrate, a first gate finger provided on the substrate adjacent to the first source finger in the width direction and extending in the extension direction of the first source finger, a first drain finger provided on the substrate and sandwiching the first gate finger between the first source finger, a second source finger provided on the substrate in the extension direction of the first source finger and extending in the extension direction, a second gate finger provided on the substrate adjacent to the second source finger in the width direction and extending in the extension direction of the first gate finger, and a second gate finger provided on the substrate and extending in the extension direction. , a second drain finger sandwiching the second gate finger; and a first gate wiring provided on the substrate, connected to a first end of the first gate finger, not connected to the second gate finger, and extending in the width direction, wherein the width of the first gate wiring in the extension direction at a first location where the first gate finger connects to the first gate wiring is smaller than the width of the first gate wiring in the extension direction at a second location located between the first source finger and the second source finger, and the second gate finger side end at the first location in the extension direction is located closer to the first gate finger than the second gate finger side end at the second location in the extension direction.

This disclosure makes it possible to provide a semiconductor device that can be miniaturized.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line AA of FIG. FIG. 3 is a cross-sectional view taken along line BB of FIG. FIG. 4 is a cross-sectional view taken along the line CC of FIG. FIG. 5 is a cross-sectional view taken along line DD of FIG. FIG. 6 is a plan view showing an active region, an ohmic metal layer, and a gate metal layer in the semiconductor device in accordance with the first embodiment. FIG. 7 is an enlarged plan view of the semiconductor device in accordance with the first embodiment. FIG. 8 is an enlarged plan view of the semiconductor device according to the first comparative example. FIG. 9 is an enlarged plan view of a semiconductor device according to a first modification of the first embodiment. FIG. 10 is an enlarged plan view of a semiconductor device according to a second modification of the first embodiment. FIG. 11 is a plan view showing an active region, an ohmic metal layer, and a gate metal layer in a semiconductor device in accordance with the second embodiment.

[Description of the embodiments of the present disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.

[Details of the embodiment of the present disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.
(1) One embodiment of the present disclosure includes a substrate, a first source finger provided on the substrate, a first gate finger provided on the substrate adjacent to the first source finger in a width direction and extending in an extension direction of the first source finger, a first drain finger provided on the substrate and sandwiching the first gate finger between the first source finger, a second source finger provided on the substrate in the extension direction of the first source finger and extending in the extension direction, a second gate finger provided on the substrate adjacent to the second source finger in the width direction and extending in the extension direction of the first gate finger, and a second gate finger provided on the substrate and a first gate wiring provided on the substrate, connected to a first end of the first gate finger and not connected to the second gate finger, and extending in the width direction, wherein a width of the first gate wiring in the extension direction at a first location where the first gate finger is connected to the first gate wiring is smaller than a width of the first gate wiring in the extension direction at a second location located between the first source finger and the second source finger, and a side end of the second gate finger at the first location in the extension direction is located closer to the first gate finger than a side end of the second gate finger at the second location in the extension direction. This makes it possible to provide a semiconductor device that can be miniaturized.
(2) When viewed in the width direction, it is preferable that a portion of the second gate finger and a portion of the first gate wiring overlap each other.
(3) It is preferable that the first gate line has a width in the extension direction that gradually increases from the first location to the second location.
(4) It is preferable that the semiconductor device further comprises a gate bus bar provided on the substrate, to which the second gate finger is connected, and a second gate wiring that connects the first gate wiring and the gate bus bar and extends in the extension direction.
(5) It is preferable that the second gate wiring and the second gate finger sandwich the second source finger.
(6) It is preferable that a width of the second source finger is smaller than a width of the first source finger, and a width of the second gate wiring in the width direction is within the width of the first source finger.
(7) It is preferable to provide a via penetrating the substrate and connecting the first source finger with a metal layer provided under the substrate.
(8) It is preferable to further include a source wiring that connects the first source finger and the second source finger and crosses the first gate wiring without contacting the first gate wiring.
(9) The substrate preferably comprises a first active region and a second active region in which a semiconductor layer in the substrate is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive, the first source finger, the first gate finger and the first drain finger being provided on the first active region, the second source finger, the second gate finger and the second drain finger being provided on the second active region, and the first gate wiring being provided on the inactive region.
(10) A third gate finger provided on the substrate and sandwiching the first source finger between the first gate finger, a third drain finger provided on the substrate and sandwiching the third gate finger between the first source finger, a third source finger provided on the substrate and having a width smaller than a width of the first source finger, the width in the width direction being within a width of the first source finger, provided on the same side as the second source finger with respect to the first source finger and extending in the extension direction, a fourth gate finger provided on the substrate in the extension direction of the third gate finger adjacent to the third source finger in the width direction, and extending in the extension direction, and a third gate wiring provided on the substrate, connected to a first end of the third gate finger but not connected to the fourth gate finger, and extending in the width direction, wherein a width of the third gate wiring in the extension direction at a third location where the third gate finger is connected to the third gate wiring is smaller than a width of the third gate wiring in the extension direction at a fourth location located between the first source finger and the third source finger, and a side end of the fourth gate finger at the third location in the extension direction is preferably located closer to the third gate finger than a side end of the fourth gate finger at the fourth location in the extension direction.

Specific examples of semiconductor devices according to embodiments of the present disclosure are described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is intended to include all modifications within the scope of the claims and meaning equivalent to the claims.

[Example 1]
Fig. 1 is a plan view of a semiconductor device according to a first embodiment. Figs. 2 to 5 are cross-sectional views taken along lines A-A to D-D in Fig. 1, respectively. The normal direction to the top surface of the substrate 10 is the Z direction, the extension direction of each finger is the Y direction, and the width direction of each finger is the X direction.

As shown in Figures 1 to 5, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is the inactive region 11a, and the region that has not been inactivated is the active region 11. Source fingers 12a to 12c, gate fingers 14a to 14d, drain fingers 16a, 16b, gate wiring 18a, 18b1, and 18b2, a gate bus bar 22, and a drain bus bar 24 are provided on the substrate 10.

The source fingers 12a to 12c and the drain fingers 16a and 16b have an ohmic metal layer 40 provided on the active region 11 and a low resistance layer 50 provided on the ohmic metal layer 40. The ohmic metal layer 40 is in ohmic contact with the semiconductor layer 10b. The low resistance layer 50 has a lower resistivity and is thicker than the ohmic metal layer 40. In the source fingers 12a to 12c and the drain fingers 16a and 16b, the width of the ohmic metal layer 40 in the X direction and the Y direction may be larger than or the same as the width of the low resistance layer 50 in the X direction and the Y direction. The source wiring 19b connects the source fingers 12a and 12b, and the source wiring 19c connects the source fingers 12a and 12c. The source wirings 19b and 19c are provided on the inactive region 11a, have the low resistance layer 50, and do not have the ohmic metal layer 40. The portions of the drain fingers 16a and 16b above the inactive region 11a have a low resistance layer 50 and do not have an ohmic metal layer 40.

The gate fingers 14a to 14d have a gate metal layer 45 provided on the active region 11, and do not have a low resistance layer 50. The gate wiring 18b1 has a gate metal layer 45 provided on the inactive region 11a, and does not have a low resistance layer 50. The gate wiring 18a has a gate metal layer 45 and a low resistance layer 50 provided on the semiconductor layer 10b. The low resistance layer 50 has a lower resistivity and is thicker than the gate metal layer 45.

The source finger 12a extends in the Y direction and has a width W2a in the X direction and a length L2a in the Y direction. Source fingers 12b and 12c extend in the Y direction from both ends of the source finger 12a in the X direction. The source fingers 12b and 12c each have a width W2b in the X direction and a length L2b in the Y direction. A drain finger 16a is provided extending in the Y direction in the +X direction of the source fingers 12a and 12b. A drain finger 16b is provided extending in the Y direction in the -X direction of the source fingers 12a and 12c. The drain fingers 16a and 16b each have a width W6 in the X direction. The gate fingers 14a and 14b are provided between the source fingers 12a and 12b and the drain finger 16a, and the gate fingers 14c and 14d are provided between the source fingers 12a and 12c and the drain finger 16b. Gate fingers 14a to 14d extend in the Y direction, and their width in the X direction corresponds to the gate length Lg.

Between the source fingers 12a and 12c, a gate wiring 18a is provided that extends in the Y direction and has a width W8a in the X direction. Between the gate fingers 14a and 14c and between the gate fingers 14b and 14d, gate wirings 18b1 and 18b2 are provided. The gate wirings 18b1 and 18b2 have a width W8b in the Y direction and extend in the X direction, respectively connecting the -Y direction ends of the gate fingers 14a and 14c and the +Y direction end of the gate wiring 18a. The gate wirings 18b1 and 18b2 cross the source wirings 19b and 19c via the insulating film 26 and are not electrically connected to each other. The -Y direction ends of the gate fingers 14b, 14d and the gate wiring 18a are connected to the gate bus bar 22. The +Y direction ends of the drain fingers 16a and 16b are connected to the drain bus bar 24. The source finger 12a is connected to a metal layer 28 provided under the substrate 10 through a via 20 that penetrates the substrate 10. An insulating film 26 is provided to cover the source fingers 12a to 12c, the gate fingers 14a to 14d, the drain fingers 16a, 16b, and the gate wirings 18a, 18b1, and 18b2.

The FET regions 30a and 30b are arranged in the Y direction. In the FET region 30a, the active region 11 including the source finger 12a extends in the X direction. The source finger 12a, the gate finger 14a, and the drain finger 16a form a unit FET 32a, and the source finger 12a, the gate finger 14c, and the drain finger 16b form a unit FET 32c. The gate width Wga of the unit FETs 32a and 32c corresponds to the length in the Y direction of the active region 11 including the source finger 12a. The source potential of the unit FETs 32a and 32c is supplied to the source finger 12a from the metal layer 28 through the via 20. The gate potential (and gate signal) is supplied from the gate bus bar 22 to the gate fingers 14a and 14c through the gate wirings 18a, 18b1, and 18b2. The drain potential is supplied from the drain bus bar 24 to the drain fingers 16a and 16b. Unit FETs 32a and 32c are arranged alternately in the X direction.

In the FET region 30b, the active region 11 is provided except for the gate wiring 18a. The source finger 12b, the gate finger 14b, and the drain finger 16a form the unit FET 32b, and the source finger 12c, the gate finger 14d, and the drain finger 16b form the unit FET 32d. The gate width Wgb of the unit FETs 32b and 32d corresponds to the length in the Y direction in the active region 11 including the source fingers 12b and 12c. The source potential of the unit FETs 32b and 32d is supplied from the metal layer 28 to the source fingers 12b and 12c through the via 20 and the source finger 12a. The gate potential (and gate signal) is supplied from the gate bus bar 22 to the gate fingers 14b and 14d. The drain potential is supplied from the drain bus bar 24 to the drain fingers 16a and 16b. The unit FETs 32b and 32d are arranged alternately in the X direction. To increase the overall gate width of the semiconductor device, multiple unit FETs 32a to 32d are arranged in the X direction.

6 is a plan view showing active regions 11b, 11c1, 11c2, an ohmic metal layer 40, and a gate metal layer 45 in a semiconductor device according to the first embodiment. As shown in FIG. 6, an active region 11b is provided in a FET region 30a of a substrate 10, and active regions 11c1 and 11c2 are provided in a FET region 30b. On the active region 11b, a source finger 12a and drain fingers 16a1 and 16b1 are provided by an ohmic metal layer 40, and gate fingers 14a and 14c are provided by a gate metal layer 45. On the active region 11c1, a source finger 12b and a drain finger 16a2 are formed by an ohmic metal layer 40, and a gate finger 14b is formed by a gate metal layer 45. On the active region 11c2, a source finger 12c and a drain finger 16b2 are formed by an ohmic metal layer 40, and a gate finger 14d is formed by a gate metal layer 45. Drain fingers 16a1 and 16a2 are connected by a low resistance layer 50 to form drain finger 16a in FIG. 1. Drain fingers 16b1 and 16b2 are connected by a low resistance layer 50 to form drain finger 16b in FIG. 1.

In unit FET 32a, gate finger 14a (first gate finger) is provided adjacent to source finger 12a (first source finger) in the X direction (width direction). Drain finger 16a1 (first drain finger) sandwiches gate finger 14a with source finger 12a. In unit FET 32b, source finger 12b (second source finger) is provided in the -Y direction of source finger 12a. Gate finger 14b (second gate finger) is provided adjacent to source finger 12b in the X direction in the -Y direction of gate finger 14a. Drain finger 16a2 (second drain finger) sandwiches gate finger 14b with source finger 12b. Gate wiring 18b1 (first gate wiring) is connected to the first end (-Y side end) of gate finger 14a, is not connected to gate finger 14b, and extends in the X direction.

In the unit FET 32c, the gate finger 14c (third gate finger) sandwiches the source finger 12a with the gate finger 14a. The drain finger 16b1 (third drain finger) sandwiches the gate finger 14c with the source finger 12a. In the unit FET 32d, the source finger 12c (third source finger) is provided on the same side as the source finger 12b with respect to the source finger 12a. The gate finger 14d (fourth gate finger) is provided adjacent to the source finger 12c in the X direction and in the -Y direction of the gate finger 14c. The drain finger 16b2 (fourth drain finger) sandwiches the gate finger 14d with the source finger 12c. The gate wiring 18b2 (third gate wiring) is connected to the first end (-Y side end) of the gate finger 14c, is not connected to the gate finger 14d, and extends in the X direction.

Gate wiring 18b1 is provided on the inactive region 11a between active regions 11b and 11c1. Gate wiring 18b2 is provided on the inactive region 11a between active regions 11b and 11c2. Gate wiring 18a is provided on the inactive region 11a between active regions 11c1 and 11c2. The first ends (-Y side ends) of gate fingers 14b, 14c and gate wiring 18a are connected to gate bus bar 22. Gate wiring 18b1 connects gate finger 14a and gate wiring 18a. Gate wiring 18b2 connects gate finger 14c and gate wiring 18a. The second ends (+Y side ends) of gate fingers 14b and 14d are not connected to gate wiring 18b1 and 18b2.

When the semiconductor device is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and/or an InGaN layer. When the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and/or an InGaAs layer. The ohmic metal layer 40 is a metal film, for example, an adhesion film (for example, a titanium film) and an aluminum film from the substrate 10 side. The gate metal layer 45 is a metal film, for example, an adhesion film (for example, a nickel film) and a gold film from the substrate 10 side. The low resistance layer 50 is a metal layer, for example, a barrier layer (for example, a titanium tungsten film) and a gold film. The source fingers 12a to 12c and the drain fingers 16a and 16b may not have the low resistance layer 50. The gate wiring 18a may not have the gate metal layer 45. The gate bus bar 22 may have the gate metal layer 45 and the low resistance layer 50, or may have the low resistance layer 50 and not have the gate metal layer 45. The drain bus bar 24 may have the ohmic metal layer 40 and the low resistance layer 50, or may have the low resistance layer 50 and not have the ohmic metal layer 40. The via 20 and the metal layer 28 are, for example, an adhesion layer and a gold layer from the substrate 10 side. The insulating film 26 is, for example, a silicon nitride film.

The width W2a of the source finger 12a in the X direction is, for example, 50 μm to 100 μm, and the length L2a in the Y direction is, for example, 100 μm to 400 μm. The width W2b of the source fingers 12b and 12c in the X direction is, for example, 5 μm to 20 μm, and the length L2b in the Y direction is, for example, 110 μm to 410 μm. The gate length Lg of the gate fingers 14a to 14d in the X direction is, for example, 0.25 μm to 2 μm. The width W6 of the drain fingers 16a and 16b in the X direction is, for example, 5 μm to 100 μm. The width W8a of the gate wiring 18a is, for example, 5 μm to 20 μm. The width W8b of the gate wirings 18b1 and 18b2 is, for example, 5 μm to 20 μm. The gate width Wga of the unit FETs 32a and 32c is, for example, 100 μm to 400 μm, and the gate width Wgb of the unit FETs 32b and 32d is, for example, 100 μm to 400 μm. The width W20 of the via 20 is, for example, 10 μm to 60 μm.

7 is an enlarged plan view of the semiconductor device according to the first embodiment. As shown in FIG. 7, the width W8c in the Y direction of the gate wiring 18b1 at the first point where the gate finger 14a is connected to the gate wiring 18b1 is smaller than the width W8d in the Y direction of the gate wiring 18b1 at the second point between the source fingers 12a and 12b. The width of the gate wiring 18b1 in the Y direction increases linearly as it goes in the -X direction. The distance by which the gate finger 14b protrudes from the active region 11c1 is L4a, the distance in the Y direction between the gate finger 14b and the gate wiring 18b1 is L8a, and the shortest distance between the gate finger 14b and the gate wiring 18b1 is L8b. The width W8c is, for example, 1 μm to 5 μm, and the width W8c is, for example, 5 μm to 20 μm. The distance L4a is, for example, 1 μm to 10 μm, and the distances L8a and L8b are, for example, 5 μm to 20 μm.

Figure 8 is an enlarged plan view of a semiconductor device according to Comparative Example 1. As shown in Figure 8, in Comparative Example 1, the planar shape of gate wiring 18b1 is rectangular. The width of gate wiring 18b1 is W8b, the distance that gate finger 14b protrudes from active region 11c1 is L4a, and the distance in the Y direction between gate finger 14b and gate wiring 18b1 is L8c.

1 and 6, when a high-frequency signal is input to the gate bus bar 22, the high-frequency signal is supplied from the gate bus bar 22 to the gate fingers 14b and 14d. The high-frequency signal is also supplied from the gate bus bar 22 to the gate fingers 14a and 14c via the gate wirings 18a, 18b1, and 18b2, respectively. When the gate wirings 18b1 and 18b2 are connected to the gate fingers 14b and 14d, the high-frequency signals are supplied from the gate wirings 18b1 and 18b2 to the gate fingers 14b and 14d, respectively. As a result, the high-frequency signal supplied from the gate bus bar 22 to the gate fingers 14b and 14d is in phase with the high-frequency signal supplied from the gate wirings 18b1 and 18b2. This causes an increase in loss and deteriorates the high-frequency characteristics.

In Comparative Example 1, the gate wirings 18b1 and 18b2 are not connected to the gate fingers 14b and 14d. As a result, high-frequency signals are not supplied from the gate wirings 18b1 and 18b2 to the gate fingers 14b and 14d, respectively. This makes it possible to suppress deterioration of high-frequency characteristics. In addition, the first ends (-Y side ends) of the gate fingers 14b and 14d are connected to the gate bus bar 22, and the second ends (+Y side ends) are separated from the gate wirings 18b1 and 18b2. As a result, a phase difference occurs between the gate signals supplied from the gate bus bar 22 to the gate fingers 14b and 14d and the gate signals supplied from the gate wirings 18a, 18b1, and 18b2 to the gate fingers 14a and 14c. However, gate signals are supplied to the gate fingers 14a to 14d from the same -Y direction, and signals are output from the drain fingers 16a and 16b in the +Y direction. This makes it possible to suppress losses due to phase differences. This improves high-frequency characteristics.

The gate finger 14b protrudes a distance L4a from the active region 11c1. If the gate wiring 18b1 and the gate finger 14b become too close, the high-frequency signal transmitted through the gate wiring 18b1 will leak to the gate finger 14b, degrading the high-frequency characteristics. To prevent this, the gate wiring 18b1 and the gate finger 14b are spaced apart by a distance L8c. The gate wiring 18b1 and the active region 11c1 are spaced apart by a distance L4a + L8c. This results in an increase in the size of the substrate 10.

According to the first embodiment, as shown in FIG. 7, the width W8c of the gate wiring 18b1 in the Y direction at the first location where the gate finger 14a connects to the gate wiring 18b1 is smaller than the width W8d of the gate wiring 18b1 in the Y direction at the second location located between the source fingers 12a and 12b. The gate finger 14b side (-Y side) end Y1 of the first location in the Y direction is located closer to the gate finger 14a side (+Y side) than the gate finger 14b side (-Y side) end Y2 of the second location in the Y direction. As a result, even if the distances L8a and L8b between the gate wiring 18b1 and the gate finger 14b are secured to be approximately the same as the distance L8c in the first comparative example, the active region 11c1 can be brought closer to the gate wiring 18b1. Therefore, the area of the substrate 10 can be reduced, and the semiconductor device can be miniaturized. In addition, when the area of the substrate 10 is the same in Comparative Example 1 and Example 1, the width Wgb of the active region 11c1 in the Y direction can be made larger in Example 1 compared to Comparative Example 1. This allows for a larger output. From the viewpoint of miniaturization, the width W8c is preferably 2/3 or less of the width W8d, and more preferably 1/2 or less. From the viewpoint of reducing the resistance of the gate wiring 18b1, the width W8c is preferably 1/10 or more of the width W8d.

In Comparative Example 1, it is also possible to reduce the width W8b. However, reducing the width W8b increases the resistance of the gate wiring 18b1, degrading the high-frequency characteristics. In Example 1, the width W8d of the gate wiring 18b1 can be increased, so the resistance of the gate wiring 18b1 can be reduced and degradation of the high-frequency characteristics can be suppressed.

When viewed from the X direction, a portion of the gate finger 14b overlaps a portion of the gate wiring 18b1. That is, the end of the gate finger 14b on the +Y side is located between Y1 and Y2. This allows the active region 11c1 to be closer to the gate wiring 18b1. This allows the semiconductor device to be made smaller.

As shown in FIG. 1 and FIG. 6, gate fingers 14b and 14d are connected to gate bus bar 22. Gate wiring 18a (second gate wiring) connects gate wirings 18b1 and 18b2 to gate bus bar 22. In this case, if gate finger 14b is connected to gate wiring 18b1, high frequency characteristics are degraded. Therefore, if gate finger 14b and gate wiring 18b1 are separated, as in Comparative Example 1, the semiconductor device becomes larger. Therefore, as shown in FIG. 7, it is preferable to make width W8c of gate wiring 18b1 smaller than width W8d.

As shown in Figures 1 and 6, the gate wiring 18a and the gate finger 14b sandwich the source finger 12b. This means that the gate wiring 18a and the source finger 12b do not overlap in a planar view. This makes it possible to suppress the gate-source capacitance and improve the high-frequency characteristics.

The width W2a of the source finger 12a in the X direction may be designed to be wide. For example, the source inductance can be reduced by supplying a source potential to the source finger 12a through the via 20. However, the width W2a of the source finger 12a becomes wide. On the other hand, the width W2b of the source fingers 12b and 12c for supplying a source potential in the Y direction does not need to be as wide as the width W2a. Therefore, as shown in FIG. 1, the width W2b of the source finger 12b is smaller than the width W2a of the source finger 12a, and the width W8a of the gate wiring 18a in the X direction is within the width W2a of the source finger 12a. That is, when viewed from the Y direction, the gate wiring 18a and the source fingers 12b and 12c overlap the source finger 12a and do not overlap areas other than the source finger 12a. As a result, even if the gate wiring 18a is provided, the width in the X direction of the semiconductor device can be suppressed. Therefore, the semiconductor device can be made smaller.

The via 20 penetrates the substrate 10 and connects the source finger 12a to the metal layer 28 provided under the substrate 10. When the via 20 is directly connected to the source finger 12a in this manner, the width W2a of the source finger 12a becomes wider. Therefore, the gate wiring 18a can be provided between the source fingers 12b and 12c.

Source wiring 19b connects source fingers 12a and 12b and crosses gate wiring 18b1 without contact. This electrically connects source fingers 12a and 12b and allows a high-frequency signal to be supplied from gate wiring 18b1 to gate finger 14a.

The semiconductor layer 10b in the substrate 10 is activated to form an active region 11b (first active region) and an active region 11c1 (second active region), which are separated from each other, and an inactive region 11a is provided between the active regions 11b and 11c1, where the semiconductor layer 10b is inactivated. The source finger 12a, the gate finger 14a, and the drain finger 16a1 are provided on the active region 11b. The source finger 12b, the gate finger 14b, and the drain finger 16a2 are provided on the active region 11c1. The gate wiring 18b1 is provided on the inactive region 11a. This reduces the gate-source capacitance due to the gate wiring 18b1, and improves the high-frequency characteristics.

As shown in FIG. 6, in FETs 32c and 32d, the width of gate wiring 18b2 in the Y direction at a third location where gate finger 14c connects to gate wiring 18b2 is smaller than the width of gate wiring 18b2 in the Y direction at a fourth location located between source finger 12a and source finger 12c. The end of gate finger 14d at the third location in the Y direction (-Y side) is located closer to gate finger 14c (+Y side) than the end of gate finger 14d at the fourth location in the Y direction (-Y side). This allows the semiconductor device to be miniaturized.

[Modification 1 of Example 1]
9 is an enlarged plan view of a semiconductor device according to a first modification of the first embodiment. As shown in FIG. 9, the width W8c in the Y direction of the +X side portion of the gate wiring 18b1 is constant, and the width W8c in the Y direction of the -X side portion is constant. The distance in the X direction between the gate finger 14b and the gate wiring 18b1 is L8d. The same applies to the gate wiring 18b2. The other configurations are the same as those of the first embodiment, and the description will be omitted. In the first modification of the first embodiment, the distance L8d is set to be approximately the same as the distance L8a, so that leakage of high frequency signals from the gate wiring 18b1 to the gate finger 14b can be suppressed. In addition, the semiconductor device can be miniaturized.

[Modification 2 of Example 1]
10 is an enlarged plan view of a semiconductor device according to Modification 2 of Example 1. As shown in FIG. 10, the width of the gate wiring 18b1 increases in a curved manner from a first point where the gate finger 14a is connected to the gate wiring 18b1 toward the −X direction. The −Y side of the gate wiring 18b1 is a substantially circular periphery centered on the end of the gate finger 14b on the +Y side. As a result, the shortest distance L8b between the gate finger 14b and the gate wiring 18b1 is substantially equal to the distances L8a and L8d. The same is true for the gate wiring 18b2. The other configurations are the same as those of Example 1, and description thereof will be omitted.

As in Example 1 and its modified example 1, the width of the gate wiring 18b1 in the Y direction gradually increases from the first location to the second location. This allows the area of the gate wiring 18b1 to be increased, and the gate resistance to be suppressed. As in modified example 2 of Example 1, the -Y side edge of the gate wiring 18b1 is made into a substantially circular periphery centered on the +Y side end of the gate finger 14b. This allows the area of the gate wiring 18b1 to be increased, and the gate resistance to be further suppressed.

[Example 2]
11 is a plan view showing an active region, an ohmic metal layer, and a gate metal layer in a semiconductor device according to a second embodiment. As shown in FIG. 11, in the second embodiment, the active regions 11c1 and 11c2 (see FIG. 6) are integrated to provide the active region 11c. The source fingers 12b and 12c (see FIG. 6) are integrated to provide the source finger 12bc. The width of the source finger 12bc in the X direction is approximately the same as the width of the source finger 12a in the X direction. The active region 11c extends in a strip shape in the X direction. The gate wiring 18a is formed of a low resistance layer 50 and is provided above the source finger 12bc via an insulating film 26. The other configurations are the same as those in the first embodiment, and will not be described.

As in Example 2, the gate wiring 18a may overlap the source fingers 12bc in a planar view. In Example 2, the gate-source capacitance becomes large. Therefore, as in Example 1, it is preferable that the gate wiring 18a does not overlap the source fingers 12b and 12c in a planar view.

In the first and second embodiments and their modified examples, an example in which four unit FETs are arranged in the X direction has been described, but the number of unit FETs in the X direction may be one, two, three, or five or more. Four unit FETs arranged in the X direction may form one group, and multiple groups may be arranged in the X direction. An example in which one source finger 12a has one via 20 has been described, but multiple vias 20 may be provided in one source finger 12a.

The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is indicated by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope of the claims.

10, 10a substrate 10b semiconductor layer 11, 11c2 active region 11a inactive region 11b active region (first active region)
11c1 Active region (second active region)
12a to 12c source fingers (first to third source fingers)
12bc source finger 14a to 14d gate fingers (first to fourth gate fingers)
16a, 16b Drain fingers 16a1, 16a2, 16b1, 16b2 Drain fingers (first to fourth drain fingers)
18a Gate wiring (second gate wiring)
18b1 Gate wiring (first gate wiring)
18b2 Gate wiring (third gate wiring)
19b Source wiring (first source wiring)
19c Source wiring (second source wiring)
20 via 22 gate bus bar 24 drain bus bar 26 insulating film 28 metal layer 30a to 30b FET regions 32a to 32d unit FETs
40 Ohmic metal layer 45 Gate metal layer 50 Low resistance layer

Claims (10)

A substrate;
a first source finger disposed on the substrate;
a first gate finger provided on the substrate adjacent to the first source finger in a width direction and along the first source finger;
a first drain finger provided on the substrate and sandwiching the first gate finger between the first source finger and the first drain finger;
a second source finger provided on a region of the substrate located in a direction in which the first source finger extends from the first source finger to the substrate; and
a second gate finger provided along the second source finger on a region of the substrate adjacent to the second source finger in the width direction and located from the first gate finger in the extension direction;
a second drain finger disposed on the substrate and sandwiching the second gate finger between the second source finger and the second drain finger;
a first gate wiring provided on the substrate, connected to a first end of the first gate finger, not connected to the second gate finger, and extending in the width direction;
Equipped with
a width of the first gate wiring in the extension direction at a first location where the first gate finger is connected to the first gate wiring is smaller than a width of the first gate wiring in the extension direction at a second location located between the first source finger and the second source finger;
A semiconductor device in which an end of the first location on the second gate finger side in the extension direction is located closer to the first gate finger than an end of the second location on the second gate finger side in the extension direction. The semiconductor device according to claim 1, wherein a portion of the second gate finger and a portion of the first gate wiring overlap when viewed in the width direction. The semiconductor device according to claim 1 or 2, wherein the width of the first gate wiring in the extension direction gradually increases from the first location to the second location. a gate bus bar provided on the substrate and to which the second gate finger is connected;
a second gate wiring that connects the first gate wiring and the gate bus bar and extends in the extension direction;
The semiconductor device according to claim 1 , further comprising: The semiconductor device according to claim 4, wherein the second gate wiring and the second gate finger sandwich the second source finger. a width of the second source finger is smaller than a width of the first source finger;
6. The semiconductor device according to claim 5, wherein the width of the second gate wiring in the width direction is within the width of the first source finger. The semiconductor device according to claim 6, further comprising a via that penetrates the substrate and connects the first source finger to a metal layer provided below the substrate. The semiconductor device according to any one of claims 1 to 7, further comprising a source wiring that connects the first source finger and the second source finger and intersects the first gate wiring without contacting the first gate wiring. the substrate includes a first active region and a second active region in which a semiconductor layer in the substrate is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive;
the first source finger, the first gate finger and the first drain finger are disposed on the first active region;
the second source finger, the second gate finger and the second drain finger are disposed on the second active region;
The semiconductor device according to claim 1 , wherein the first gate wiring is provided on the inactive region. a third gate finger provided on the substrate adjacent to the first source finger in a width direction and along the first source finger , the third gate finger sandwiching the first source finger between the first gate finger and the third gate finger;
a third drain finger provided on the substrate and sandwiching the third gate finger between the first source finger and the third drain finger;
a third source finger provided on the substrate, the third source finger having a width smaller than that of the first source finger, the width in the width direction being within the width of the first source finger, the third source finger provided on the same side as the second source finger with respect to the first source finger, and extending in the extension direction;
a fourth gate finger provided along the third source finger on a region of the substrate adjacent to the third source finger in the width direction and located from the third gate finger in the extension direction;
a fourth drain finger provided on the substrate and sandwiching the fourth gate finger between the third source finger and the fourth drain finger;
a third gate wiring provided on the substrate, connected to a first end of the third gate finger, not connected to the fourth gate finger, and extending in the width direction;
Equipped with
a width of the third gate wiring in the extension direction at a third location where the third gate finger is connected to the third gate wiring is smaller than a width of the third gate wiring in the extension direction at a fourth location located between the first source finger and the third source finger;
10. The semiconductor device according to claim 8, wherein the fourth gate finger side end of the third location in the extension direction is located closer to the third gate finger than the fourth gate finger side end of the fourth location in the extension direction.

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