JP3115208B2 - Duty limit circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty limiting circuit for preventing thermal destruction due to abnormal duty of a transmission signal of a radar transmitter or the like.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional duty limiting circuit for preventing thermal destruction due to abnormal duty of a transmission signal of a radar transmitter or the like. In the figure, reference numeral 1 denotes a transmission trigger input for setting a duty, reference numeral 2 denotes a basic clock for generating the timing of the transmission trigger input 1 and the like, reference numeral 3 denotes a transmission trigger input and a transmission ON time detection circuit which receives a clock, 4 is a transmission start trigger generated by the transmission ON time detection circuit 3 and 5 is a transmission start trigger 4
And a clock counting circuit which receives clock 2 as input, 6 is a transmission off expected time trigger which is an output of clock counting circuit 5,
Reference numeral 7 denotes a transmission off collation circuit which receives a transmission trigger input 1 and an expected transmission off time trigger 6 which is an output of the clock counting circuit 5; 8, a pass / fail signal which is an output of the transmission off collation circuit 7; The gate circuit 10 which receives 1 and the pass / fail signal 8 is a transmission trigger output which is the output of the gate circuit 9.

Next, the operation will be described. When a transmission trigger input 1 for setting the duty of a transmission signal and a basic clock 2 for generating the transmission trigger 1 and other timings are input to the transmission ON time detection circuit 3, the transmission ON time detection circuit 3 Shifts the transmission trigger input 1 by the clock 2 and generates the transmission start trigger 4 indicating the transmission start position. When the transmission start trigger 4 is input to the clock counting circuit 5, the clock counting circuit 5 starts counting the clock 2 from the time when the transmission start trigger 4 is received, and the transmission end time and the next transmission start time are respectively expected. A transmission off expected time trigger 6 which is a time is output. The transmission off matching circuit 7 receives the transmission off expected time trigger 6 and the transmission trigger input 1 and compares the timings of the two. The transmission ends at the time expected by the transmission trigger input 1 and the next transmission after the expected time. Confirm that
The result is given to the gate circuit 9 as a pass / fail signal 8. The gate circuit 9 passes or blocks the transmission trigger input 1 based on the result of the pass / fail signal 8, and the transmission trigger output 10
To the next processing circuit.

[0004]

Since the conventional duty limiting circuit is configured as described above, the clock 2 needs to be input normally in order to manage the duty of the transmission trigger input 1. The configuration of a conventional duty limiting circuit that detects an abnormality in the duty due to an abnormality in the transmission system on the premise that only the clock transmission system maintains the normality is impossible in its concept. Clock 2
In a system where is transmitted on the same path as the transmission trigger input 1, it can not be said that the clock 2 is usually more reliable than the transmission system of the transmission trigger input 1. Therefore, the conventional duty limiting circuit has a problem that it is not sufficient as a protection means for a transmitter or the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a safe and reliable duty limiting circuit that prevents thermal damage to a transmitter or the like due to abnormal duty.

[0006]

According to a first aspect of the present invention, a duty limiting circuit includes a power supply, a current sensor connected to an output of the power supply, an output of the current sensor as an input, and a power supply output control signal fed back to the power supply. Overcurrent determination circuit,
A voltage reduction detection circuit that receives the power supply output which has passed through the current sensor, a power output which has passed through the current sensor as input, after
Given bias to stage the pulsed load, and a bias generation circuit for output blocking signal from the voltage reduction detection circuit is controlled, at the time of duty abnormal overcurrent determination
The circuit detects overcurrent and the power output control signal is
Acts on the power supply to lower the voltage at the power supply output
At the same time, the undervoltage detection circuit judges the undervoltage,
The signal instructs the bias generation circuit to cut off the bias .

According to a second aspect of the present invention, there is provided a duty limiting circuit according to the first aspect, wherein the reduced voltage detecting circuit is connected via a resistor between the detected voltage and a power supply having the opposite polarity to the detected voltage. And a transistor having a base connected to a connection point between the Zener diode and the resistor, an emitter grounded, and a collector having a reduced voltage detection output terminal.

[0008]

According to a first aspect of the present invention, a current sensor detects an increase in load current due to an increase in the operating duty of a pulse load, and when the current value exceeds a certain value, reduces the output voltage to the power supply. So give feedback. A decrease in output voltage due to the feedback control, that is, a decrease in voltage is detected, and a bias generation circuit that supplies a bias to a pulse load is subjected to a bias cutoff control.

According to the duty limiting circuit of the present invention, when the detected voltage decreases, the emitter-collector of the transistor is turned on, and a voltage lower than the ground voltage by the emitter-collector voltage appears at the collector. The voltage appearing at the collector is treated as a cutoff signal to the bias circuit.

[0010]

【Example】

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a duty limiting circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 11 denotes a power source, 12 denotes a power output which is an output of the power source 11, 13 denotes a current sensor inserted in the middle of the path of the power output 12, 14 denotes a current sensor output having an output of the current sensor 13, 15
Is an overcurrent determination circuit having the current sensor output 14 as an input,
Reference numeral 6 denotes a power supply output control signal fed back from the overcurrent determination circuit 15 to the power supply 11, reference numeral 17 denotes a bias generation circuit having the power supply output 12 input through the current sensor 13, and reference numeral 18 inputs the power supply output 12 passed through the current sensor 13. The reference numeral 19 denotes a cutoff signal for controlling the output of the bias generation circuit 17 based on the output of the reduction voltage detection circuit 18, and 20 denotes a bias which is the output of the bias generation circuit 17.

Next, the operation will be described. A power supply output 12 from the power supply 11 is supplied to a bias generation circuit 17 via a current sensor 13, and the bias generation circuit 17 applies a bias 20 to a pulse load at a subsequent stage. Normally, the current sensor output 14 of the current sensor 13 does not exhibit an overcurrent, the overcurrent determination circuit 15 does not determine the overcurrent, and the power output control signal 16 Also do not give. Therefore, the power supply output 12 outputs a normal standard value. Then, the undervoltage detection circuit 18 does not determine that the voltage is undervoltage, and the cutoff signal 19 does not instruct the bias generation circuit 17 to cut off the bias 20. When the duty is abnormal, the average value of the bias current increases, and the current sensor output 14 of the current sensor 13 exhibits an overcurrent,
The overcurrent is determined by the overcurrent determination circuit 15, and the power output control signal 16 acts on the power supply 11 to reduce the voltage of the power output 12. Then, the undervoltage detection circuit 18 determines the undervoltage, and the cutoff signal 19 instructs the bias generation circuit 17 to cut off the bias 20, and finally protects the pulse load from thermal destruction.

According to this embodiment, the duty limit circuit detects an increase in load current due to an increase in the operation duty of the pulse load by the current sensor, and when the current value exceeds a certain value, the output voltage is applied to the power supply. Is applied to reduce the output voltage, and a decrease in the output voltage due to the feedback is detected, and the bias supply to the pulse load is cut off. Therefore, while the duty limiting circuit that operates in a logical manner presupposes the safe supply of the clock,
According to the present invention, even if those logic circuits are broken, if the pulse load attempts to operate with a duty over due to the result, the load current increases as described above, and the duty is limited in an analog manner. It can be protected from reaching.

Embodiment 2 FIG. Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram showing a reduced voltage limiting circuit of a duty limiting circuit according to Embodiment 2 of the present invention. In the figure, reference numeral 21 denotes a voltage to be detected, 22 denotes a Zener diode having a cathode (an anode when the voltage to be detected is negative) connected to the voltage to be detected 21, and 23 denotes an anode of the Zener diode 22 (a voltage to be detected is negative). A resistor having one end connected to the cathode), a power supply 24 having the opposite polarity to the detected voltage to which the other end of the resistor 23 is connected, and a base 25 connected to the connection point between the Zener diode 22 and the resistor 23. A PNP transistor (an NPN transistor when the voltage to be detected is negative) is connected, and the emitter is grounded to take out a signal from the collector.

Next, the operation will be described. The case where the detected voltage is a positive voltage will be described. Zener diode 2
A current flows through the power supply 2 and the resistor 23 from the power supply 24 having a polarity opposite to the detected voltage 21, and a voltage having a value lower than the detected voltage 21 by the Zener voltage of the Zener diode 22 appears at the anode of the Zener diode 22. Now, the detected voltage 2
1 and the Zener voltage are equal, the transistor 25
Becomes the same ground potential as the emitter, the base-emitter voltage of the transistor 25 becomes zero, and the emitter-collector is turned off. For example, when the collector is pulled down, a pull-down voltage appears at the collector. When the detected voltage 21 decreases, the detected voltage 21 is lower than the Zener voltage by the base of the transistor 25.
Emitter voltage (for a normal silicon transistor,
When the voltage drops to about 0.7 V) or more, the transistor 25
The base-emitter voltage is about 0.7 V, and as a result, the emitter-collector is turned on. For example, when the collector is pulled down, the collector-collector voltage is higher than the ground potential.
A voltage lower by the emitter-to-emitter voltage appears at the collector. The voltage appearing at the collector can be treated as a cutoff signal for the bias generation circuit.

[0015]

According to a first aspect of the present invention, there is provided a duty limiting circuit, comprising: a power supply; a current sensor connected to an output of the power supply; Circuit, a voltage reduction detection circuit that receives the power supply output that has passed through the current sensor as an input, and a pulse load that receives the power supply output that has passed through the current sensor as an input.
To give a bias, and a bias generation circuit for output blocking signal from the voltage reduction detection circuit is controlled, du
In the event of a malfunction, the overcurrent judgment circuit determines the overcurrent.
Power supply output control signal
It acts to lower the output voltage and
The detection circuit judges the undervoltage, and the cutoff signal generates a bias.
Since the circuit is configured to command the cutoff of the bias ,
A safe and reliable duty limiting circuit can be obtained as compared with a conventional logic duty limiting circuit using a clock having a transmission error as much as a transmission trigger.

According to a second aspect of the present invention, there is provided the duty limiting circuit according to the first aspect, wherein the reduced voltage detection circuit is connected via a resistor between the detected voltage and a power supply having a polarity opposite to the detected voltage. And a transistor with the base connected to the connection point of the Zener diode and the resistor, the emitter grounded, and the collector used as the reduced voltage detection output terminal. Is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a duty limiting circuit according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of a reduced voltage detection circuit of a duty limiting circuit according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram of a conventional duty limiting circuit.

[Explanation of symbols]

11 power supply, 12 power supply output, 13 current sensor, 14
Current sensor output, 15 overcurrent determination circuit, 16 power supply output control signal, 17 bias generation circuit, 18 reduced voltage detection circuit, 19 cutoff signal, 21 detected voltage, 22 zener diode, 23 resistance, 24 power supply of opposite polarity,
25 Transistor thin wire.

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04B 1/04 G01S 7/282 H03F 1/52

Claims (2)

(57) [Claims] A power supply; a current sensor connected to an output of the power supply; an overcurrent determination circuit that receives an output of the current sensor as an input and feeds back a power supply output control signal to the power supply; the aforementioned and the voltage reduction detection circuit for a power output and input, and inputs the power supply output which has passed through the current sensor, after
Given bias to stage the pulsed load, and a bias generation circuit for output blocking signal from the reduced voltage detecting circuit is controlled, at the time of duty abnormalities, the overcurrent determination
An overcurrent is determined in the circuit, and the power output control signal is output.
The signal reduces the voltage of the power supply output with respect to the power supply.
And the undervoltage detection circuit determines the undervoltage.
And the cutoff signal is applied to the bias generation circuit.
A duty limiting circuit for commanding to shut off EAS . 2. A reduced voltage detection circuit comprising: a Zener diode connected via a resistor between a detected voltage and a power supply having a polarity opposite to the detected voltage; and a base connected to a connection point between the Zener diode and the resistor. 2. A duty limiting circuit according to claim 1, further comprising a transistor having an emitter grounded and a collector having a reduced voltage detection output terminal.