JP3121062B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a main memory into a hardware area and a software area, stores an instruction execution procedure in the hardware area, and detects a compound instruction or a specific event in the software area. The present invention relates to a technique effective when applied to an information processing apparatus capable of executing an instruction execution procedure in a wear area.

[0002]

2. Description of the Related Art Conventionally, in this type of information processing apparatus, for example, as described in Japanese Patent Publication No. 59-9937,
A series of instruction execution procedures in the hardware area is configured by a combination of instructions executed in the software area.

[0003]

However, in the above-mentioned prior art, the memory access control in each of the software area and the hardware area is described, but the memory access control in each of the software area and the hardware area is described. No consideration is given to instruction exception information detection control, and an instruction whose execution is controlled according to the processing mode of the information processing apparatus is included in the instruction execution procedure in the hardware area (for example,
In the case of the M-series processor manufactured by Hitachi, Ltd., there is a problem that execution of an instruction execution procedure in the hardware area is restricted when a BASR instruction causes an instruction exception in the M mode.

It is an object of the present invention to control the detection of instruction exception information of an instruction executed in a software area and of an instruction executed in a hardware area independently of each other. An object of the present invention is to provide an information processing apparatus capable of executing an instruction execution procedure in a hardware area regardless of a mode.

[0005] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the information processing apparatus of the present invention divides the main memory into a software area and a hardware area, stores normal software in the software area, and stores a specific instruction or a specific instruction of the software area in the hardware area. An information processing apparatus that stores an instruction execution procedure for an event, and executes an instruction execution procedure in a hardware area corresponding to the issuance of a specific instruction or the occurrence of a specific event when the specific instruction is issued. The first logic circuit indicates that the instruction is in the middle, and the second logic circuit exclusively detects the instruction exception information of the instruction executed in the hardware area.

[0008]

According to the information processing apparatus described above, by providing the first logic circuit and the second logic circuit, when the instruction sequence is executed in the hardware area and when it is executed in the software area, Thus, the instruction exception information can be independently detected.

That is, if the instruction to be executed is part of the instruction execution procedure in the software area, the instruction exception information is detected as before, while if it is part of the instruction execution procedure in the hardware area, In addition, the second logic circuit provided exclusively for the hardware area can detect the instruction exception information independently of the software area and independently of the mode of the information processing apparatus.

Thus, the instructions that can be used in creating the instruction execution procedure in the hardware area are expanded, and it is not necessary to be aware of the mode of the information processing apparatus executed in the instruction execution procedure.

[0011]

FIG. 1 is a schematic configuration diagram showing a main part of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is an explanatory view showing a divided state of a main memory in the information processing apparatus according to the present embodiment. FIG. 6 is an explanatory diagram showing a state of execution of an instruction execution procedure in the embodiment.

First, the main configuration of the information processing apparatus according to the present embodiment will be described with reference to FIG.

The information processing apparatus of this embodiment is, for example, an information processing apparatus in which a main memory is divided into a software area and a hardware area, and generates an instruction register 1 for storing instruction data information and software area instruction exception information. Software area instruction exception information detection circuit 2 to generate hardware area instruction exception information detection circuit (second logic circuit) 3 for generating hardware area instruction exception information, and macro mode flip-flop (first logic Circuit) 4
And a selector 5 for selecting software area instruction exception information or hardware area instruction exception information according to the mode.

The main memory is divided into, for example, a software area 6 and a hardware area 7 as shown in FIG. 2, and an operating system is stored in the software area 6 in the same manner as a conventional main memory. The hardware area 7 stores a compound instruction stored in the software area 6 or an instruction execution procedure to be executed when a specific event is detected.

Next, the operation of this embodiment will be described.

First, the logical operation of the information processing apparatus will be described with reference to FIG.

First, the instruction data information 8 stored in the instruction register 1 is sent to the software area instruction exception information detection circuit 2 and the hardware area instruction exception information detection circuit 3, respectively.

The software area instruction exception information detecting circuit 2 derives the software area instruction exception information 1 from the instruction data information 8 and the various kinds of mode information 9 for detecting instruction exception information.
Generate 0. On the other hand, the hardware area instruction exception information detection circuit 3 which is a feature of the present invention generates hardware area instruction exception information 11 from the instruction data information 8.

Further, software area instruction exception information 1
0 and the hardware area instruction exception information 11 are input to the selector 5, and if the mode information 12 of the macro mode flip-flop 4 is "0" (normal mode: a mode for executing the instruction execution procedure of the software area 6), the software area instruction If the exception information 10 and the mode information 12 are “1” (macro mode: a mode for executing the execution procedure of the hardware area 7), the hardware area instruction exception information 11 is selected, and the instruction exception information 13 is generated. You.

Next, the manner of execution of the instruction execution procedure will be specifically described with reference to FIG.

For example, an instruction execution procedure stored in the software area 6, an SR (subtraction) instruction, and an AR (addition)
When an instruction or the like is executed, a compound instruction (in this embodiment, temporarily
When the (ST-X instruction) is detected, the mode is switched to a mode in which the execution procedure of the hardware area 7 is executed, that is, a macro mode, and an instruction execution procedure describing a predetermined process of the INST-X instruction is started.

When the last EMD (macro mode end) instruction of the hardware instruction execution procedure is executed, the mode is switched again to the mode for executing the instruction execution procedure of the software area 6, that is, the normal mode. Return to the instruction following the instruction and continue execution.

That is, in the above system, the compound instruction (INST-X) is executed by a plurality of instructions (STM instruction, BASR instruction, etc.) in the hardware area 7.

Here, the STM instruction is an instruction that can be executed regardless of the processing mode of this information processing apparatus (M, M / EA, M / EX mode in an M series processing apparatus manufactured by Hitachi, Ltd.).

However, conventionally, this information processing apparatus has been
In the case of the Hitachi M series processing apparatus M mode, since there is no BASR instruction, a program interrupt due to an instruction exception occurs. In other words, the execution procedure of the hardware area 7 including the BASR instruction is restricted by the mode of the information processing apparatus.
Special care such as the present invention is required.

Therefore, according to the information processing apparatus of this embodiment, the hardware area instruction exception information detecting circuit 3 for generating the hardware area instruction exception information 11 and the macro mode flip-flop 4 indicating normal mode or macro mode are provided. As a result, the instruction sequence is
If it is part of the instruction execution procedure, the software area instruction exception information 10 is detected as before, while if it is part of the instruction execution procedure of the hardware area 7, it is independent of the software area 6. The hardware area instruction exception information 11 can be detected.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, in the information processing apparatus of this embodiment, the case where a compound instruction is detected has been described.
The present invention is not limited to the above embodiment, and can be applied to the occurrence of a specific event. In this case, the instruction execution procedure in the corresponding hardware area 7 is executed in the same manner as the generation of the composite instruction. You.

[0029]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, a first logic circuit indicating that the instruction execution procedure in the hardware area is being executed, and a second logic circuit exclusively detecting the instruction exception information of the instruction executed in the hardware area. Is provided, it is possible to independently detect and control the instruction exception information of the instructions executed in the software area and the hardware area. Therefore, the instructions usable in creating the instruction execution procedure in the hardware area are extended. In addition, there is no need to be aware of the mode of the information processing apparatus in which the instruction execution procedure is executed.

As a result, it is possible to obtain an information processing apparatus capable of improving the productivity of the instruction execution procedure in the hardware area.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a main part of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating a divided state of a main memory in the information processing apparatus according to the present embodiment.

FIG. 3 is an explanatory diagram showing a state of execution of an instruction execution procedure in the embodiment.

[Explanation of symbols]

1 instruction register 2 software area instruction exception information detection circuit 3 hardware area instruction exception information detection circuit (second logic circuit) 4 macro mode flip-flop (first logic circuit) 5 selector 6 software area 7 hardware area 8 instruction Data information 9 Various mode information for detecting instruction exception information 10 Software area instruction exception information 11 Hardware area instruction exception information 12 Mode information 13 Instruction exception information

Continuing from the front page (72) Koji Nakamura, Inventor: 1 Horiyamashita, Hadano City, Kanagawa Prefecture, Kanagawa Plant, Hitachi, Ltd. (56) References JP-A-2-83739 (JP, A) JP-A-1-310441 (JP) , A) JP-A-63-120336 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/22-9/38

Claims (1)

(57) [Claims] 1. A main memory is divided into a software area and a hardware area, normal software is stored in the software area, and an instruction execution procedure for a specific instruction or a specific event of the software area is stored in the hardware area. An information processing apparatus that executes an instruction execution procedure in the hardware area corresponding to the issuance of the specific instruction or the occurrence of a specific event when the specific instruction is issued or a specific event occurs. A first logic circuit indicating the presence of the instruction, a second logic circuit exclusively detecting instruction exception information of an instruction executed in the hardware area, and an instruction exception information of an instruction executed in the software area. A third logic circuit that outputs the hardware area instruction exception information and the software area command based on an output of the first logic circuit. A selector for selecting one of the exception information is provided, and the instruction exception information is detected independently when the instruction sequence is executed in the hardware area and when the instruction string is executed in the software area. Information processing device.