JP3124131B2 - Tabular circuit description device and method, and functional language conversion device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tabular circuit description that operates on a personal computer and a functional language converter that converts the description into a language.

[0002]

2. Description of the Related Art Conventionally, various kinds of information to be controlled at a site, for example, physical information such as the number of products passing through an outlet of a belt conveyor reaching a predetermined quantity, or dangerous when a cutting machine is in operation. There is logical information such as detection of a moving object in the area. Programmable controllers (hereinafter, referred to as PCs) are widely used to perform predetermined output control (sequence control) according to the detected various information.

[0003] This method of programming a PC involves a completely different description format from ordinary computer programming. In general, for example, a-contacts (normally open switches) A, B,
A development connection diagram (ladder diagram) of a relay circuit using symbol marks such as D and b contacts (normally closed switches) E and coils C and F is used. Alternatively, for example, a condition table shown in FIG. 28 may be used.

FIGS. 27 and 28 show the same program contents except for the description format. That is, the relay circuit a-1 in FIG. 27 and the condition table column b in FIG.
-1 corresponds to it and represents an output C conditioned on input A and input B. Similarly, a relay circuit a-2 and a condition table column b-2 correspond to each other, and represent an output F conditioned on an input D and an input E.

FIG. 29 shows a relay circuit a-
1 or the operation of the program indicated by the column b-1 of the condition table is shown in a truth table. FIG. 30 shows the operation of the program indicated by the relay circuit a-2 or the column b-2 of the condition table. This is shown in a fake value table.

These descriptions are converted into program codes by a programming device (program loader) and
Is stored in The program code is not a machine language that can be directly executed in a PC, which is generally called a programming language, but is converted into an intermediate code that can be easily analyzed by the PC.

The basic structure of the above intermediate code is “(F op
1 op2... Opn) ”, and has a functional (action) language structure. In the above basic structure, "(" is the start of an instruction, "F" is the name of the instruction, ")"
Is the end of the instruction. Also, “op1”, “op”
"2",... "Opn" are instruction operands,
These operands can further become instructions and take a hierarchical structure as a whole. This functional language has a one-to-one correspondence with a machine language that operates directly on a PC, and can be easily converted to a machine language.

[0008] Normally, the on-site aspects such as the progress of the process and the work procedure are fluid. For this reason, the sequence (program) of the sequence control at the work site is not originally defined as a specification from the beginning, and is constantly changed or modified according to the actual situation of the site during the trial operation or actual operation of the PC. It is decided by being repeated. Therefore,
In order to easily cope with these changes, it is desirable that the above-mentioned ladder diagram and condition table can easily describe any complicated control contents corresponding to the changes.

[0009]

However, since a ladder diagram simulates logic by the flow of current, a considerable amount of electrical expertise is required when converting logic into a circuit. For example, the logic circuit shown in FIG. 31 can convert the logic flow into a current flow and convert it into a ladder diagram shown in FIG. 32. However, this conversion requires a high degree of skill, and a beginner can easily perform the conversion. There was a problem that it was not possible.

In addition, it requires considerable skill to recognize that the ladder diagram of FIG. 32 is equivalent to the logic circuit of FIG. 31, which also cannot be easily recognized by a beginner. There was a problem.

The condition table is described in, for example, FIG.
34 can be converted to the condition table shown in FIG. 34, but the logic circuit shown in FIG. 31 cannot be converted to the condition table because of the deep logic. A logic diagram having a time delay as shown in FIG. 35, that is, a circuit having a delay operation cannot be converted into a condition table. As described above, the condition table cannot describe all necessary logic circuits, and there is a problem that the use of the condition table is limited.

SUMMARY OF THE INVENTION An object of the present invention is to create any logic circuit including a delay operation (timer) which can be created without requiring specialized knowledge, is excellent in readability, and has an online readout of an actual circuit operation state. An object of the present invention is to provide a programming method (circuit description) that can be described in a table format and that can be monitored, and a language conversion device that converts the program into a functional language.

[0013]

The present invention is applied to a tabular circuit description for describing a circuit diagram for a programmable controller in a tabular form, and a functional language converter therefor.

A first aspect of the present invention is a tabular circuit description apparatus having a function of describing a circuit diagram for a programmable controller (hereinafter, referred to as a PC) in a tabular form. , An output description function for describing on a plurality of output description lines, and an input description function for describing on a plurality of input description lines corresponding to the output (2)
The output description function (1) includes output name input means (a) for describing the name of an output signal, timer input means (b) for describing a timer set value, and output for describing an output condition. A condition input means (c) and a comment input means (d) for describing a comment are provided. The input description function (2) includes an input name input means (e) for describing a name of an input signal, An input symbol meaning an input, an input inversion symbol meaning an inverted input of a signal, a logical sum symbol meaning a logical sum of input signals, and a logical product symbol meaning a logical product of input signals, And an input logic input means (f) for inputting any of the symbols consisting of: an input signal of the input name input means (e) or an operation result of a logical operation inputted by the input logic input means (f). A positive logic sign that means Fill force name input means (e)
An input condition input means (g) for inputting an input condition consisting of an input signal of (i) or a negative logic symbol meaning that the operation result of the logical operation input by the input logic input means (f) is inverted and used. And comment input means (h) for inputting a comment. The output condition input means (c)
A light symbol indicating that a logical product of a positive logic symbol or a negative logic symbol input from the input condition input means (g) is substituted for an output signal; and a positive logic signal input from the input condition input means (g). A set signal indicating that the output signal is turned on when the logical product of the symbol or the negative logical symbol is true and not processed when the logical product is false, and a positive logical symbol or negative logical input from the input condition input means (g). A reset signal that turns off the output signal when the logical product of the symbols is true and that means no processing when the symbol is false is input.

A functional language conversion apparatus according to a second aspect of the present invention is a functional language conversion apparatus for converting a circuit description language in a table format in which a circuit diagram for a PC is described in a table format into a functional language. Circuit storage means (3) for storing a table-form circuit description language; and language storage means (for storing a functional language converted from the table-form circuit description language stored in the circuit storage means (3)). 4) extracting output conditions from an output condition description column (c) of a plurality of output description lines (1) of a tabular circuit description language stored in the circuit storage means (3);
Input / output condition extraction storage means (5) for extracting input conditions from input condition description fields (g) of a plurality of input description lines (2) and storing the input conditions, respectively; An input / output instruction creating means (6) for reading the condition and output condition, converting the read input condition and output condition into a functional language input condition and output condition, respectively, and storing them in a predetermined area of the language storage means (4); ), And extract the output name from the output name description field (a) of the tabular circuit description language stored in the circuit storage means (3), and extract the timer set value from the timer description field (b). Output information extraction storage means (7) for storing as output information; and a timer instruction and a timer value name of a functional language based on the output name and the timer set value read from the output information extraction storage means (7). Strange A timer instruction creating means (8) for storing the information in a predetermined area of the language storage means (4) and a logic description field (f) of a tabular circuit description language stored in the circuit storage means (3). Input logic extraction storage means (9) for extracting logic, converting it into a functional language, and storing the input logic and input / output condition extraction storage means (5) read from the input logic extraction storage means (9) A & instruction of a functional language is created based on the read input condition and output condition, and the & instruction is stored in a predetermined area of the language storage means (4), and that the & instruction has been created is stored. The instruction setting means (10) and the timer setting value are read from the output information extraction storage means (7), and the timer setting value is stored in a predetermined position of the language storage means (4).
A timer setting value generating means (11) for storing an instruction end code corresponding to the & instruction which stores the information generated by the & instruction generating means (10) and an output from the output information extracting and storing means (7) Output command creating means (12) for reading the name and storing the output name in a predetermined position of the language storage means (4).

A third aspect of the present invention is a tabular circuit description method for describing a circuit diagram for a programmable controller (hereinafter referred to as a PC) in a tabular form. An output description step (1) described on an output description line and an input description step (2) for describing on a plurality of input description lines corresponding to the output are provided. Output name input step (a) that describes the name of the output, a timer input step (b) that describes the timer setting value, an output condition input step (c) that describes the output condition, and a comment input step ( d), the input description step (2) includes an input name input step (e) for describing a name of an input signal, an input symbol indicating input of a signal, and inversion of the signal. An input logic for inputting any of the following symbols: an input inversion symbol meaning force, a logical sum symbol meaning the logical sum of input signals, and a logical product symbol meaning logical product of input signals. Input step (f)
And a positive logical symbol meaning that the input signal input in the input name input step (e) or the operation result of the logical operation input in the input logical input step (f) is used, and the input name input An input condition input for inputting an input condition consisting of an input signal of the means (e) or a negative logic symbol indicating that the operation result of the logical operation input by the input logic input means (f) is inverted and used; The output condition input step (c) comprises a step (g) and a comment input step (h) for inputting a comment.
Is a light symbol indicating that a logical product of the positive logic symbol or the negative logic symbol input in the input condition input step (g) is substituted for the output signal, and the light symbol input in the input condition input means (g). A set signal meaning that the output signal is turned on when the logical product of the positive logical symbol or the negative logical symbol is true and not processed when the logical product is false, and a positive logical symbol or a logical signal input by the input condition input means (g). A reset signal that turns off the output signal when the logical product of the negative logical symbols is true and turns off the output signal when the logical product is false is input.

A functional language conversion method according to a fourth aspect of the present invention is a functional language conversion method for converting a tabular circuit description language in which a circuit diagram for a PC is described in a table format into a functional language. Circuit storage procedure (3) for storing the table-form circuit description language, and a language storage procedure (4) for storing the functional language converted from the table-form circuit description language stored in the circuit storage procedure (3). ), And extracting the output condition from the output condition description column (c) of the plurality of output description lines (1) of the tabular circuit description language stored in the circuit storage procedure (3),
An input / output condition extraction / storage procedure (5) for extracting and storing input conditions from the input condition description field (g) of the plurality of input description lines (2), and the input / output condition extraction / storage procedure (5) An input / output instruction for reading the input condition and the output condition, converting the read input condition and the output condition into the input condition and the output condition of the functional language, and storing the input condition and the output condition in a predetermined area of the language storage procedure (4). Creation procedure (6)
And the output name is extracted from the output name description field (a) of the tabular circuit description language stored in the circuit storage procedure (3), and the timer setting value is extracted from the timer description field (b) and output. An output information extraction and storage procedure (7) for storing as information, the output name and the timer setting value stored in the output information extraction and storage procedure (7) are read, and the read output name and the timer setting are read out. A timer instruction creation procedure (8) that converts the value into a timer instruction of a functional language and a timer value name based on the value and stores it in a predetermined area that is stored in the language storage procedure, and is stored in the circuit storage procedure (3). An input logic extraction and storage procedure (9) for extracting input logic from a logic description field (f) of a tabular circuit description language, converting it into a functional language, and storing the input logic, and storing the input logic in the input logic extraction and storage procedure (9) Being on A & instruction of a functional language is created based on the input logic and the input and output conditions stored in the input / output condition extraction and storage procedure (5), and the & instruction is specified in the language storage procedure (4). The & instruction creation procedure (10) for storing the & instruction creation in the area and reading the timer setting value stored in the output information extraction and storage procedure (7) and reading the timer setting value in the language A timer setting value creation procedure (11) that stores the instruction completion code corresponding to the & instruction stored in the & instruction creation procedure (10), which is stored in a predetermined position stored in the storage procedure (4). ), And an output command creation procedure for reading out the output name stored in the output information extraction storage procedure (7) and storing the output name in a predetermined position stored in the language storage procedure (4) ( And 2),
Is configured.

The tabular circuit description language is, for example, a tabular circuit description language for describing a circuit diagram for a programmable controller in a tabular form. The output description line (1) includes a plurality of output description lines (1) and a plurality of input description lines (2) for describing an input corresponding to the output. Name description field (a) and timer description field (b) that describes the timer set value
And an output condition description field (c) for describing an output condition, and a comment description field (d) for describing a comment. The input description line (2) includes an input name description field for describing a name of an input signal. (E), an input logic description field (f) describing input logic, and an input condition description field (g) describing input conditions.
And a comment description field (h) for describing a comment, and an input symbol representing an input of a signal and an input inversion representing an inverted input of a signal for describing in the input logic description field (f). A symbol, a logical sum symbol indicating a logical sum of the input signals, and a logical product symbol indicating the logical product of the input signals, and are described in the input condition description field (g). A positive logical symbol indicating that the input signal of the input name description field (e) or the operation result of the input logic description field (f) is used, and the input signal or the input logic of the input name description field (e). A negative logical symbol meaning that the operation result in the description field (f) is used in an inverted manner; and a positive logic in the input condition description field (g) for describing in the output condition description field (c). Means to substitute the logical product of logical or negative logical symbols into the output signal. And a set symbol meaning that the output signal is turned on when the logical product of the positive logical symbol or the negative logical symbol in the input condition description field (g) is true and not processed when the logical product is false. The output signal is turned off when the logical product of the positive logical symbol or the negative logical symbol in the condition description column (g) is true, and the reset symbol means no processing when the logical product is false.

Further, in the above-mentioned tabular circuit description language, for example, an input symbol representing an input of the signal described in the input logic description field (f) is represented by an arrow. An input inversion symbol indicating inversion input is represented by an arrow with a black circle added at the center, the above-mentioned OR symbol representing OR is represented by a single vertical line, and the AND symbol representing AND is parallelized The light symbol described in the output condition description column (c) is represented by “W”, the set symbol is represented by “S”, the reset symbol is represented by “R”, and the reset symbol is represented by “R”. The positive logical symbol described in the input condition description column (g) is represented by “○”, and the negative logical symbol is represented by “×”.

[0020]

[0021] This eliminates the need for specialized knowledge,
Any logic circuit including a delay operation (timer) with excellent readability can be described. Further, the tabular circuit description described in this manner is easily converted into a functional language by each means of the functional language converter according to claim 3 and stored.

Thus, the PC can be operated by converting it into a machine language, and online monitoring of the actual circuit operation state can be performed.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 4 shows the logic circuit diagram of FIG . 31 described above in the form of a circuit table according to the present invention, and FIG .
5 is also described in the form of a circuit table.

4 and 5, the upper three output description lines 31
And a circuit table format consisting of the input description lines 32 at the bottom six lines. The output description line 31 includes an output name description field 33,
It consists of a timer description field 34 and an output condition description field 35,
The input description line 32 includes an input name description field 36, an input logic description field 37, and an input condition description field 38.

In the input name description column 36 in FIG. 4, the names A to F of the input signals in FIG. 31 are described as they are. In the input logic description field 37, the inverted inputs of the signals B, D and E are indicated by arrows with black circles, the inputs of the signals A, C and F are indicated by arrows or no marks, the OR circuit is a single vertical line, and the AND circuit is indicated. Is described by two vertical lines. The input condition description field 38
, The input to the last AND circuit is described by the symbol ○.

The output name description column 33 describes the name G of the output signal, and the corresponding timer description column 34
, The symbol “W” is described in the output condition description field 35.

In FIG. 5, the logic circuit diagram of FIG . 35 is described in the input name description field 36, the input logic description field 37, and the input condition description field 38 in the same manner as described above. And
In this case, the timer value “1” of the timer circuit is described in the timer description field 34.

As described above, according to the present embodiment, the conversion to the condition table of the logic circuit shown in FIG . Further, although not specifically shown, FIG. 6 shows an example in which a circuit having a deeper (complex) logic than the logic circuit shown in FIG. 31 or FIG. 35 is described in a table format. In the tabular description shown in FIG. 11, an output name description field 43, a timer description field 44, and an output condition description field 45 are provided at the top.
Are provided, and an input description line 42 (seven lines) including an input name description field 46, an input logic description field 47, and an input condition description field 48 are provided below. Each of the output description lines 41 and the input description lines 42 has no restriction on the number of lines, and increases according to the logic depth.

In the input name description field 46, the names of the input signals are "I.RD-EMS" and "I.RD-RU".
N "," IF-ELS "," I. RST-COS ",
"IF-LS", "T.SSTIM" and "IFFR"
D-ST ".

In the input logic description column 47, input signals "I.RD-RUN" and "IF-EL"
The input of "S" is described by arrows 47-0 and 47-1, and the OR circuit to which these inputs 47-0 and 47-1 are added is described by one vertical line 47-2.
The calculation result of -2 is described by an arrow 47-3, and it is described that the calculation result 47-3 is input to the final AND circuit (no symbol, substituted by a partition line in the column).

Below the input signal "IF-
LS "and" T.SSTIM "are input with arrows 4 respectively.
7-4 and 47-5, the AND circuit to which the inputs 47-4 and 47-5 are added is described by two vertical lines 47-6, and the operation result of the AND circuit 47-6 is indicated by an arrow 4
7-7, and the OR circuit to which the operation result 47-7 is added is described by one vertical line 47-8.
The input of the input signal "I. FRD-ST" applied to the OR circuit 47-8 together with 7-7 is described by an arrow 47-9. Further, the operation result of the above OR circuit 47-8 is described by an arrow 47-10, and it is described that the result is inputted to the AND circuit at the last stage (partition line of the column).

The first column 48 of the input condition description field 48
−1, the input signal “I.RD-EMS” in the first row
Is described by a circle, and the OR circuit 47−
The input symbol of the operation result 47-3 of 2 is described with a circle, and 5
In the row, the input symbol of the operation result 47-10 of the OR circuit 47-8 is described with a cross.

The symbol 記号 in the above input symbol indicates that the input signal of the corresponding row is used or the result of the logical operation is used, and the symbol x indicates that the input signal or the result of the logical operation of the corresponding row is used. It indicates that it is used inverted.

On the other hand, in the output name description column 43 of FIG. 3, output signal names "T.SSTIM" , "M.RD-F",
“M.RD-R” is described, and the signal “T.SSTI ” is written.
The address “DIABCDE” where the timer value is stored is described in the timer description field 44 corresponding to “M” , and the output condition “W” is described in the output condition description field 45.

The output condition “W” indicates that the result of the logical operation is substituted for the output signal “T.SSTIM” . The logical operation result corresponding to the input signal “I.RD-” is obtained by describing two input marks “○” and one “X” as input conditions in the first column 48-1 of the input condition description field 48. EMS "and the operation result 47-3 of the OR circuit 47-2, and the operation result 47-1 of the OR circuit 47-8
It is shown that it is derived by the logical product of three inputs with the inverted signal of 0.

The output signal "M.
No timer value is described in the timer description column 44 corresponding to "RD-F", and the output condition "S" is described in the output condition description column 45.

The output condition "S" indicates that the output signal "M.RD-F" is turned on when the logical operation result is true, and that no processing is performed when the logical operation result is false. .
The operation result of the logic corresponding to this is input symbol description field 48.
Are described in the third column 48-3, which is the input condition, so that the operation result 47-3 of the OR circuit 47-2 is obtained.
And the operation result 47-10 of the OR circuit 47-8
It is shown that it is derived by AND of two inputs.

In the output signal "M.RD-R" in the output name description field 43, the timer value is not described in the corresponding timer description field 44, and the output condition "R" is described in the output condition description field 45. Have been.

The output condition "R" indicates that the output signal "M.RD-R" is turned off when the logical operation result is true and no processing is performed when the logical operation result is false. The logical operation result corresponding to the input signal “I.RD-EMS” and the OR circuit are described by describing three X symbols as input symbols in the second column 48-2 of the input symbol description field 48. 47-2 and the input signal "IR.
It is shown that "ST-COS" is derived by the logical product of three inputs that are inverted and input.

In this embodiment, such a table-like circuit description (condition table description) is performed, and this is used as a circuit program, that is, a source program. The above-described circuit program of FIG. 6 is equivalent to the functional language shown in FIG. This functional language is an intermediate code that connects a source program and an object program, and can be easily converted into a machine language.

The first, eighth, and ninth lines of the functional language shown in FIG.
The instructions “W”, “R” and “S” in the line are synonymous with the above-described output condition symbols “W”, “R” and “S” in FIG. Also, the instruction “TON” on the first line
Is a timer instruction instructing output to be performed after a predetermined time (second).

The instruction “&” in the second line is the same as the first operand in the second line, the second operand in the third line,
This is an operation instruction for obtaining a logical product with the third operand on the line. Similarly, the instruction “&” in the other rows is an operation instruction for obtaining the logical product of the first to third operands or the first and second operands.

The instruction “> = 1” in the third, fourth, eighth, and ninth lines is, in this case, a logical sum of the first operand and the second operand. Is an operation instruction for The instruction “NOT” on the fourth and eighth lines is an instruction for inverting the output. Further, the input signal “I.
The symbol "!" Added immediately before " RD-EMS", "I. RST-COS", etc. indicates that those signals are inverted.

Next, FIG. 8 shows a block diagram of a functional language conversion apparatus for converting the above-mentioned source program, that is, the table-form circuit description (see FIGS. 4 to 6) into a functional language. In the figure, a functional language converter 50 is a source storage device 51 for storing a table type circuit description, and a functional type language converted from the table type circuit description stored in the source storage device 51 (see FIG. 7). Is provided with a functional language storage device 52 for storing.

Then, the functional language conversion device 50 includes an input / output condition extraction device 53 for extracting input / output conditions from the tabular circuit description stored in the source storage device 51. It has a data area consisting of 5 columns, and the input / output condition extraction device 53
And an input / output condition storage device 54 for storing the input / output conditions extracted in accordance with the above. Has a W, R, S instruction creating device 55 for storing the instruction.

Further, the functional language converter 50 includes an output line extraction device 56 for extracting output line information from the tabular circuit description of the source storage device 51. One line shown in FIG. An output line information storage device 57 which has a data region for six lines of values and stores the output name and timer set value of the output line information extracted by the output line extraction device 56 in the data region; The timer setting value is read from the data area of the output row information storage device 57,
It has a timer instruction creation device 58 that stores a timer instruction based on the timer set value and a timer value name at a predetermined position in the functional language storage device 52.

Further, the functional language conversion device 50 includes:
An input logic extraction device 59 for extracting input logic from the table-form circuit description of the source storage device 51. The input logic extraction device 59 has an 8-row data area shown in FIG. Based on the input logic storage device 60 that converts logic into a functional language and stores it, and the input / output conditions stored in the input / output condition storage device 57 and the input logic stored in the input logic storage device 60, An & instruction is created by adding an inversion of the input, the & instruction is stored at a predetermined position in the functional language storage device 52, and an & instruction creating device 61 is stored to store the fact that the & instruction was created. .

Finally, the functional language converter 50 includes:
The timer setting value name is read from the output line information stored in the output line information storage device 57, and the timer setting value is stored in a predetermined position of the functional language storage device 52.
& The output signal name is read from the timer setting value creation device 62 for storing the instruction end code corresponding to the instruction and the output line information similarly stored in the output line information storage device 57, and the output signal name is stored in a functional language. An output command creation device 63 to be stored in the device 52 is provided.

FIG. 9 is a storage state diagram of input / output conditions extracted from the above-described circuit description in the form of a table and stored in the data area of the input / output condition extraction device 53. In the figure, the input / output conditions are stored in a state of 11 rows and 5 columns. The minimum required number of rows in this data area is the number of input signals plus two rows. In the example of FIG. 6, the input / output conditions of the tabular circuit description shown in FIG. 6 are stored, and the number of input signals is seven. Therefore, the 10th and 11th lines are unused. The minimum required number of columns in this data area is the number of output signals, and since the number of output signals in the tabular circuit description shown in FIG.
The column is unused.

In the use part of the data area, the output conditions "W", "R", and "S"
Are respectively stored. And 1 to 3 in the second row
The column stores the row numbers of the tabular circuit description in which the output conditions “W”, “R”, and “S” are described.

The first to third columns of the third to ninth rows of the data area are described in the first to third rows of the first to seventh rows of the input condition description column 48 of the tabular circuit description shown in FIG. The input condition symbols “○” and “×” are stored at the same positions. In the input condition description field 48 of the tabular circuit description shown in FIG. 6, in the first to third rows of the first to seventh rows, "absence" is indicated at a position where the input condition symbol "o" or "x" is not described. Is stored.

Lines 10 and 11 above, and 4 and 5
The unused part in the column stores "absence" of the used part, which is not particularly shown. Next, FIG. 10 is a storage state diagram of the output line information stored in the data area of the output line information storage device 57.

In the example of FIG. 6, the output signal name “T.SSTIM” and the timer setting value “DIABCD” described in the first line of the output description line 41 of the table-type circuit description shown in FIG.
E ”is stored in the upper and lower rows of the data area, and the output signal name“ M.RD-F ”and the timer setting value described in the second row of the output description row 41 of the tabular circuit description shown in FIG. “None” is stored in the next two lines above and below the data area, and the output signal name “M.RD-R” and the timer setting value “None” described in the third line of the output description line 41 are also stored. , Are stored in the next two lines above and below the data area.

FIG. 11 shows the input logical storage device 60.
FIG. 9 is a storage state diagram of input logic extracted from a table-form circuit description and converted into a functional language, stored in a data area of FIG. In the example shown in the figure, the data area consists of eight lines, and the input signal name “I.RD” for which no logical operation is described in the input logic description column 47 of the input description line 42 of the tabular circuit description shown in FIG. -EMS "and" I. RST-COS "
The input signal names stored in the same data area row as described in the tabular circuit description, and the description of the logical operation is made in the input logical description field 47, are stored in the row corresponding to the input signal of the top row added to the logical operation. Are stored as parameters in the functional language to which the described logic is converted.

Next, the processing operation of the embodiment having the above configuration will be described with reference to the flowcharts of FIGS. In this processing, the functional language conversion device 5 shown in FIG.
Under the control of a CPU (Central Processing Unit) (not shown), the devices 51 to 63 constituting the functional language conversion device 50 convert the stored table-form circuit description into a functional language. Is made. 9 and FIG.
All the data areas of the input / output condition storage device 54, the output line information storage device 57, and the input logical storage device 60 shown in FIG. 11 are all cleared.

FIG. 12 is a main flowchart showing the overall processing. 13 to 20 to be described later.
Will be described in detail. First, in the overall processing shown in FIG. 12, in step S121, input / output condition extraction processing in the input / output condition extraction device 53 is performed, and then, in step S122.
Then, output line information extraction processing in the output line extraction device 56 is performed, and further, in step S123, input logic extraction processing in the input logic extraction device 59 is performed.

In steps S124 to S128, conversion to a functional language is performed based on the input / output conditions, output line information, and input logic extracted in each of the above three steps S121 to S123.

That is, in step S124, W,
In the S, R instruction creating device 55, processing of creating W, S, R instructions is performed. Next, in step S125, the timer instruction creation device 58 performs a timer instruction creation process. Subsequently, in step S126, the & instruction creation device 61 performs an & instruction creation process. Subsequently, in step S127, the timer setting value creation device 62
In, a process of creating a timer set value is performed.
In step S128, the output instruction creating device 63 performs an output instruction creating process.

[0059] Then, the following columns (table format circuit description that is converted to a functional language is output lines 45 in the example of FIG. 6 45-
1, 45-2 , 45-3 ), and it is determined whether or not there is an instruction (output condition) “W”, “S” or “R”. And if there is any instruction (output condition),
Returning to step S124, steps S124 to S129
Is repeated.

As a result, the source storage device 51 shown in FIG.
Is converted into the functional language shown in FIG. 7 and the functional language storage device 5 shown in FIG.
2 is stored.

Next, the above steps S121 to S128
The details of the process will be described. FIG. 13 is a flowchart of the input / output condition extraction processing. In the figure,
First, the input / output condition extraction device 53 searches the output condition description field 45 of FIG. 6 in units of columns, extracts W, R, and S symbols and their existing line numbers (step S131), and extracts the extracted result. Is stored in a predetermined data area of the input / output condition storage device 54 (step S132) .

Next, the input condition description field 48 of FIG. 6 is searched in units of columns to extract "O" and "X" symbols and the line numbers where they exist (step S133). Is stored in a predetermined data area of the input / output condition storage device 54 (step S134).

Thus, for example, the storage state of the data area of the input / output condition storage device 54 shown in FIG. 9 is realized. Next, FIG. 14 is a flowchart of an output line information extraction process.

In the figure, the output line extracting device 56 searches the output name description column 43 and the timer description column 44 of FIG. 6 on a line-by-line basis, and extracts an output name and a timer set value (step S141). The output name and the timer set value thus obtained are stored in the output line information storage device 57 (step S1).
42).

Thus, for example, the storage state of the data area of the output row information storage device 57 shown in FIG. 10 is realized.
Next, FIG. 15 is a flowchart of the input logic extraction processing.

In the figure, an input logic extraction device 59
First, the input logical description column 47 of FIG. 6 is searched for each line (step S151), and it is determined whether or not the last end of the logical symbol exists in the searched line (step S152). And
If the last end exists, the logic is traced from the last end, and the logic is converted into a functional language (step S15).
3) The converted functional language is input to the input logical storage device 60.
(Step S154).

On the other hand, if it is determined in step S152 that no logical symbol exists in the search line, the input name description field 46
Is extracted (step S15).
6), the extracted input signal name is stored in the input logical storage device 6
0 in a predetermined data area (step S15).
7).

Thus, for example, the storage state of the data area of the input logical storage device 60 shown in FIG. 11 is realized. Next, FIG. 16 is a flowchart of the W, S, R instruction creation processing.

In the figure, a W, S, R instruction creation device 5
5 extracts the types of the W, S, and R instructions ("W" in the example of FIG. 9) from the first column of the storage state shown in FIG. 9 in the data area of the input / output condition storage device 54 (step S161). ), And stores the extracted instruction “W” in a predetermined data area of the functional language storage device 52 (step S162).

As a result, the state of language storage in the functional language storage device 52 shown in FIG. 21A is realized. Next, FIG. 17 is a flowchart of the timer instruction creation processing.

In the figure, a timer instruction creating device 58
Extracts an output row number ("1" in the example of FIG. 9) corresponding to the first column of the storage state shown in FIG. 9 in the data area of the input / output condition storage device 54 (step S171). It is determined whether there is a timer setting value corresponding to the extracted output row number (in this case, the first column) in the data area of the output row information storage device 57 in the storage state shown in FIG. 10 (step S172). In this determination, if there is a timer setting value, the timer setting value (“DIABCDE” in the example of FIG. 3) and the output signal name of the row (“T.SSTI” in the example of FIG. 4).
M ”) (step S173), and based on the output signal name“ T.SSTIM ”, a timer current value name“ TRSSTIM ”is created (step S174).
In this process, in this embodiment, the output signal name and the timer current value name have a one-to-one correspondence as shown in FIG. 25, and the timer current value name is created based on this algorithm.

Subsequently, the timer current value name “TRSSTIM” and the timer instruction “TON” created above are stored in a predetermined data area of the functional language storage device 52 (the next address of the previously stored instruction) (step). S175).

As a result, the state of language storage in the functional language storage device 52 shown in FIG. 21B is realized. If the timer set value does not exist in step S172, the process ends immediately without performing the processes of steps S173 to S175.

Next, FIG. 18 is a flowchart of & instruction creation processing. In the figure, & instruction creation device 61
Searches the data area of the input / output condition storage device 54 (step S181), and for each column of the storage state shown in FIG.
It is determined whether there are a plurality of "o" or "x" (step S182).

If there is a plurality of "&" instructions, the && instruction is stored in a predetermined data area of the functional language storage device 52 (step S183), and the fact that the && instruction is stored is stored. (Step S184), and the process proceeds to the next Step S185.

As a result, the state of language storage in the functional language storage device 52 shown in FIG. On the other hand, in step S182, if there is only one “「 ”or“ × ”in the searched column, steps S183 and S1
The process directly proceeds to step S185 without performing the process of S84.

In step S185, the data area of the input / output condition storage device 54 is searched (step S185).
A row number having “○” or “×” in the column of the storage state shown in FIG. 9 is extracted, and an input name (operand) corresponding to the extracted row number is stored in the input logical storage device 60 shown in FIG. It is extracted from the state, and the extracted input name (operand) is stored in a predetermined data area of the functional language storage device 52 (step S186).

Next, it is determined whether or not the input condition extracted from the column is "x" indicating signal inversion (step S187). If "x", then the stored input name (operand ) Is an atom (step S188). In this embodiment, when the operand is the input signal name (see the first and fourth lines in FIG. 11),
This is called an atom, while the operand is a function (FIG. 11).
Is referred to as a list).

If it is determined that the stored operand is an atom, "!" Indicating inversion is added to the head of the operand (step S189), and the processing is terminated. On the other hand, if the stored operand is a list in the above determination, subsequently, it is determined whether or not the function name of the list (operand) is "NOT" of the inversion instruction (step S1).
90).

In this determination, if the function name is "NOT", the "NOT" function is removed to further invert the inversion command "NOT" (step S19).
1), end the process.

[0081] On the other hand, in the above determination, if the function name is not "NOT", Ru inverts the value that list enclosed in "(NOT)" as the "NOT" function (Step S1
92). In addition, in the &
If the creation of the order is memorized, the end of the & instruction "(&"
Is stored subsequently (step S19).
3). If the & instruction has not been created,
The process ends immediately without performing step S193.

As a result, the state of language storage in the functional language storage device 52 shown in FIG. continue,
FIG. 19 is a time chart of the timer setting value creation process.

In the figure, a timer set value creation device 62
Retrieves the storage state shown in FIG. 10 in the output line information storage device 57, and determines whether or not the timer set value name exists in the line being processed (step S195). Then, if the timer set value name exists, the timer set value (“DIABCDE” in the example of the figure) is stored in a predetermined data area of the functional language storage device 52 (step S19).
6).

If the timer set value name does not exist in step S195, the process ends immediately.
Thereby, when the above step S196 is performed,
The language storage state of the functional language storage device 52 shown in FIG. 23 is realized.

FIG. 20 is a flowchart of the output instruction creation process. Referring to FIG.
Extracts the output signal name (“T.SSTIM” in this example) of the row being processed from the output row information storage device 57,
The output signal name is stored in a predetermined data area of the functional language storage device 52 (step S201), and the process ends.

Thus, the state of language storage in the functional language storage device 52 shown in FIG. 24 is realized. In this way, steps S124 to S12 of the overall process shown in FIG.
8, the correspondence between the input and output in the first column in the storage state of the input / output condition storage device 54 shown in FIG.
Subsequently, steps S124 to S128 are repeated, and 2
The column and the third column are also converted, and the functional language shown in FIG. 7 converted from the tabular circuit description in FIG. 6 is stored in the functional language storage device 52.

Finally, FIG. 26 shows an example of an online monitor which displays a condition table (circuit description in table format) described according to this embodiment. In the figure, in the input signal name (or output signal name) description field and the input condition (or output condition) description field, a hatched portion or a portion indicated by “●” indicates that the signal is ON. . Thus, when the output signal is not ON, the missing condition can be found instantaneously by searching the corresponding column.

[0088]

As described above, according to the present invention, a logic circuit can be easily described by using a unique symbol in a table format. Circuits and circuits including delay operations (timers) can be described, and since they are in table format, they are extremely readable and easy to describe as compared to ladder diagrams, so even beginners can easily write complex logic circuits. Can be created.

[0089] Further, by performing online monitoring using tabular description, since the defects of the program by the condition missing it can very easily found, it is possible to debug complex logic circuits for beginners.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a table format for describing a circuit according to the present invention.

FIG. 2 is a diagram illustrating symbols used for describing a circuit in a table format according to the present invention.

FIG. 3 is a block diagram of the present invention.

FIG. 4 is a diagram showing an example in which a logic circuit that cannot be described conventionally in a condition table is described in a table format of the present invention.

FIG. 5 is a diagram showing an example in which a logic circuit that cannot be described conventionally in a condition table is described in a table format of the present invention.

FIG. 6 is a diagram for explaining an example of a table format of the present invention in which a deep logic circuit is described.

FIG. 7 is a diagram illustrating a functional language.

FIG. 8 is a block diagram of a functional language converter according to one embodiment.

FIG. 9 is a data area state diagram of the input / output condition storage device.

FIG. 10 is a data area state diagram of the output row information storage device.

FIG. 11 is a data area state diagram of the input logical storage device.

FIG. 12 is a flowchart of an overall process.

FIG. 13 is a flowchart of an input / output condition extraction process.

FIG. 14 is a flowchart of an output line information extraction process.

FIG. 15 is a flowchart of an input logic extraction process.

FIG. 16 is a flowchart of a W, S, R instruction creation process.

FIG. 17 is a flowchart of a timer instruction creation process.

FIG. 18 is a flowchart of & instruction creation processing.

FIG. 19 is a flowchart of a timer setting value creation process.

FIG. 20 is a flowchart of an output instruction creation process.

FIGS. 21A and 21B are diagrams illustrating a functional language stored in a data area of a functional language storage device.

FIGS. 22A and 22B are diagrams illustrating a functional language stored in a data area of a functional language storage device.

FIG. 23 is a diagram illustrating a functional language stored in a data area of the functional language storage device.

FIG. 24 is a diagram illustrating a functional language stored in a data area of the functional language storage device.

FIG. 25 is a diagram illustrating the relationship between an output signal name and its current timer value.

FIG. 26 is a diagram illustrating a display example during online monitoring.

FIG. 27 is a diagram illustrating an example of a ladder circuit diagram.

FIG. 28 is a diagram showing an example of a conventional condition table.

FIG. 29 is a diagram (No. 1) of a truth value table.

FIG. 30 is a diagram (No. 2) of a truth table.

FIG. 31 illustrates an example of a logic circuit.

FIG. 32 is a diagram showing an example of a ladder diagram.

FIG. 33 is a diagram illustrating an example of a logic circuit.

FIG. 34 is a diagram showing a condition table.

FIG. 35 is a diagram illustrating an example of a logic circuit.

[Explanation of symbols]

 1 output description line 2 input description line 3 circuit storage means 4 language storage means 5 input / output condition extraction storage means 6 input / output instruction creation means 7 output information extraction storage means 8 timer instruction creation means 9 input logic extraction storage means 10 & instruction creation Means 11 Timer setting value creating means 12 Output instruction creating means a Output name description field b Timer description field c Output condition description field e Input name description field f Input logic description field g Input condition description field

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadashi Abe 1 Fujimachi, Hino-shi, Tokyo Fujifacom Control Co., Ltd. (72) Inventor Yoshiharu Maruyama 1 Fujimachi, Hino-shi, Tokyo Fujifacom Control Ltd. (56) References JP-A-62-295109 (JP, A) JP-A-3-113505 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05B 19/04-19 / 05

Claims (6)

(57) [Claims] 1. A programmable controller (hereinafter referred to as P
Have the functions described a circuit diagram for the referred to as C) in a tabular form
A tabular circuit description apparatus, output descriptor function for describing the plurality of output lines described (1)
Described in a plurality of input description lines corresponding to the output.
The output description function (1) includes an output name input means (a) for describing the name of an output signal, and a timer input means (b) for describing a timer set value. Output condition input means (c) for describing an output condition , and comment input means (d) for describing a comment. The input description function (2) includes an input name input for describing a name of an input signal. Means (e), an input symbol meaning signal input, and an inverted signal input.
Means the inverted input symbol and the logical sum of the input signal
And the logical product of the input signal
An input to input either a logical AND symbol or a symbol consisting of
A logic input means (f) and an input signal of the input name input means (e) or the input signal
The operation result of the logical operation input by the logical input means (f) is
Use a positive logic symbol that means to use
Input signal of input means (e) or said input logic input means
Invert and use the operation result of the logical operation input in (f)
Input condition consisting of a negative logic symbol
An input condition input means (g) for inputting and a comment input means (h) for inputting a comment are provided, and the output condition input means (c) includes a positive logical symbol input from the input condition input means (g).
Or assigning the logical product of negative logic symbols to the output signal.
Meaning light symbol and the input condition input means (g)
The logical product of the positive and negative logical symbols input from
Turn on the output signal when
Meaning set signal and the input condition input means (g)
The logical product of the positive and negative logical symbols input from
The output signal is turned off when
And a set signal, or become signal sac Chiizure from is input
That, tabular circuit description and wherein the. 2. A circuit diagram for a PC is described in a table format.
A functional language conversion apparatus for converting a tabular circuit description language functional language, the table being stored with the circuit storage unit that stores a table format circuit description language (3), to the circuit storage unit (3) Formal circuit description
A language storage unit (4) for storing a functional language converted from a language; and a tabular circuit description stored in the circuit storage unit (3).
An output condition is extracted from the output condition description field (c) of a plurality of output description lines (1) of the predicate language , and a plurality of input description lines (2) are extracted.
Input / output condition extraction storage means (5) for extracting input conditions from the input condition description field (g) and storing the input conditions, respectively; and reading the input conditions and output conditions from the input / output condition extraction storage means (5). An input / output instruction creating unit (6) for converting the read input condition and output condition into a functional language input condition and output condition, respectively, and storing them in a predetermined area of the language storage unit (4); Table format circuit description stored in 3)
Output information extraction storage means (7) for extracting an output name from an output name description field (a) of a predicate language , extracting a timer set value from a timer description field (b), and storing each as output information;
When a predetermined region of the converting the said output name read from the output information extracting storage means (7) in accordance with the timer setting value to the timer instruction and the timer value name of functional languages verbal memory means (4) Timer instruction creation means to be stored in the memory (8)
And a tabular circuit description stored in the circuit storage means (3).
Input logic extraction storage means (9) for extracting input logic from a logic description field (f) of a predicate language , converting the input logic into a functional language, and storing it
Based on the input logic read from the input logic extraction storage means (9) and the input conditions and output conditions read from the input / output condition extraction storage means (5),
Create an instruction, the & stores instructions in a predetermined area of the language storage unit (4), and stores the instruction to create a & instruction creating means (10), before Kide force information extracting storage means (7) from the read timer setting value when storing the timer setting value to a predetermined position before Symbol verbal memory means (4)
Both were created by the & instruction creation means (10)
Stores the instruction end code corresponding to the stored & instruction.
And pay timer setting value generating means (11), output command creating means for storing the output name reads output names from the output information extracting storage means (7) in a predetermined position of the verbal memory means (4) ( 12) A functional language conversion device comprising: (3) Programmable controller (hereinafter P
C) in a tabular format that describes the circuit diagram in tabular format.
Road description method, Output description step described in multiple output description lines (1)
Described in a plurality of input description lines corresponding to the output.
Input description step (2), The output description step (1) comprises: Output name input step (a) for describing the name of the output signal
When, A timer input step (b) for describing a timer set value; An output condition input step (c) for describing an output condition; From the comment input step (d) that describes the comment
Become The input description step (2) includes: Input name input step (e) for describing the name of the input signal
When, Input symbol for signal input and inverted signal input
Means the inverted input symbol and the logical sum of the input signal
And the logical product of the input signal
An input to input either a logical AND symbol or a symbol consisting of
A logical input step (f); The input signal input in the input name input step (e)
Or the logic input in the input logic input step (f)
Positive logic symbol meaning that the operation result of the logical operation is used
And the input signal of the input name input means (e) or
The operation result of the logical operation input by the input logical input means (f)
Negative logic sign, meaning that the result is used inverted
Input condition input step (g) for inputting input conditions consisting of
When, From the comment input step (h) for inputting comments
Become The output condition input step (c) includes: The positive logical notation input in the input condition input step (g)
Sign or negative logical sign Substituting logical product into output signal
And the input condition input means (g)
The logical product of the positive logical symbol or negative logical symbol input in
Turn on the output signal when
The set signal meaning and the input condition input means (g).
The logical product of the input positive logical symbol or negative logical symbol is true.
When the output signal is turned off and false,
One of the signals consisting of
, A circuit description method in a tabular form, characterized in that: (4) The circuit diagram for PC was described in the table format.
A functional language that converts a tabular circuit description language into a functional language
A conversion method, A circuit storage procedure (3) for storing a tabular circuit description language; Tabular circuit description stored in the circuit storage procedure (3)
A language storage procedure for storing a functional language converted from a language
(4) and Tabular circuit description stored in the circuit storage procedure (3)
Output condition description field of multiple output description lines (1) of predicate language
The output condition is extracted from (c), and a plurality of input description lines (2)
Extract the input conditions from the input condition description field (g) of
Input / output condition extraction and storage procedure (5) for storing and storing; The input / output condition extraction and storage procedure (5)
Read the input condition and output condition, and read the input
Conditions and output conditions are input and output conditions of functional language
To the predetermined area of the language storage procedure (4).
I / O instruction creation procedure (6) to be stored in Tabular circuit description stored in the circuit storage procedure (3)
The output name is extracted from the output name description field (a) of the predicate language,
Extract the timer setting value from the description field (b)
Output information extraction and storage procedure for storing as output information (7)
When, The output stored in the output information extraction storage procedure (7)
Read the input name and the timer set value,
Function type word based on the output name and the timer set value.
Into a language timer instruction and a timer value name
Timer instruction creation procedure to store in a predetermined area
Order (8), Tabular circuit description stored in the circuit storage procedure (3)
Extract input logic from logic description field (f) of predicate language
Input logic extraction and storage procedure for converting to language and storing (9)
When, The input logic stored in the input logic extraction storage procedure (9)
Force logic and stored in the input / output condition extraction storage procedure (5).
Functional language based on said input and output conditions
Create & instruction and store the & instruction in the language storage procedure
(4) Stored in a predetermined area and created & instruction
And a command creation procedure (10) for storing The tie stored in the output information extraction storage procedure (7)
Reads the timer setting and stores the timer setting in the language storage
Stored in a predetermined position stored in the order (4),
The fact that it was created in the instruction creation procedure (10) is stored.
Set timer to store instruction end code corresponding to & instruction
Value creation procedure (11), Before being stored in the output information extraction storage procedure (7)
And reads the output name and stores the output name in the language storage
Steps for creating an output instruction stored in a predetermined position stored in order (4)
Order (12), A functional language conversion method comprising: (5) The tabular circuit description language is a programmer
Table that describes the circuit diagram for the cable controller in tabular format
A formal circuit description language, A plurality of output description lines (1) for describing an output;
Multiple input description lines to describe the input corresponding to the output
(2) The output description line (1) contains an output describing the name of the output signal.
Input field (a) and timer description that describes the timer setting value
Column (b) and an output condition description column for describing the output condition
(C) and a comment description field (d) for describing a comment.
Is established, The input description line (2) contains an input describing the name of the input signal.
Input name description field (e) and input logic description describing input logic
Column (f) and input condition description column (g) describing input conditions
And a comment description field (h) for writing comments
hand, A signal input for writing in the input logic description field (f)
Input symbol for force and input for inverted signal input.
Logic that means the logical sum of the power inversion symbol and the input signal
Logical notation that means the logical product of the sum symbol and the input signal
No. and The input for describing in the input condition description field (g)
Input signal in the name description field (e) or the input logic description field
Positive logic symbol meaning that the operation result of (f) is used
And the input signal of the input name description field (e) or the input theory
Performance of the description field (f) Inverts the result of the calculation
Having a negative logic sign to taste, The input for describing in the output condition description column (c)
Logical product of the positive and negative logical symbols in the condition description field (g)
To the output signal,
Of the positive logical symbol or the negative logical symbol in the input condition description field (g).
Turn on the output signal when the logical product is true, and leave it unprocessed when the logical product is false
And the input symbol description field
When the logical product of the positive and negative logical symbols in (g) is true
Reset the output signal to OFF, meaning no processing when false
With a sign, 5. The method according to claim 4, wherein: 6. The tabular circuit description language is based on the input theory.
Input meaning the input of the signal described in the logical description field (f).
The force symbol is represented by an arrow, indicating that the input is the inverse of the signal.
The force reversal symbol is represented by an arrow with a black circle added in the center, and
The logical sum symbol signifying the sum is represented by a single vertical line,
The logical product symbol that represents logical product is represented by two vertical lines in parallel.
The write condition described in the output condition description column (c) is described.
Symbol is represented by "W" and the set symbol is represented by "S".
The reset symbol is represented by "R", The input condition description field
The positive logic symbol described in (g) is represented by “○”, and
The negative logic symbol is represented by "x". 6. The functional language conversion method according to claim 5, wherein: